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authorYann Herklotz <git@yannherklotz.com>2021-07-23 12:56:07 +0200
committerYann Herklotz <git@yannherklotz.com>2021-07-23 12:56:07 +0200
commitf7bffa59bfd1eb4bece108ce63459670ac1c183b (patch)
tree4cbb030bb94d91806d3c9bd995e14c81583e828f
parent7cdea045e75f2246243461ae0579c3dfe27f8afb (diff)
downloadverismith-f7bffa59bfd1eb4bece108ce63459670ac1c183b.tar.gz
verismith-f7bffa59bfd1eb4bece108ce63459670ac1c183b.zip
Add paranthesis
-rw-r--r--src/Verismith/Verilog/CodeGen.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Verismith/Verilog/CodeGen.hs b/src/Verismith/Verilog/CodeGen.hs
index 7f5dd46..62102c3 100644
--- a/src/Verismith/Verilog/CodeGen.hs
+++ b/src/Verismith/Verilog/CodeGen.hs
@@ -60,7 +60,7 @@ moduleDecl (ModDecl i outP inP items ps) =
modI = vsep $ moduleItem <$> items
outIn = outP ++ inP
params [] = ""
- params (p : pps) = hcat ["#", paramList (p :| pps)]
+ params (p : pps) = hcat ["#(", paramList (p :| pps), ")"]
moduleDecl (ModDeclAnn a m) = sep [hsep ["/*", pretty $ show a, "*/"], moduleDecl m]
-- | Generates a parameter list. Can only be called with a 'NonEmpty' list.