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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-05 15:21:06 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-05 15:21:06 +0000 |
| commit | bdf9a79502ffd79cdea9dc3678ee0f61b16fdea9 (patch) | |
| tree | c75df5fb421c8ebedc34b445e88d4a7083a36bdf /app | |
| parent | 02b5ed9984e0efd4a5032309dfb709b1fc30f876 (diff) | |
| download | verismith-bdf9a79502ffd79cdea9dc3678ee0f61b16fdea9.tar.gz verismith-bdf9a79502ffd79cdea9dc3678ee0f61b16fdea9.zip | |
Add completely random module generation
Diffstat (limited to 'app')
| -rw-r--r-- | app/Simulation.hs | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/app/Simulation.hs b/app/Simulation.hs index 675a7dc..28950c2 100644 --- a/app/Simulation.hs +++ b/app/Simulation.hs @@ -55,7 +55,8 @@ runSimulation = do let circ = head $ (nestUpTo 30 . generateAST $ Circuit gr) ^.. getVerilogSrc . traverse . getDescription rand <- genRandom 20 - val <- shelly $ runSim defaultIcarus (initMod circ) rand + rand2 <- QC.generate (randomMod 10 100) + val <- shelly $ runSim defaultIcarus (rand2) rand T.putStrLn . decodeUtf8 $ (L.toStrict . toLazyByteString . byteStringHex $ val) onFailure :: Text -> RunFailed -> Sh () |