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authorYann Herklotz <git@yannherklotz.com>2019-11-14 16:49:42 +0000
committerYann Herklotz <git@yannherklotz.com>2019-11-14 16:49:42 +0000
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# Expression evaluates to 1'bx instead of expected 1'b0
-[ [Issue 283](https://github.com/steveicarus/iverilog/issues/283) ]
+[ Not fixed | [Issue 283](https://github.com/steveicarus/iverilog/issues/283) ]
+
+## Affected versions
+
+- Icarus Verilog 10.0
+- Icarus Verilog 10.3
+
+## Description
The following code outputs and assigns `y` to 1'bx instead of 1'b0. This happens in iverilog version 10.3 and also happens in version 10.0 (11/23/14) on edaplayground. However, this seems to execute fine in version 9.6 and 9.7 on edaplayground.
@@ -35,4 +42,3 @@ iverilog testbench.v -o im && ./im
the output is `x` instead of `0`.
If the always block is not used, and the expression is assigned to `y` directly, the result is the expected 1'b0. Any changes to the expression seems to fix the result as well.
-