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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 19:44:40 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 19:44:40 +0100 |
| commit | cabb2cec0bde620c49b1d7a36cd8226f579c1023 (patch) | |
| tree | a3f0cfcd487f5c58179706d75f5ef70917c9a760 /src/Test/VeriFuzz/Graph | |
| parent | 9f2bb8aff3198d36ac847dde67e4e630cd8b889f (diff) | |
| download | verismith-cabb2cec0bde620c49b1d7a36cd8226f579c1023.tar.gz verismith-cabb2cec0bde620c49b1d7a36cd8226f579c1023.zip | |
[Fix #13, Fix #15] Fix type errors and add inst functions
Diffstat (limited to 'src/Test/VeriFuzz/Graph')
| -rw-r--r-- | src/Test/VeriFuzz/Graph/ASTGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs index cf996de..3c000ea 100644 --- a/src/Test/VeriFuzz/Graph/ASTGen.hs +++ b/src/Test/VeriFuzz/Graph/ASTGen.hs @@ -77,7 +77,7 @@ genModuleDeclAST c = ModDecl id output ports items where id = Identifier "gen_module" ports = genPortsAST inputsC c - output = Just $ Port (PortNet Wire) 1 "y" + output = [Port (PortNet Wire) 1 "y"] items = genAssignAST c generateAST :: Circuit -> VerilogSrc |