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authorYann Herklotz <git@ymhg.org>2019-04-02 18:16:21 +0100
committerYann Herklotz <git@ymhg.org>2019-04-02 18:16:21 +0100
commitc0c799ab3f79c370e4c33b8f824489ce8b1c96ec (patch)
tree042f235cdf458e6bf5330a477435d4b34bee7859 /src/VeriFuzz/Icarus.hs
parent1ef0455ddad821c2ddf64d451e99b8b5508c39c5 (diff)
downloadverismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.tar.gz
verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.zip
Rename to Verilog
Diffstat (limited to 'src/VeriFuzz/Icarus.hs')
-rw-r--r--src/VeriFuzz/Icarus.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Icarus.hs b/src/VeriFuzz/Icarus.hs
index 32c4013..47159b3 100644
--- a/src/VeriFuzz/Icarus.hs
+++ b/src/VeriFuzz/Icarus.hs
@@ -89,7 +89,7 @@ runSimIcarus sim rinfo bss = do
<> (SysTaskEnable $ Task "finish" [])
]
let newtb = instantiateMod m tb
- let modWithTb = VerilogSrc $ Description <$> [newtb, m]
+ let modWithTb = Verilog $ Description <$> [newtb, m]
writefile "main.v" $ genSource modWithTb
runSimWithFile sim "main.v" bss
where m = rinfo ^. mainModule