| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -107/+0 |
| * | Rename to Verilog | Yann Herklotz | 2019-04-02 | 1 | -1/+1 |
| * | Change license name | Yann Herklotz | 2019-03-30 | 1 | -1/+1 |
| * | Rename Stmnt to Statement | Yann Herklotz Grave | 2019-03-06 | 1 | -2/+2 |
| * | Add lens to access main module in SourceInfo | Yann Herklotz Grave | 2019-03-01 | 1 | -1/+2 |
| * | [Fix #37] Fix types in the simulator with more general functions | Yann Herklotz Grave | 2019-03-01 | 1 | -8/+8 |
| * | Reformat using brittany | Yann Herklotz Grave | 2019-02-25 | 1 | -2/+4 |
| * | Indent by 4 | Yann Herklotz Grave | 2019-02-17 | 1 | -29/+32 |
| * | Brittany formatting | Yann Herklotz Grave | 2019-02-17 | 1 | -15/+13 |
| * | Fix lint errors | Yann Herklotz Grave | 2019-02-16 | 1 | -3/+2 |
| * | Add runner for verilog file | Yann Herklotz | 2019-02-07 | 1 | -3/+10 |
| * | Add hashing of bytestring output | Yann Herklotz | 2019-02-05 | 1 | -16/+18 |
| * | Add conversion to bytestring | Yann Herklotz | 2019-02-05 | 1 | -6/+35 |
| * | Try to add logging | Yann Herklotz | 2019-02-02 | 1 | -1/+1 |
| * | Fix all the compile and test errors | Yann Herklotz | 2019-02-01 | 1 | -5/+8 |
| * | Fix imports | Yann Herklotz | 2019-02-01 | 1 | -9/+9 |
| * | More restructuring | Yann Herklotz | 2019-02-01 | 1 | -0/+63 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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