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| author | Yann Herklotz <git@yannherklotz.com> | 2020-05-11 18:29:06 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-05-11 18:29:06 +0100 |
| commit | 805f67c07cc15d784078b00a84f4055f84016cec (patch) | |
| tree | 15c93eb5102e3813515d41204deb3f86f78f1994 /src/Verismith/Tool/Template.hs | |
| parent | 54bb059ab6955f58f4a4b95cdd080775a56bc793 (diff) | |
| download | verismith-805f67c07cc15d784078b00a84f4055f84016cec.tar.gz verismith-805f67c07cc15d784078b00a84f4055f84016cec.zip | |
Fix types with annotations
Diffstat (limited to 'src/Verismith/Tool/Template.hs')
| -rw-r--r-- | src/Verismith/Tool/Template.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs index a2e0675..5a20ff5 100644 --- a/src/Verismith/Tool/Template.hs +++ b/src/Verismith/Tool/Template.hs @@ -172,7 +172,7 @@ sbyConfig mt datadir sim1 sim2 (SourceInfo top _) = T.unlines <$> deps readL = T.intercalate "\n" $ mappend "read -formal " <$> deps -icarusTestbench :: (Synthesiser a) => FilePath -> (Verilog ann) -> a -> Text +icarusTestbench :: (Synthesiser a, Show ann) => FilePath -> (Verilog ann) -> a -> Text icarusTestbench datadir t synth1 = T.unlines [ "`include \"" <> ddir <> "/data/cells_cmos.v\"" , "`include \"" <> ddir <> "/data/cells_cyclone_v.v\"" |