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-rw-r--r--src/Verismith/Tool/Template.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs
index a2e0675..5a20ff5 100644
--- a/src/Verismith/Tool/Template.hs
+++ b/src/Verismith/Tool/Template.hs
@@ -172,7 +172,7 @@ sbyConfig mt datadir sim1 sim2 (SourceInfo top _) = T.unlines
<$> deps
readL = T.intercalate "\n" $ mappend "read -formal " <$> deps
-icarusTestbench :: (Synthesiser a) => FilePath -> (Verilog ann) -> a -> Text
+icarusTestbench :: (Synthesiser a, Show ann) => FilePath -> (Verilog ann) -> a -> Text
icarusTestbench datadir t synth1 = T.unlines
[ "`include \"" <> ddir <> "/data/cells_cmos.v\""
, "`include \"" <> ddir <> "/data/cells_cyclone_v.v\""