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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-02 13:44:24 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-02 13:44:24 +0000 |
| commit | 686bc953c50cf23b96dba4f182e8005289e71b98 (patch) | |
| tree | b705c856a233e4fdc444d2b252dd4b87873b6318 /src | |
| parent | e14fbc146d93bdebbf22c0a9ceb58ee3459de4b7 (diff) | |
| download | verismith-686bc953c50cf23b96dba4f182e8005289e71b98.tar.gz verismith-686bc953c50cf23b96dba4f182e8005289e71b98.zip | |
Add mutation for declaration
Diffstat (limited to 'src')
| -rw-r--r-- | src/VeriFuzz/Mutate.hs | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/VeriFuzz/Mutate.hs b/src/VeriFuzz/Mutate.hs index 705e607..7295b63 100644 --- a/src/VeriFuzz/Mutate.hs +++ b/src/VeriFuzz/Mutate.hs @@ -166,3 +166,8 @@ makeTopAssert = (modItems %~ (++ [assert])) . (modInPorts %~ addClk) . makeTop 2 [TaskEnable $ Task "assert" [BinOp (Id "y_1") BinEq (Id "y_2")]] e = EPosEdge "clk" addClk = ((Port Wire 1 "clk") :) + +declareMod :: [Port] -> ModDecl -> ModDecl +declareMod ports = modItems %~ (decl++) + where + decl = Decl Nothing <$> ports |