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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-01 14:41:16 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-01 14:41:16 +0100 |
| commit | 99d2932e1b4357f4e0aa303a29d08bfd81977a9e (patch) | |
| tree | cebe6c8dc8ce7fde354681ae8f5224f02b56e0eb /src | |
| parent | 531f39d5dabb752b3f3c2599977442b0c8484444 (diff) | |
| download | verismith-99d2932e1b4357f4e0aa303a29d08bfd81977a9e.tar.gz verismith-99d2932e1b4357f4e0aa303a29d08bfd81977a9e.zip | |
Formatting
Diffstat (limited to 'src')
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/AST.hs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs index 288fb2e..6f6e930 100644 --- a/src/Test/VeriFuzz/Verilog/AST.hs +++ b/src/Test/VeriFuzz/Verilog/AST.hs @@ -210,9 +210,9 @@ data ContAssign = ContAssign { _contAssignNetLVal :: Identifier } deriving (Eq) -- | Stmnts in Verilog. -data Stmnt = TimeCtrl { _statDelay :: Delay - , _statDStat :: Maybe Stmnt - } -- ^ Time control (@#NUM@) +data Stmnt = TimeCtrl { _statDelay :: Delay + , _statDStat :: Maybe Stmnt + } -- ^ Time control (@#NUM@) | EventCtrl { _statEvent :: Event , _statEStat :: Maybe Stmnt } |