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Diffstat (limited to 'src/Verismith/Verilog/Internal.hs')
| -rw-r--r-- | src/Verismith/Verilog/Internal.hs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/Verismith/Verilog/Internal.hs b/src/Verismith/Verilog/Internal.hs index d06fc5f..ce4cbce 100644 --- a/src/Verismith/Verilog/Internal.hs +++ b/src/Verismith/Verilog/Internal.hs @@ -62,6 +62,7 @@ testBench = wireDecl "c", ModInst "and" + [] "and_gate" [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"], Initial $ |