| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix parser for a larger set of inputs | Yann Herklotz | 2021-04-26 | 1 | -0/+1 |
| * | Format with ormolu | Yann Herklotz | 2020-05-12 | 1 | -41/+42 |
| * | WIP changes to the AST types | Yann Herklotz | 2020-03-16 | 1 | -9/+9 |
| * | Update license notices | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
| * | Rename main modules | Yann Herklotz | 2019-09-18 | 1 | -0/+93 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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