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| author | Yann Herklotz <git@yannherklotz.com> | 2021-04-26 11:38:55 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-04-26 11:38:55 +0100 |
| commit | 326048aeac6f846d8ad52c2a66f73219426f8bea (patch) | |
| tree | a86c5a045e47900d9d78be680cf3e43a0454131b /src/Verismith/Verilog/Internal.hs | |
| parent | 773acb06f15d49b810b76508505f5df5a84f8172 (diff) | |
| download | verismith-326048aeac6f846d8ad52c2a66f73219426f8bea.tar.gz verismith-326048aeac6f846d8ad52c2a66f73219426f8bea.zip | |
Fix parser for a larger set of inputs
- Added support for parameter parsing
- Added support for parameter declaration for instantiations
- Fix parsing of @(*)
- Fix parsing of `timescale
- Add parsing for case statements with default
Diffstat (limited to 'src/Verismith/Verilog/Internal.hs')
| -rw-r--r-- | src/Verismith/Verilog/Internal.hs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/Verismith/Verilog/Internal.hs b/src/Verismith/Verilog/Internal.hs index d06fc5f..ce4cbce 100644 --- a/src/Verismith/Verilog/Internal.hs +++ b/src/Verismith/Verilog/Internal.hs @@ -62,6 +62,7 @@ testBench = wireDecl "c", ModInst "and" + [] "and_gate" [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"], Initial $ |