diff options
Diffstat (limited to 'test')
-rw-r--r-- | test/Reduce.hs | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/test/Reduce.hs b/test/Reduce.hs index bc4bbc3..be5ead3 100644 --- a/test/Reduce.hs +++ b/test/Reduce.hs @@ -29,6 +29,7 @@ reduceUnitTests = testGroup [ moduleReducerTest , modItemReduceTest , halveStatementsTest + , statementReducerTest , activeWireTest , cleanTest , cleanAllTest @@ -372,6 +373,94 @@ endmodule |]) -- brittany-disable-next-binding +statementReducerTest :: TestTree +statementReducerTest = testCase "Statement reducer" $ do + GenVerilog <$> halveStatements "top" srcInfo1 @?= fmap GenVerilog golden1 + GenVerilog <$> halveStatements "top" srcInfo2 @?= fmap GenVerilog golden2 + where + srcInfo1 = SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + a <= 1; + b <= 2; + c <= 3; + d <= 4; + end + + always @(posedge clk) begin + a <= 1; + b <= 2; + c <= 3; + d <= 4; + end +endmodule +|] + golden1 = Dual (SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + a <= 1; + b <= 2; + end + + always @(posedge clk) begin + a <= 1; + b <= 2; + end +endmodule +|]) $ SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + c <= 3; + d <= 4; + end + + always @(posedge clk) begin + c <= 3; + d <= 4; + end +endmodule +|] + srcInfo2 = SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + if (x) + y <= 2; + else + y <= 3; + end +endmodule +|] + golden2 = Dual (SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) + y <= 2; +endmodule +|]) $ SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) + y <= 3; +endmodule +|] + +-- brittany-disable-next-binding moduleReducerTest :: TestTree moduleReducerTest = testCase "Module reducer" $ do halveModules srcInfo1 @?= golden1 |