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| * | Add reduction stage back | Yann Herklotz | 2019-12-26 | 1 | -0/+1 | |
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| * | Bump to version 0.6.0.0v0.6.0.0 | Yann Herklotz | 2019-12-25 | 1 | -2/+2 | |
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| * | Add synthesis tools | Yann Herklotz | 2019-12-19 | 1 | -0/+3 | |
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| * | Add links | Yann Herklotz | 2019-12-19 | 1 | -4/+4 | |
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| * | Add external dependencies to README | Yann Herklotz | 2019-12-19 | 1 | -2/+7 | |
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| * | Add new Yosys report | Yann Herklotz | 2019-12-13 | 2 | -0/+16 | |
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| * | Add quartuslight | Yann Herklotz | 2019-12-10 | 1 | -2/+2 | |
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| * | Do not run counter example if no rerunner is specified | Yann Herklotz | 2019-12-03 | 7 | -26/+40 | |
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| * | Set aigsmt to none | Yann Herklotz | 2019-12-03 | 1 | -1/+1 | |
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| * | More minimisation | Yann Herklotz | 2019-12-03 | 2 | -3/+11 | |
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| * | Move to resourcesv0.5.0.1fpga20 | Yann Herklotz | 2019-11-26 | 1 | -6/+10 | |
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| * | Add more information in README | Yann Herklotz | 2019-11-26 | 1 | -2/+2 | |
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| * | Update link to paper | Yann Herklotz | 2019-11-26 | 1 | -1/+1 | |
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| * | Update links in the readme | Yann Herklotz | 2019-11-26 | 1 | -1/+6 | |
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| * | Add new yosys report | Yann Herklotz | 2019-11-26 | 1 | -0/+80 | |
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| * | Add different identifier for forloops | Yann Herklotz | 2019-11-24 | 1 | -15/+17 | |
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| * | Upgrade version to v0.5.0.0v0.5.0.0 | Yann Herklotz | 2019-11-24 | 1 | -2/+2 | |
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| * | Add ModConnNamed in testbench | Yann Herklotz | 2019-11-24 | 1 | -1/+1 | |
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| * | Add extension to simulation reduction | Yann Herklotz | 2019-11-24 | 1 | -1/+1 | |
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| * | Fix more changes to for loops | Yann Herklotz | 2019-11-24 | 1 | -1/+1 | |
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| * | Do not mutate the expression in the for loop | Yann Herklotz | 2019-11-24 | 1 | -1/+1 | |
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| * | Fix build | Yann Herklotz | 2019-11-24 | 1 | -1/+1 | |
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| * | Add output of v file during reduction | Yann Herklotz | 2019-11-24 | 2 | -35/+20 | |
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| * | Show the result as it is run | Yann Herklotz | 2019-11-24 | 1 | -4/+4 | |
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| * | Add cross-check between netlists | Yann Herklotz | 2019-11-24 | 3 | -11/+16 | |
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| * | Merge branch 'master' of github.com:ymherklotz/verismith | Yann Herklotz | 2019-11-24 | 2 | -2/+2 | |
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| | * | Icarus bug fixed | Yann Herklotz | 2019-11-16 | 2 | -2/+2 | |
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| * | | Fix counter-example simulation run | Yann Herklotz | 2019-11-24 | 1 | -1/+1 | |
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| * | Support proper Quartus Pro version | Yann Herklotz | 2019-11-14 | 7 | -41/+168 | |
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| * | Add Cyclone 10 LP and GX | Yann Herklotz | 2019-11-14 | 1 | -33/+473 | |
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| * | Update bug | Yann Herklotz | 2019-11-14 | 1 | -0/+10 | |
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| * | Add first quartus bug | Yann Herklotz | 2019-11-14 | 1 | -0/+19 | |
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| * | Update description | Yann Herklotz | 2019-11-14 | 1 | -1/+1 | |
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| * | Add yosys 0.9 bug | Yann Herklotz | 2019-11-14 | 1 | -0/+60 | |
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| * | Update bug reports | Yann Herklotz | 2019-11-14 | 11 | -28/+97 | |
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| * | Add proper reports to bugs | Yann Herklotz | 2019-11-14 | 34 | -2091/+810 | |
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| * | Add delay to finish | Yann Herklotz | 2019-11-14 | 1 | -1/+1 | |
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| * | Add z3 as default equivalence check with ABC | Yann Herklotz | 2019-11-14 | 1 | -0/+1 | |
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| * | Update x | Yann Herklotz | 2019-11-13 | 1 | -6/+6 | |
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| * | Add icarus verilog bug | Yann Herklotz | 2019-11-13 | 1 | -0/+6 | |
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| * | Add enable to dffeas | Yann Herklotz | 2019-11-12 | 1 | -8/+10 | |
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| * | Add reduction for simulation failures | Yann Herklotz | 2019-11-12 | 7 | -72/+176 | |
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| * | Use text to store counter-example | Yann Herklotz | 2019-11-12 | 1 | -15/+15 | |
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| * | Remove second trigger for always block | Yann Herklotz | 2019-11-12 | 1 | -1/+1 | |
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| * | Add counter example parsing | Yann Herklotz | 2019-11-10 | 8 | -47/+165 | |
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| * | Classify Verilog correctly | Yann Herklotz | 2019-11-05 | 1 | -1/+2 | |
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| * | Update reducer script | Yann Herklotz | 2019-11-05 | 1 | -8/+22 | |
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| * | Add reduction pass to remove constants from concat | Yann Herklotz | 2019-11-05 | 5 | -15/+88 | |
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| * | Add asynchronous load | Yann Herklotz | 2019-11-05 | 1 | -2/+6 | |
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| * | Add support for Quartus using projects | Yann Herklotz | 2019-11-04 | 2 | -17/+45 | |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
| aboutsummaryrefslogtreecommitdiffstats |