verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Large refactor with passing tests	Yann Herklotz	2019-04-02	1	-109/+0
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*	Rename to Verilog	Yann Herklotz	2019-04-02	1	-1/+1
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*	Change license name	Yann Herklotz	2019-03-30	1	-1/+1
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*	Add lens to access main module in SourceInfo	Yann Herklotz Grave	2019-03-01	1	-2/+8
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*	[Fix #37] Fix types in the simulator with more general functions	Yann Herklotz Grave	2019-03-01	1	-32/+42
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*	Reformat using brittany	Yann Herklotz Grave	2019-02-25	1	-6/+13
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*	Indent by 4	Yann Herklotz Grave	2019-02-17	1	-33/+34
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*	Brittany formatting	Yann Herklotz Grave	2019-02-17	1	-3/+2
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*	Fix logging	Yann Herklotz	2019-02-03	1	-1/+1
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*	Add timeout and timeout check	Yann Herklotz	2019-02-02	1	-1/+1
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*	Try to add logging	Yann Herklotz	2019-02-02	1	-7/+13
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*	Fix all the compile and test errors	Yann Herklotz	2019-02-01	1	-9/+8
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*	Fix imports	Yann Herklotz	2019-02-01	1	-2/+2
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*	More restructuring	Yann Herklotz	2019-02-01	1	-0/+81