| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Format with ormolu | Yann Herklotz | 2020-05-12 | 1 | -158/+170 |
| * | Fix types with annotations | Yann Herklotz | 2020-05-11 | 1 | -12/+15 |
| * | WIP changes to the AST types | Yann Herklotz | 2020-03-16 | 1 | -15/+15 |
| * | Fix spacing in the generated Verilog | Yann Herklotz | 2020-03-03 | 1 | -16/+20 |
| * | Add case statement to the AST | Yann Herklotz | 2020-03-03 | 1 | -1/+10 |
| * | Update license notices | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
| * | Add comment to code generation | Yann Herklotz | 2019-10-25 | 1 | -1/+1 |
| * | Rename main modules | Yann Herklotz | 2019-09-18 | 1 | -0/+341 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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