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+title = "Loop pipelining"
+author = "Yann Herklotz"
+tags = []
+categories = []
+backlinks = ["3c1", "3a8", "2e1f", "2b2", "1c5", "1c"]
+forwardlinks = ["3c1", "1c7", "1c6a"]
+zettelid = "1c6"
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+
+Loop pipelining is a great optimisation for VLIW processors that have
+parallel constructs. The main idea is to identify loops where reordering
+the instructions would improve the instruction parallelism inside of the
+loops.
+
+Notes on verifying loop pipelining can be found in [\#3c1].
+
+  [\#3c1]: /zettel/3c1