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Diffstat (limited to 'content/zettel/1c6.md')
| -rw-r--r-- | content/zettel/1c6.md | 18 |
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diff --git a/content/zettel/1c6.md b/content/zettel/1c6.md new file mode 100644 index 0000000..c1f835d --- /dev/null +++ b/content/zettel/1c6.md @@ -0,0 +1,18 @@ ++++ +title = "Loop pipelining" +author = "Yann Herklotz" +tags = [] +categories = [] +backlinks = ["3c1", "3a8", "2e1f", "2b2", "1c5", "1c"] +forwardlinks = ["3c1", "1c7", "1c6a"] +zettelid = "1c6" ++++ + +Loop pipelining is a great optimisation for VLIW processors that have +parallel constructs. The main idea is to identify loops where reordering +the instructions would improve the instruction parallelism inside of the +loops. + +Notes on verifying loop pipelining can be found in [\#3c1]. + + [\#3c1]: /zettel/3c1 |