diff options
| author | zedarider <ymherklotz@gmail.com> | 2016-02-26 22:46:09 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-02-26 22:46:09 +0000 |
| commit | 1684a53b7f5837d0c4e0d487e3fadccb69fe2c2a (patch) | |
| tree | a17efcef6963d3047c8ced65c24f3256ac22f318 /glue_logic | |
| download | FPGA-2015-1684a53b7f5837d0c4e0d487e3fadccb69fe2c2a.tar.gz FPGA-2015-1684a53b7f5837d0c4e0d487e3fadccb69fe2c2a.zip | |
adding fpga lab projects
Diffstat (limited to 'glue_logic')
88 files changed, 3321 insertions, 0 deletions
diff --git a/glue_logic/db/glu_Logic.(0).cnf.cdb b/glue_logic/db/glu_Logic.(0).cnf.cdb Binary files differnew file mode 100644 index 0000000..fa33eea --- /dev/null +++ b/glue_logic/db/glu_Logic.(0).cnf.cdb diff --git a/glue_logic/db/glu_Logic.(0).cnf.hdb b/glue_logic/db/glu_Logic.(0).cnf.hdb Binary files differnew file mode 100644 index 0000000..208b17b --- /dev/null +++ b/glue_logic/db/glu_Logic.(0).cnf.hdb diff --git a/glue_logic/db/glu_Logic.asm.qmsg b/glue_logic/db/glu_Logic.asm.qmsg new file mode 100644 index 0000000..c0f11df --- /dev/null +++ b/glue_logic/db/glu_Logic.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455635769000 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635769004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:16:08 2016 " "Processing started: Tue Feb 16 15:16:08 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635769004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455635769004 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic " "Command: quartus_asm --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455635769004 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455635769976 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455635770011 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:10 2016 " "Processing ended: Tue Feb 16 15:16:10 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455635770639 ""} diff --git a/glue_logic/db/glu_Logic.asm.rdb b/glue_logic/db/glu_Logic.asm.rdb Binary files differnew file mode 100644 index 0000000..679bc42 --- /dev/null +++ b/glue_logic/db/glu_Logic.asm.rdb diff --git a/glue_logic/db/glu_Logic.cbx.xml b/glue_logic/db/glu_Logic.cbx.xml new file mode 100644 index 0000000..d7104e1 --- /dev/null +++ b/glue_logic/db/glu_Logic.cbx.xml @@ -0,0 +1,5 @@ +<?xml version="1.0" ?> +<LOG_ROOT> + <PROJECT NAME="glu_Logic"> + </PROJECT> +</LOG_ROOT> diff --git a/glue_logic/db/glu_Logic.cmp.idb b/glue_logic/db/glu_Logic.cmp.idb Binary files differnew file mode 100644 index 0000000..039a95c --- /dev/null +++ b/glue_logic/db/glu_Logic.cmp.idb diff --git a/glue_logic/db/glu_Logic.cmp.kpt b/glue_logic/db/glu_Logic.cmp.kpt Binary files differnew file mode 100644 index 0000000..c36d492 --- /dev/null +++ b/glue_logic/db/glu_Logic.cmp.kpt diff --git a/glue_logic/db/glu_Logic.cmp.rdb b/glue_logic/db/glu_Logic.cmp.rdb Binary files differnew file mode 100644 index 0000000..d675571 --- /dev/null +++ b/glue_logic/db/glu_Logic.cmp.rdb diff --git a/glue_logic/db/glu_Logic.cmp_merge.kpt b/glue_logic/db/glu_Logic.cmp_merge.kpt Binary files differnew file mode 100644 index 0000000..432cbbd --- /dev/null +++ b/glue_logic/db/glu_Logic.cmp_merge.kpt diff --git a/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd Binary files differnew file mode 100644 index 0000000..e765b81 --- /dev/null +++ b/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd diff --git a/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd Binary files differnew file mode 100644 index 0000000..dab2df3 --- /dev/null +++ b/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd diff --git a/glue_logic/db/glu_Logic.db_info b/glue_logic/db/glu_Logic.db_info new file mode 100644 index 0000000..cda06f9 --- /dev/null +++ b/glue_logic/db/glu_Logic.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +Version_Index = 302049280 +Creation_Time = Tue Feb 16 15:10:26 2016 diff --git a/glue_logic/db/glu_Logic.fit.qmsg b/glue_logic/db/glu_Logic.fit.qmsg new file mode 100644 index 0000000..3457b41 --- /dev/null +++ b/glue_logic/db/glu_Logic.fit.qmsg @@ -0,0 +1,44 @@ +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1455635758479 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "glu_Logic EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"glu_Logic\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1455635758896 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759013 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759014 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759014 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455635759095 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455635759287 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 49 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 51 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 53 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 55 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 57 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455635759296 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455635759303 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "glu_Logic.sdc " "Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455635760262 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455635760265 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1455635760268 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1455635760270 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455635760273 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455635760276 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455635760283 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455635760286 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455635760288 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455635760291 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455635760294 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455635760296 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1455635760298 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1455635760301 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455635760303 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455635760305 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455635760310 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455635760310 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635760325 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455635760952 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635760998 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455635761007 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455635761055 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635761057 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455635761406 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" { } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455635761783 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455635761783 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635761859 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455635761870 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455635761870 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455635761870 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455635761881 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455635761988 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455635762283 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455635762365 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455635762664 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635763015 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/EIE1 FPGA/output_files/glu_Logic.fit.smsg " "Generated suppressed messages file /EIE1 FPGA/output_files/glu_Logic.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455635763758 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1111 " "Peak virtual memory: 1111 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:05 2016 " "Processing ended: Tue Feb 16 15:16:05 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455635765258 ""} diff --git a/glue_logic/db/glu_Logic.hier_info b/glue_logic/db/glu_Logic.hier_info new file mode 100644 index 0000000..99591ae --- /dev/null +++ b/glue_logic/db/glu_Logic.hier_info @@ -0,0 +1,23 @@ +|glu_Logic +Output[0] <= Input[0].DB_MAX_OUTPUT_PORT_TYPE +Output[1] <= Input[1].DB_MAX_OUTPUT_PORT_TYPE +Output[2] <= Input[2].DB_MAX_OUTPUT_PORT_TYPE +Output[3] <= Input[3].DB_MAX_OUTPUT_PORT_TYPE +Output[4] <= Input[4].DB_MAX_OUTPUT_PORT_TYPE +Output[5] <= Input[5].DB_MAX_OUTPUT_PORT_TYPE +Output[6] <= Input[6].DB_MAX_OUTPUT_PORT_TYPE +Output[7] <= Input[7].DB_MAX_OUTPUT_PORT_TYPE +Output[8] <= Input[8].DB_MAX_OUTPUT_PORT_TYPE +Output[9] <= Input[9].DB_MAX_OUTPUT_PORT_TYPE +Input[0] => Output[0].DATAIN +Input[1] => Output[1].DATAIN +Input[2] => Output[2].DATAIN +Input[3] => Output[3].DATAIN +Input[4] => Output[4].DATAIN +Input[5] => Output[5].DATAIN +Input[6] => Output[6].DATAIN +Input[7] => Output[7].DATAIN +Input[8] => Output[8].DATAIN +Input[9] => Output[9].DATAIN + + diff --git a/glue_logic/db/glu_Logic.hif b/glue_logic/db/glu_Logic.hif Binary files differnew file mode 100644 index 0000000..baa8ed2 --- /dev/null +++ b/glue_logic/db/glu_Logic.hif diff --git a/glue_logic/db/glu_Logic.ipinfo b/glue_logic/db/glu_Logic.ipinfo Binary files differnew file mode 100644 index 0000000..3560eab --- /dev/null +++ b/glue_logic/db/glu_Logic.ipinfo diff --git a/glue_logic/db/glu_Logic.lpc.html b/glue_logic/db/glu_Logic.lpc.html new file mode 100644 index 0000000..fbc5ab5 --- /dev/null +++ b/glue_logic/db/glu_Logic.lpc.html @@ -0,0 +1,18 @@ +<TABLE> +<TR bgcolor="#C0C0C0"> +<TH>Hierarchy</TH> +<TH>Input</TH> +<TH>Constant Input</TH> +<TH>Unused Input</TH> +<TH>Floating Input</TH> +<TH>Output</TH> +<TH>Constant Output</TH> +<TH>Unused Output</TH> +<TH>Floating Output</TH> +<TH>Bidir</TH> +<TH>Constant Bidir</TH> +<TH>Unused Bidir</TH> +<TH>Input only Bidir</TH> +<TH>Output only Bidir</TH> +</TR> +</TABLE> diff --git a/glue_logic/db/glu_Logic.lpc.rdb b/glue_logic/db/glu_Logic.lpc.rdb Binary files differnew file mode 100644 index 0000000..da6029a --- /dev/null +++ b/glue_logic/db/glu_Logic.lpc.rdb diff --git a/glue_logic/db/glu_Logic.lpc.txt b/glue_logic/db/glu_Logic.lpc.txt new file mode 100644 index 0000000..a463804 --- /dev/null +++ b/glue_logic/db/glu_Logic.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/glue_logic/db/glu_Logic.map.ammdb b/glue_logic/db/glu_Logic.map.ammdb Binary files differnew file mode 100644 index 0000000..8b8ff04 --- /dev/null +++ b/glue_logic/db/glu_Logic.map.ammdb diff --git a/glue_logic/db/glu_Logic.map.bpm b/glue_logic/db/glu_Logic.map.bpm Binary files differnew file mode 100644 index 0000000..7d25716 --- /dev/null +++ b/glue_logic/db/glu_Logic.map.bpm diff --git a/glue_logic/db/glu_Logic.map.cdb b/glue_logic/db/glu_Logic.map.cdb Binary files differnew file mode 100644 index 0000000..bd11818 --- /dev/null +++ b/glue_logic/db/glu_Logic.map.cdb diff --git a/glue_logic/db/glu_Logic.map.hdb b/glue_logic/db/glu_Logic.map.hdb Binary files differnew file mode 100644 index 0000000..e76e1e4 --- /dev/null +++ b/glue_logic/db/glu_Logic.map.hdb diff --git a/glue_logic/db/glu_Logic.map.kpt b/glue_logic/db/glu_Logic.map.kpt Binary files differnew file mode 100644 index 0000000..8a58f05 --- /dev/null +++ b/glue_logic/db/glu_Logic.map.kpt diff --git a/glue_logic/db/glu_Logic.map.logdb b/glue_logic/db/glu_Logic.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/glue_logic/db/glu_Logic.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/glue_logic/db/glu_Logic.map.qmsg b/glue_logic/db/glu_Logic.map.qmsg new file mode 100644 index 0000000..010dfc6 --- /dev/null +++ b/glue_logic/db/glu_Logic.map.qmsg @@ -0,0 +1,9 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455635783353 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635783359 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:16:22 2016 " "Processing started: Tue Feb 16 15:16:22 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635783359 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455635783359 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic " "Command: quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455635783359 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1455635784489 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "glu_logic.bdf 1 1 " "Found 1 design units, including 1 entities, in source file glu_logic.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 glu_Logic " "Found entity 1: glu_Logic" { } { { "glu_Logic.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/glu_Logic.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455635784576 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455635784576 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "glu_Logic " "Elaborating entity \"glu_Logic\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455635784637 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455635786197 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455635786197 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "20 " "Implemented 20 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455635786515 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455635786515 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455635786515 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "458 " "Peak virtual memory: 458 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635786650 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:26 2016 " "Processing ended: Tue Feb 16 15:16:26 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635786650 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635786650 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635786650 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455635786650 ""} diff --git a/glue_logic/db/glu_Logic.map.rdb b/glue_logic/db/glu_Logic.map.rdb Binary files differnew file mode 100644 index 0000000..01c0276 --- /dev/null +++ b/glue_logic/db/glu_Logic.map.rdb diff --git a/glue_logic/db/glu_Logic.map_bb.cdb b/glue_logic/db/glu_Logic.map_bb.cdb Binary files differnew file mode 100644 index 0000000..4de5b57 --- /dev/null +++ b/glue_logic/db/glu_Logic.map_bb.cdb diff --git a/glue_logic/db/glu_Logic.map_bb.hdb b/glue_logic/db/glu_Logic.map_bb.hdb Binary files differnew file mode 100644 index 0000000..0f7c577 --- /dev/null +++ b/glue_logic/db/glu_Logic.map_bb.hdb diff --git a/glue_logic/db/glu_Logic.map_bb.logdb b/glue_logic/db/glu_Logic.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/glue_logic/db/glu_Logic.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/glue_logic/db/glu_Logic.pplq.rdb b/glue_logic/db/glu_Logic.pplq.rdb Binary files differnew file mode 100644 index 0000000..8502917 --- /dev/null +++ b/glue_logic/db/glu_Logic.pplq.rdb diff --git a/glue_logic/db/glu_Logic.pre_map.hdb b/glue_logic/db/glu_Logic.pre_map.hdb Binary files differnew file mode 100644 index 0000000..b58383e --- /dev/null +++ b/glue_logic/db/glu_Logic.pre_map.hdb diff --git a/glue_logic/db/glu_Logic.pti_db_list.ddb b/glue_logic/db/glu_Logic.pti_db_list.ddb Binary files differnew file mode 100644 index 0000000..4c5fa0d --- /dev/null +++ b/glue_logic/db/glu_Logic.pti_db_list.ddb diff --git a/glue_logic/db/glu_Logic.root_partition.map.reg_db.cdb b/glue_logic/db/glu_Logic.root_partition.map.reg_db.cdb Binary files differnew file mode 100644 index 0000000..e48cb51 --- /dev/null +++ b/glue_logic/db/glu_Logic.root_partition.map.reg_db.cdb diff --git a/glue_logic/db/glu_Logic.routing.rdb b/glue_logic/db/glu_Logic.routing.rdb Binary files differnew file mode 100644 index 0000000..5826080 --- /dev/null +++ b/glue_logic/db/glu_Logic.routing.rdb diff --git a/glue_logic/db/glu_Logic.rtlv.hdb b/glue_logic/db/glu_Logic.rtlv.hdb Binary files differnew file mode 100644 index 0000000..f4f21bc --- /dev/null +++ b/glue_logic/db/glu_Logic.rtlv.hdb diff --git a/glue_logic/db/glu_Logic.rtlv_sg.cdb b/glue_logic/db/glu_Logic.rtlv_sg.cdb Binary files differnew file mode 100644 index 0000000..8d895cc --- /dev/null +++ b/glue_logic/db/glu_Logic.rtlv_sg.cdb diff --git a/glue_logic/db/glu_Logic.rtlv_sg_swap.cdb b/glue_logic/db/glu_Logic.rtlv_sg_swap.cdb Binary files differnew file mode 100644 index 0000000..c194c18 --- /dev/null +++ b/glue_logic/db/glu_Logic.rtlv_sg_swap.cdb diff --git a/glue_logic/db/glu_Logic.sgdiff.cdb b/glue_logic/db/glu_Logic.sgdiff.cdb Binary files differnew file mode 100644 index 0000000..0858bcf --- /dev/null +++ b/glue_logic/db/glu_Logic.sgdiff.cdb diff --git a/glue_logic/db/glu_Logic.sgdiff.hdb b/glue_logic/db/glu_Logic.sgdiff.hdb Binary files differnew file mode 100644 index 0000000..d86c614 --- /dev/null +++ b/glue_logic/db/glu_Logic.sgdiff.hdb diff --git a/glue_logic/db/glu_Logic.sld_design_entry.sci b/glue_logic/db/glu_Logic.sld_design_entry.sci Binary files differnew file mode 100644 index 0000000..91c4798 --- /dev/null +++ b/glue_logic/db/glu_Logic.sld_design_entry.sci diff --git a/glue_logic/db/glu_Logic.sld_design_entry_dsc.sci b/glue_logic/db/glu_Logic.sld_design_entry_dsc.sci Binary files differnew file mode 100644 index 0000000..91c4798 --- /dev/null +++ b/glue_logic/db/glu_Logic.sld_design_entry_dsc.sci diff --git a/glue_logic/db/glu_Logic.smart_action.txt b/glue_logic/db/glu_Logic.smart_action.txt new file mode 100644 index 0000000..e04bbcf --- /dev/null +++ b/glue_logic/db/glu_Logic.smart_action.txt @@ -0,0 +1 @@ +FIT diff --git a/glue_logic/db/glu_Logic.sta.qmsg b/glue_logic/db/glu_Logic.sta.qmsg new file mode 100644 index 0000000..79eb0ed --- /dev/null +++ b/glue_logic/db/glu_Logic.sta.qmsg @@ -0,0 +1,49 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455635772538 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:16:11 2016 " "Processing started: Tue Feb 16 15:16:11 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta glu_Logic -c glu_Logic " "Command: quartus_sta glu_Logic -c glu_Logic" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455635772553 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455635772647 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1455635773041 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773045 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773132 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773132 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "glu_Logic.sdc " "Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455635773623 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635773628 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635773633 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635773638 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455635773642 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635773645 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455635773668 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1455635773723 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455635773745 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773750 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773792 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773815 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773840 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773863 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773882 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455635773948 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455635773983 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455635774419 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635774497 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635774497 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635774497 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635774497 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774498 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774533 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774556 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774577 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774597 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774615 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455635774664 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635774905 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635774905 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635774905 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635774906 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774928 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774948 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774969 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774991 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635775012 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455635775477 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455635775477 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "487 " "Peak virtual memory: 487 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:15 2016 " "Processing ended: Tue Feb 16 15:16:15 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} diff --git a/glue_logic/db/glu_Logic.sta.rdb b/glue_logic/db/glu_Logic.sta.rdb Binary files differnew file mode 100644 index 0000000..8ab6516 --- /dev/null +++ b/glue_logic/db/glu_Logic.sta.rdb diff --git a/glue_logic/db/glu_Logic.syn_hier_info b/glue_logic/db/glu_Logic.syn_hier_info new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/glue_logic/db/glu_Logic.syn_hier_info diff --git a/glue_logic/db/glu_Logic.tis_db_list.ddb b/glue_logic/db/glu_Logic.tis_db_list.ddb Binary files differnew file mode 100644 index 0000000..180899a --- /dev/null +++ b/glue_logic/db/glu_Logic.tis_db_list.ddb diff --git a/glue_logic/db/glu_Logic.tiscmp.fast_1200mv_0c.ddb b/glue_logic/db/glu_Logic.tiscmp.fast_1200mv_0c.ddb Binary files differnew file mode 100644 index 0000000..50c6e4c --- /dev/null +++ b/glue_logic/db/glu_Logic.tiscmp.fast_1200mv_0c.ddb diff --git a/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_0c.ddb b/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_0c.ddb Binary files differnew file mode 100644 index 0000000..a542856 --- /dev/null +++ b/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_0c.ddb diff --git a/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_85c.ddb b/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_85c.ddb Binary files differnew file mode 100644 index 0000000..1d08652 --- /dev/null +++ b/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_85c.ddb diff --git a/glue_logic/db/glu_Logic.vpr.ammdb b/glue_logic/db/glu_Logic.vpr.ammdb Binary files differnew file mode 100644 index 0000000..170d7e1 --- /dev/null +++ b/glue_logic/db/glu_Logic.vpr.ammdb diff --git a/glue_logic/db/logic_util_heursitic.dat b/glue_logic/db/logic_util_heursitic.dat new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/glue_logic/db/logic_util_heursitic.dat diff --git a/glue_logic/db/prev_cmp_glu_Logic.qmsg b/glue_logic/db/prev_cmp_glu_Logic.qmsg new file mode 100644 index 0000000..b545053 --- /dev/null +++ b/glue_logic/db/prev_cmp_glu_Logic.qmsg @@ -0,0 +1,116 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455635751781 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635751788 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:15:51 2016 " "Processing started: Tue Feb 16 15:15:51 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635751788 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455635751788 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic " "Command: quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455635751789 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1455635752936 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "glu_logic.bdf 1 1 " "Found 1 design units, including 1 entities, in source file glu_logic.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 glu_Logic " "Found entity 1: glu_Logic" { } { { "glu_Logic.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/glu_Logic.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455635753027 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455635753027 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "glu_Logic " "Elaborating entity \"glu_Logic\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455635753116 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455635754836 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455635754836 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "20 " "Implemented 20 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455635755072 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455635755072 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455635755072 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "458 " "Peak virtual memory: 458 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635755206 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:15:55 2016 " "Processing ended: Tue Feb 16 15:15:55 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635755206 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635755206 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635755206 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455635755206 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455635757583 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635757615 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:15:56 2016 " "Processing started: Tue Feb 16 15:15:56 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635757615 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1455635757615 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic " "Command: quartus_fit --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1455635757626 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1455635757715 ""} +{ "Info" "0" "" "Project = glu_Logic" { } { } 0 0 "Project = glu_Logic" 0 0 "Fitter" 0 0 1455635757716 ""} +{ "Info" "0" "" "Revision = glu_Logic" { } { } 0 0 "Revision = glu_Logic" 0 0 "Fitter" 0 0 1455635757716 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1455635758479 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "glu_Logic EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"glu_Logic\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1455635758896 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759013 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759014 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759014 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455635759095 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455635759287 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 49 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 51 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 53 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 55 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 57 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455635759296 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455635759303 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "glu_Logic.sdc " "Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455635760262 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455635760265 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1455635760268 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1455635760270 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455635760273 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455635760276 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455635760283 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455635760286 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455635760288 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455635760291 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455635760294 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455635760296 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1455635760298 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1455635760301 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455635760303 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455635760305 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455635760310 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455635760310 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635760325 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455635760952 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635760998 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455635761007 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455635761055 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635761057 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455635761406 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" { } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455635761783 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455635761783 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635761859 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455635761870 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455635761870 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455635761870 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455635761881 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455635761988 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455635762283 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455635762365 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455635762664 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635763015 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/EIE1 FPGA/output_files/glu_Logic.fit.smsg " "Generated suppressed messages file /EIE1 FPGA/output_files/glu_Logic.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455635763758 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1111 " "Peak virtual memory: 1111 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:05 2016 " "Processing ended: Tue Feb 16 15:16:05 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455635765258 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1455635769000 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635769004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:16:08 2016 " "Processing started: Tue Feb 16 15:16:08 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635769004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455635769004 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic " "Command: quartus_asm --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455635769004 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455635769976 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455635770011 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:10 2016 " "Processing ended: Tue Feb 16 15:16:10 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455635770639 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1455635771599 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1455635772538 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:16:11 2016 " "Processing started: Tue Feb 16 15:16:11 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta glu_Logic -c glu_Logic " "Command: quartus_sta glu_Logic -c glu_Logic" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455635772553 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455635772647 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1455635773041 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773045 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773132 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773132 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "glu_Logic.sdc " "Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455635773623 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635773628 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635773633 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635773638 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455635773642 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635773645 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455635773668 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1455635773723 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455635773745 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773750 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773792 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773815 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773840 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773863 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773882 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455635773948 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455635773983 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455635774419 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635774497 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635774497 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635774497 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635774497 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774498 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774533 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774556 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774577 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774597 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774615 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455635774664 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635774905 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635774905 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635774905 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635774906 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774928 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774948 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774969 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774991 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635775012 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455635775477 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455635775477 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "487 " "Peak virtual memory: 487 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:15 2016 " "Processing ended: Tue Feb 16 15:16:15 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 7 s " "Quartus II Full Compilation was successful. 0 errors, 7 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455635777402 ""} diff --git a/glue_logic/glu_Logic.bdf b/glue_logic/glu_Logic.bdf new file mode 100644 index 0000000..26fb82b --- /dev/null +++ b/glue_logic/glu_Logic.bdf @@ -0,0 +1,58 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 648 464 816 480) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "Input[9..0]" (rect 5 0 56 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 864 464 1040 480) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "Output[9..0]" (rect 90 0 149 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(connector + (pt 816 472) + (pt 864 472) + (bus) +) diff --git a/glue_logic/glu_Logic.qpf b/glue_logic/glu_Logic.qpf new file mode 100644 index 0000000..34de522 --- /dev/null +++ b/glue_logic/glu_Logic.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 15:10:25 February 16, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "15:10:25 February 16, 2016" + +# Revisions + +PROJECT_REVISION = "glu_Logic" diff --git a/glue_logic/glu_Logic.qsf b/glue_logic/glu_Logic.qsf new file mode 100644 index 0000000..bc9f5ca --- /dev/null +++ b/glue_logic/glu_Logic.qsf @@ -0,0 +1,76 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 15:10:25 February 16, 2016 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# glu_Logic_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C16F484C6 +set_global_assignment -name TOP_LEVEL_ENTITY glu_Logic +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:10:25 FEBRUARY 16, 2016" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name BDF_FILE glu_Logic.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_D2 -to Input[9] +set_location_assignment PIN_E4 -to Input[8] +set_location_assignment PIN_E3 -to Input[7] +set_location_assignment PIN_H7 -to Input[6] +set_location_assignment PIN_J7 -to Input[5] +set_location_assignment PIN_G5 -to Input[4] +set_location_assignment PIN_G4 -to Input[3] +set_location_assignment PIN_H6 -to Input[2] +set_location_assignment PIN_H5 -to Input[1] +set_location_assignment PIN_J6 -to Input[0] +set_location_assignment PIN_B1 -to Output[9] +set_location_assignment PIN_B2 -to Output[8] +set_location_assignment PIN_C2 -to Output[7] +set_location_assignment PIN_C1 -to Output[6] +set_location_assignment PIN_E1 -to Output[5] +set_location_assignment PIN_F2 -to Output[4] +set_location_assignment PIN_H1 -to Output[3] +set_location_assignment PIN_J3 -to Output[2] +set_location_assignment PIN_J2 -to Output[1] +set_location_assignment PIN_J1 -to Output[0] +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name CDF_FILE output_files/Chain1.cdf
\ No newline at end of file diff --git a/glue_logic/glu_Logic.qws b/glue_logic/glu_Logic.qws Binary files differnew file mode 100644 index 0000000..63563b7 --- /dev/null +++ b/glue_logic/glu_Logic.qws diff --git a/glue_logic/incremental_db/README b/glue_logic/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/glue_logic/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.db_info b/glue_logic/incremental_db/compiled_partitions/glu_Logic.db_info new file mode 100644 index 0000000..5fd933f --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +Version_Index = 302049280 +Creation_Time = Tue Feb 16 15:12:31 2016 diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.ammdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.ammdb Binary files differnew file mode 100644 index 0000000..1a57b15 --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.ammdb diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.cdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.cdb Binary files differnew file mode 100644 index 0000000..1906e65 --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.cdb diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.dfp b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.dfp Binary files differnew file mode 100644 index 0000000..b1c67d6 --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.dfp diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.hdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.hdb Binary files differnew file mode 100644 index 0000000..c32a041 --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.hdb diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.kpt b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.kpt Binary files differnew file mode 100644 index 0000000..b1479c0 --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.kpt diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.logdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.rcfdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.rcfdb Binary files differnew file mode 100644 index 0000000..166bbfc --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.rcfdb diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.cdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.cdb Binary files differnew file mode 100644 index 0000000..9c73857 --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.cdb diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.dpi b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.dpi Binary files differnew file mode 100644 index 0000000..4ae522e --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.dpi diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.cdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.cdb Binary files differnew file mode 100644 index 0000000..d47c66e --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.cdb diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hb_info b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hb_info Binary files differnew file mode 100644 index 0000000..8210c55 --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hb_info diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hdb Binary files differnew file mode 100644 index 0000000..8397de6 --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hdb diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.sig b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.sig new file mode 100644 index 0000000..ef58eaa --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hdb Binary files differnew file mode 100644 index 0000000..3903d4f --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hdb diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.kpt b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.kpt Binary files differnew file mode 100644 index 0000000..52f7807 --- /dev/null +++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.kpt diff --git a/glue_logic/output_files/Chain1.cdf b/glue_logic/output_files/Chain1.cdf new file mode 100644 index 0000000..ff8f9b9 --- /dev/null +++ b/glue_logic/output_files/Chain1.cdf @@ -0,0 +1,13 @@ +/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(EP3C16F484) Path("//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/output_files/") File("glu_Logic.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/glue_logic/output_files/glu_Logic.asm.rpt b/glue_logic/output_files/glu_Logic.asm.rpt new file mode 100644 index 0000000..837dbe8 --- /dev/null +++ b/glue_logic/output_files/glu_Logic.asm.rpt @@ -0,0 +1,116 @@ +Assembler report for glu_Logic +Tue Feb 16 15:16:10 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: /EIE1 FPGA/output_files/glu_Logic.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Tue Feb 16 15:16:10 2016 ; +; Revision Name ; glu_Logic ; +; Top-level Entity Name ; glu_Logic ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Use configuration device ; Off ; Off ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Enable OCT_DONE ; Off ; Off ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++---------------------------------------+ +; Assembler Generated Files ; ++---------------------------------------+ +; File Name ; ++---------------------------------------+ +; /EIE1 FPGA/output_files/glu_Logic.sof ; ++---------------------------------------+ + + ++-----------------------------------------------------------------+ +; Assembler Device Options: /EIE1 FPGA/output_files/glu_Logic.sof ; ++----------------+------------------------------------------------+ +; Option ; Setting ; ++----------------+------------------------------------------------+ +; Device ; EP3C16F484C6 ; +; JTAG usercode ; 0x000C87E7 ; +; Checksum ; 0x000C87E7 ; ++----------------+------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Assembler + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + Info: Processing started: Tue Feb 16 15:16:08 2016 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 427 megabytes + Info: Processing ended: Tue Feb 16 15:16:10 2016 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/glue_logic/output_files/glu_Logic.done b/glue_logic/output_files/glu_Logic.done new file mode 100644 index 0000000..6f7edbf --- /dev/null +++ b/glue_logic/output_files/glu_Logic.done @@ -0,0 +1 @@ +Tue Feb 16 15:16:27 2016 diff --git a/glue_logic/output_files/glu_Logic.fit.rpt b/glue_logic/output_files/glu_Logic.fit.rpt new file mode 100644 index 0000000..bb750e3 --- /dev/null +++ b/glue_logic/output_files/glu_Logic.fit.rpt @@ -0,0 +1,1188 @@ +Fitter report for glu_Logic +Tue Feb 16 15:16:03 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. I/O Assignment Warnings + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Non-Global High Fan-Out Signals + 21. Other Routing Usage Summary + 22. I/O Rules Summary + 23. I/O Rules Details + 24. I/O Rules Matrix + 25. Fitter Device Options + 26. Operating Settings and Conditions + 27. Fitter Messages + 28. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+--------------------------------------------------+ +; Fitter Status ; Successful - Tue Feb 16 15:16:03 2016 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ; +; Revision Name ; glu_Logic ; +; Top-level Entity Name ; glu_Logic ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Total logic elements ; 0 / 15,408 ( 0 % ) ; +; Total combinational functions ; 0 / 15,408 ( 0 % ) ; +; Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 20 / 347 ( 6 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 516,096 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+--------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP3C16F484C6 ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Device I/O Standard ; 2.5 V ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Off ; Off ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; RAM Bit Reservation (Cyclone III) ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; < 0.1% ; +; Processors 5-8 ; 0.0% ; ++----------------------------+-------------+ + + ++--------------------------------------------------+ +; I/O Assignment Warnings ; ++-----------+--------------------------------------+ +; Pin Name ; Reason ; ++-----------+--------------------------------------+ +; Output[9] ; Missing drive strength and slew rate ; +; Output[8] ; Missing drive strength and slew rate ; +; Output[7] ; Missing drive strength and slew rate ; +; Output[6] ; Missing drive strength and slew rate ; +; Output[5] ; Missing drive strength and slew rate ; +; Output[4] ; Missing drive strength and slew rate ; +; Output[3] ; Missing drive strength and slew rate ; +; Output[2] ; Missing drive strength and slew rate ; +; Output[1] ; Missing drive strength and slew rate ; +; Output[0] ; Missing drive strength and slew rate ; ++-----------+--------------------------------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+------------------------+ +; Type ; Value ; ++---------------------+------------------------+ +; Placement (by node) ; ; +; -- Requested ; 0 / 51 ( 0.00 % ) ; +; -- Achieved ; 0 / 51 ( 0.00 % ) ; +; ; ; +; Routing (by net) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++---------------------+------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 41 ; 0 ; N/A ; Source File ; +; hard_block:auto_generated_inst ; 10 ; 0 ; N/A ; Source File ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /EIE1 FPGA/output_files/glu_Logic.pin. + + ++-------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+---------------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------------+ +; Total logic elements ; 0 / 15,408 ( 0 % ) ; +; -- Combinational with no register ; 0 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 0 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 0 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 17,068 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; +; -- I/O registers ; 0 / 1,660 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 0 / 963 ( 0 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 20 / 347 ( 6 % ) ; +; -- Clock pins ; 0 / 8 ( 0 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; Global signals ; 0 ; +; M9Ks ; 0 / 56 ( 0 % ) ; +; Total block memory bits ; 0 / 516,096 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 516,096 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out ; 1 ; +; Highest non-global fan-out ; 1 ; +; Total fan-out ; 35 ; +; Average fan-out ; 0.70 ; ++---------------------------------------------+---------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++--------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+-------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+-------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 0 / 15408 ( 0 % ) ; 0 / 15408 ( 0 % ) ; +; -- Combinational with no register ; 0 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 0 ; 0 ; +; -- 3 input functions ; 0 ; 0 ; +; -- <=2 input functions ; 0 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 0 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 15408 ( 0 % ) ; 0 / 15408 ( 0 % ) ; +; ; ; ; +; Total LABs: partially or completely used ; 0 / 963 ( 0 % ) ; 0 / 963 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 20 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; 0 / 112 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 30 ; 5 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 10 ; 0 ; +; -- Output Ports ; 10 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+-------------------+--------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; Input[0] ; J6 ; 1 ; 0 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; Input[1] ; H5 ; 1 ; 0 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; Input[2] ; H6 ; 1 ; 0 ; 25 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; Input[3] ; G4 ; 1 ; 0 ; 23 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; Input[4] ; G5 ; 1 ; 0 ; 27 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; Input[5] ; J7 ; 1 ; 0 ; 22 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; Input[6] ; H7 ; 1 ; 0 ; 25 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; Input[7] ; E3 ; 1 ; 0 ; 26 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; Input[8] ; E4 ; 1 ; 0 ; 26 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; Input[9] ; D2 ; 1 ; 0 ; 25 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Output[0] ; J1 ; 1 ; 0 ; 20 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Output[1] ; J2 ; 1 ; 0 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Output[2] ; J3 ; 1 ; 0 ; 21 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Output[3] ; H1 ; 1 ; 0 ; 21 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Output[4] ; F2 ; 1 ; 0 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Output[5] ; E1 ; 1 ; 0 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Output[6] ; C1 ; 1 ; 0 ; 26 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Output[7] ; C2 ; 1 ; 0 ; 26 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Output[8] ; B2 ; 1 ; 0 ; 27 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; Output[9] ; B1 ; 1 ; 0 ; 27 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; E4 ; DIFFIO_L2p, nRESET ; Use as regular IO ; Input[8] ; Dual Purpose Pin ; +; D1 ; DIFFIO_L4n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; E2 ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; K6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; K2 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; K1 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; K5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; L3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; M18 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; M17 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; L18 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; L17 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; K20 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; K22 ; DIFFIO_R16n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 24 / 33 ( 73 % ) ; 2.5V ; -- ; +; 2 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 46 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 41 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 46 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 1 / 43 ( 2 % ) ; 2.5V ; -- ; +; 7 ; 0 / 47 ( 0 % ) ; 2.5V ; -- ; +; 8 ; 0 / 43 ( 0 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A3 ; 354 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 350 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 345 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 336 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 334 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 332 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 328 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 326 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 321 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A12 ; 319 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 314 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 312 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 307 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 298 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 296 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 291 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 290 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 284 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA3 ; 102 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA4 ; 106 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA5 ; 108 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA7 ; 115 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; 123 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA10 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; 134 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA12 ; 136 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA13 ; 138 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; 140 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; 145 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; 149 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; 151 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA18 ; 163 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; 164 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 169 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA21 ; 179 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA22 ; 178 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB3 ; 103 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB4 ; 107 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 109 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB7 ; 116 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 135 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AB12 ; 137 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AB13 ; 139 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB14 ; 141 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 146 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 150 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 152 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; 162 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB19 ; 165 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; 170 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB21 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 2 ; 1 ; Output[9] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; B2 ; 1 ; 1 ; Output[8] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; B3 ; 355 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 351 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 346 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 337 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 335 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 333 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; 329 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B10 ; 327 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 322 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B12 ; 320 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 315 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; 313 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 308 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; 299 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; 297 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; 292 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B19 ; 289 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 285 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 269 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B22 ; 268 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 7 ; 1 ; Output[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; C2 ; 6 ; 1 ; Output[7] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; C3 ; 358 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 359 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 349 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 340 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 339 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C10 ; 330 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; 309 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C15 ; 300 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 286 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C19 ; 282 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 270 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C21 ; 267 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C22 ; 266 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 9 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; D2 ; 8 ; 1 ; Input[9] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D6 ; 356 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D10 ; 324 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D12 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D13 ; 310 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D15 ; 293 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D17 ; 281 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; D18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D19 ; 283 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D20 ; 271 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D21 ; 261 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D22 ; 260 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 14 ; 1 ; Output[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E2 ; 13 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; E3 ; 5 ; 1 ; Input[7] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E4 ; 4 ; 1 ; Input[8] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E5 ; 363 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E6 ; 362 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; 357 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E9 ; 338 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; E10 ; 325 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 317 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 316 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; 311 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; 301 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 294 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 275 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E18 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E21 ; 256 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; 255 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 16 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 15 ; 1 ; Output[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F7 ; 360 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 352 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 347 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 348 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 318 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; 302 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F13 ; 306 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F14 ; 279 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F15 ; 276 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F16 ; 274 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; 272 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F18 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F19 ; 263 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F20 ; 262 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F21 ; 251 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 250 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 39 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G2 ; 38 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G3 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 17 ; 1 ; Input[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; G5 ; 3 ; 1 ; Input[4] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; G6 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G7 ; 361 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; 353 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G9 ; 342 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G10 ; 341 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 331 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 305 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; 295 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G14 ; 280 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G15 ; 278 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 277 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 273 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G18 ; 264 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G21 ; 226 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G22 ; 225 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; H1 ; 26 ; 1 ; Output[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; H2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H5 ; 0 ; 1 ; Input[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; H6 ; 11 ; 1 ; Input[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; H7 ; 10 ; 1 ; Input[6] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; 344 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H10 ; 343 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H11 ; 323 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H12 ; 304 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 303 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 288 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 287 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; 259 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H17 ; 265 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H18 ; 257 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; H19 ; 254 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 253 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; 246 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H22 ; 245 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J1 ; 29 ; 1 ; Output[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J2 ; 28 ; 1 ; Output[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J3 ; 27 ; 1 ; Output[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J4 ; 24 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J6 ; 12 ; 1 ; Input[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J7 ; 22 ; 1 ; Input[5] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J15 ; 238 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; 243 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J17 ; 258 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J18 ; 249 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J21 ; 242 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; 241 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 31 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; K2 ; 30 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K5 ; 32 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; K6 ; 19 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K8 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; 236 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; 244 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K17 ; 247 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K18 ; 248 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K19 ; 237 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; K20 ; 231 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; K21 ; 240 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 239 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L1 ; 35 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; L2 ; 34 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; L3 ; 37 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 36 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L5 ; 33 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; L6 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L7 ; 50 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L8 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; 233 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; 232 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L17 ; 230 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 229 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; L19 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L21 ; 235 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L22 ; 234 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 45 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M3 ; 47 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 46 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 51 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M6 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M7 ; 65 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M8 ; 66 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; 195 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M16 ; 222 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M17 ; 228 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 227 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; M19 ; 221 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M20 ; 220 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M21 ; 219 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 218 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 49 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 48 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N5 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N6 ; 64 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N7 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N8 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; 189 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 196 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; 205 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N17 ; 214 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N18 ; 215 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 213 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N20 ; 212 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 217 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N22 ; 216 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 53 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 52 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P5 ; 63 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P6 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P7 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P8 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; 180 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 192 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 193 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P17 ; 197 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P18 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P20 ; 208 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; P21 ; 211 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 210 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; 55 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 54 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R5 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R7 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R9 ; 88 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 90 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 97 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 98 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 153 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R16 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R17 ; 194 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; R18 ; 203 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; 204 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R20 ; 200 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; 207 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R22 ; 206 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 41 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T2 ; 40 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T3 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; T4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T6 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T7 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T8 ; 89 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 91 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T10 ; 121 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T11 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 148 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T14 ; 160 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T15 ; 161 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T16 ; 171 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T17 ; 181 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T18 ; 182 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 224 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T22 ; 223 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; U1 ; 60 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; 94 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; 95 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U9 ; 112 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U10 ; 122 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U11 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U12 ; 147 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U13 ; 156 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U14 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U15 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U19 ; 188 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 187 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; 202 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U22 ; 201 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 62 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; 61 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V5 ; 93 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; 92 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V7 ; 105 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V8 ; 113 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 119 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; V10 ; 120 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V12 ; 142 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 154 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 157 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 158 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; 168 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; V17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V18 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V21 ; 199 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V22 ; 198 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W6 ; 104 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W7 ; 110 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 114 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W10 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W13 ; 143 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; 155 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; W15 ; 159 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W17 ; 166 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W19 ; 184 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W20 ; 183 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 191 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; 190 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y2 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y3 ; 99 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y4 ; 96 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; 101 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y7 ; 111 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 117 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 144 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y17 ; 167 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 186 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y22 ; 185 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +; |glu_Logic ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |glu_Logic ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++-----------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++-----------+----------+---------------+---------------+-----------------------+-----+------+ +; Output[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Output[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Output[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Output[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Output[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Output[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Output[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Output[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Output[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Output[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Input[9] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Input[8] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Input[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Input[6] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Input[5] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Input[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Input[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Input[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Input[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Input[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; ++-----------+----------+---------------+---------------+-----------------------+-----+------+ + + ++-------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-------------------------+-------------------+---------+ +; Input[9] ; ; ; +; - Output[9]~output ; 0 ; 6 ; +; Input[8] ; ; ; +; - Output[8]~output ; 0 ; 6 ; +; Input[7] ; ; ; +; - Output[7]~output ; 0 ; 6 ; +; Input[6] ; ; ; +; - Output[6]~output ; 1 ; 6 ; +; Input[5] ; ; ; +; - Output[5]~output ; 1 ; 6 ; +; Input[4] ; ; ; +; - Output[4]~output ; 0 ; 6 ; +; Input[3] ; ; ; +; - Output[3]~output ; 1 ; 6 ; +; Input[2] ; ; ; +; - Output[2]~output ; 0 ; 6 ; +; Input[1] ; ; ; +; - Output[1]~output ; 1 ; 6 ; +; Input[0] ; ; ; +; - Output[0]~output ; 0 ; 6 ; ++-------------------------+-------------------+---------+ + + ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------------+----------------+ +; Name ; Fan-Out ; ++----------------+----------------+ +; Input[0]~input ; 1 ; +; Input[1]~input ; 1 ; +; Input[2]~input ; 1 ; +; Input[3]~input ; 1 ; +; Input[4]~input ; 1 ; +; Input[5]~input ; 1 ; +; Input[6]~input ; 1 ; +; Input[7]~input ; 1 ; +; Input[8]~input ; 1 ; +; Input[9]~input ; 1 ; ++----------------+----------------+ + + ++-----------------------------------------------------+ +; Other Routing Usage Summary ; ++-----------------------------+-----------------------+ +; Other Routing Resource Type ; Usage ; ++-----------------------------+-----------------------+ +; Block interconnects ; 10 / 47,787 ( < 1 % ) ; +; C16 interconnects ; 0 / 1,804 ( 0 % ) ; +; C4 interconnects ; 10 / 31,272 ( < 1 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Local interconnects ; 0 / 15,408 ( 0 % ) ; +; R24 interconnects ; 0 / 1,775 ( 0 % ) ; +; R4 interconnects ; 2 / 41,310 ( < 1 % ) ; ++-----------------------------+-----------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 20 ; 0 ; 20 ; 0 ; 0 ; 20 ; 20 ; 0 ; 20 ; 20 ; 0 ; 10 ; 0 ; 0 ; 10 ; 0 ; 10 ; 10 ; 0 ; 0 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 20 ; 0 ; 20 ; 20 ; 0 ; 0 ; 20 ; 0 ; 0 ; 20 ; 10 ; 20 ; 20 ; 10 ; 20 ; 10 ; 10 ; 20 ; 20 ; 20 ; 10 ; 20 ; 20 ; 20 ; 20 ; 20 ; 0 ; 20 ; 20 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Output[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Output[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Output[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Output[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Output[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Output[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Output[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Output[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Output[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Output[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Input[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Input[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Input[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Input[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Input[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Input[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Input[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Input[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Input[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Input[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (119006): Selected device EP3C16F484C6 for design "glu_Logic" +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP3C40F484C6 is compatible + Info (176445): Device EP3C55F484C6 is compatible + Info (176445): Device EP3C80F484C6 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 +Info (144001): Generated suppressed messages file /EIE1 FPGA/output_files/glu_Logic.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 1111 megabytes + Info: Processing ended: Tue Feb 16 15:16:05 2016 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:05 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /EIE1 FPGA/output_files/glu_Logic.fit.smsg. + + diff --git a/glue_logic/output_files/glu_Logic.fit.smsg b/glue_logic/output_files/glu_Logic.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/glue_logic/output_files/glu_Logic.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/glue_logic/output_files/glu_Logic.fit.summary b/glue_logic/output_files/glu_Logic.fit.summary new file mode 100644 index 0000000..a142eb4 --- /dev/null +++ b/glue_logic/output_files/glu_Logic.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Tue Feb 16 15:16:03 2016 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version +Revision Name : glu_Logic +Top-level Entity Name : glu_Logic +Family : Cyclone III +Device : EP3C16F484C6 +Timing Models : Final +Total logic elements : 0 / 15,408 ( 0 % ) + Total combinational functions : 0 / 15,408 ( 0 % ) + Dedicated logic registers : 0 / 15,408 ( 0 % ) +Total registers : 0 +Total pins : 20 / 347 ( 6 % ) +Total virtual pins : 0 +Total memory bits : 0 / 516,096 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/glue_logic/output_files/glu_Logic.flow.rpt b/glue_logic/output_files/glu_Logic.flow.rpt new file mode 100644 index 0000000..4b4d005 --- /dev/null +++ b/glue_logic/output_files/glu_Logic.flow.rpt @@ -0,0 +1,114 @@ +Flow report for glu_Logic +Tue Feb 16 15:16:26 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+--------------------------------------------------+ +; Flow Status ; Successful - Tue Feb 16 15:16:26 2016 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ; +; Revision Name ; glu_Logic ; +; Top-level Entity Name ; glu_Logic ; +; Family ; Cyclone III ; +; Device ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Total logic elements ; 0 ; +; Total combinational functions ; 0 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 20 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+--------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 02/16/2016 15:16:24 ; +; Main task ; Compilation ; +; Revision Name ; glu_Logic ; ++-------------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+---------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+---------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 260248564169585.145563578405340 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+---------------------------------+---------------+-------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:03 ; 1.0 ; 448 MB ; 00:00:01 ; +; Total ; 00:00:03 ; -- ; -- ; 00:00:01 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; eews104a-012 ; Windows 7 ; 6.1 ; x86_64 ; ++----------------------+------------------+-----------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic + + + diff --git a/glue_logic/output_files/glu_Logic.jdi b/glue_logic/output_files/glu_Logic.jdi new file mode 100644 index 0000000..39e5c82 --- /dev/null +++ b/glue_logic/output_files/glu_Logic.jdi @@ -0,0 +1,8 @@ +<sld_project_info> + <project> + <hash md5_digest_80b="379951d8e352e4b13b31"/> + </project> + <file_info> + <file device="EP3C16F484C6" path="glu_Logic.sof" usercode="0xFFFFFFFF"/> + </file_info> +</sld_project_info> diff --git a/glue_logic/output_files/glu_Logic.map.rpt b/glue_logic/output_files/glu_Logic.map.rpt new file mode 100644 index 0000000..1adfe57 --- /dev/null +++ b/glue_logic/output_files/glu_Logic.map.rpt @@ -0,0 +1,260 @@ +Analysis & Synthesis report for glu_Logic +Tue Feb 16 15:16:26 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Elapsed Time Per Partition + 10. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+--------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Tue Feb 16 15:16:26 2016 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ; +; Revision Name ; glu_Logic ; +; Top-level Entity Name ; glu_Logic ; +; Family ; Cyclone III ; +; Total logic elements ; 0 ; +; Total combinational functions ; 0 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 20 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+--------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP3C16F484C6 ; ; +; Top-level entity name ; glu_Logic ; glu_Logic ; +; Family name ; Cyclone III ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-8 ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+---------+ +; glu_Logic.bdf ; yes ; User Block Diagram/Schematic File ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/glu_Logic.bdf ; ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+---------+ + + ++----------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+------------------+ +; Resource ; Usage ; ++---------------------------------------------+------------------+ +; ; ; +; Total combinational functions ; 0 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 0 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 20 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; Output[9]~output ; +; Maximum fan-out ; 1 ; +; Total fan-out ; 30 ; +; Average fan-out ; 0.75 ; ++---------------------------------------------+------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +; |glu_Logic ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; |glu_Logic ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + Info: Processing started: Tue Feb 16 15:16:22 2016 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (12021): Found 1 design units, including 1 entities, in source file glu_logic.bdf + Info (12023): Found entity 1: glu_Logic +Info (12127): Elaborating entity "glu_Logic" for the top level hierarchy +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 20 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 10 input pins + Info (21059): Implemented 10 output pins +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 458 megabytes + Info: Processing ended: Tue Feb 16 15:16:26 2016 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/glue_logic/output_files/glu_Logic.map.summary b/glue_logic/output_files/glu_Logic.map.summary new file mode 100644 index 0000000..081dcdb --- /dev/null +++ b/glue_logic/output_files/glu_Logic.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Tue Feb 16 15:16:26 2016 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version +Revision Name : glu_Logic +Top-level Entity Name : glu_Logic +Family : Cyclone III +Total logic elements : 0 + Total combinational functions : 0 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 20 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/glue_logic/output_files/glu_Logic.pin b/glue_logic/output_files/glu_Logic.pin new file mode 100644 index 0000000..8b2ec3a --- /dev/null +++ b/glue_logic/output_files/glu_Logic.pin @@ -0,0 +1,554 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +CHIP "glu_Logic" ASSIGNED TO AN: EP3C16F484C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO8 : A2 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 : +GND+ : A11 : : : : 8 : +GND+ : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 : +VCCIO7 : A21 : power : : 2.5V : 7 : +GND : A22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 : +VCCIO3 : AA6 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +GND+ : AA11 : : : : 3 : +GND+ : AA12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 : +GND : AB1 : gnd : : : : +VCCIO3 : AB2 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 : +GND : AB6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 : +GND+ : AB11 : : : : 3 : +GND+ : AB12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 : +VCCIO4 : AB21 : power : : 2.5V : 4 : +GND : AB22 : gnd : : : : +Output[9] : B1 : output : 2.5 V : : 1 : Y +Output[8] : B2 : output : 2.5 V : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 : +GND+ : B11 : : : : 8 : +GND+ : B12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 : +Output[6] : C1 : output : 2.5 V : : 1 : Y +Output[7] : C2 : output : 2.5 V : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +GND : C5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +GND : C9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 : +GND : C11 : gnd : : : : +GND : C12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 : +GND : C14 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +GND : C16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +GND : C18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : input : 2.5 V : : 1 : N +Input[9] : D2 : input : 2.5 V : : 1 : Y +GND : D3 : gnd : : : : +VCCIO1 : D4 : power : : 2.5V : 1 : +VCCIO8 : D5 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +GND : D7 : gnd : : : : +GND : D8 : gnd : : : : +VCCIO8 : D9 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +VCCIO8 : D11 : power : : 2.5V : 8 : +VCCIO7 : D12 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 : +VCCIO7 : D14 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +VCCIO7 : D16 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +VCCIO7 : D18 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 : +Output[5] : E1 : output : 2.5 V : : 1 : Y +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N +Input[7] : E3 : input : 2.5 V : : 1 : Y +Input[8] : E4 : input : 2.5 V : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : +VCCIO8 : E8 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 : +VCCD_PLL2 : E17 : power : : 1.2V : : +GNDA2 : E18 : gnd : : : : +VCCIO6 : E19 : power : : 2.5V : 6 : +GND : E20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : +Output[4] : F2 : output : 2.5 V : : 1 : Y +GND : F3 : gnd : : : : +VCCIO1 : F4 : power : : 2.5V : 1 : +GNDA3 : F5 : gnd : : : : +VCCD_PLL3 : F6 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 : +VCCA2 : F18 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 : +GND+ : G1 : : : : 1 : +GND+ : G2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 : +Input[3] : G4 : input : 2.5 V : : 1 : Y +Input[4] : G5 : input : 2.5 V : : 1 : Y +VCCA3 : G6 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 6 : +VCCIO6 : G19 : power : : 2.5V : 6 : +GND : G20 : gnd : : : : +GND+ : G21 : : : : 6 : +GND+ : G22 : : : : 6 : +Output[3] : H1 : output : 2.5 V : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : : : : 1 : +GND : H3 : gnd : : : : +VCCIO1 : H4 : power : : 2.5V : 1 : +Input[1] : H5 : input : 2.5 V : : 1 : Y +Input[2] : H6 : input : 2.5 V : : 1 : Y +Input[6] : H7 : input : 2.5 V : : 1 : Y +GND : H8 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 : +Output[0] : J1 : output : 2.5 V : : 1 : Y +Output[1] : J2 : output : 2.5 V : : 1 : Y +Output[2] : J3 : output : 2.5 V : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 : +GND : J5 : gnd : : : : +Input[0] : J6 : input : 2.5 V : : 1 : Y +Input[5] : J7 : input : 2.5 V : : 1 : Y +VCCINT : J8 : power : : 1.2V : : +GND : J9 : gnd : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +VCCINT : J14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 : +GND : J19 : gnd : : : : +VCCIO6 : J20 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 : +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : input : 2.5 V : : 1 : N +~ALTERA_DCLK~ : K2 : output : 2.5 V : : 1 : N +GND : K3 : gnd : : : : +VCCIO1 : K4 : power : : 2.5V : 1 : +nCONFIG : K5 : : : : 1 : +nSTATUS : K6 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 : +MSEL3 : K20 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22 : output : 2.5 V : : 6 : N +TMS : L1 : input : : : 1 : +TCK : L2 : input : : : 1 : +nCE : L3 : : : : 1 : +TDO : L4 : output : : : 1 : +TDI : L5 : input : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 : +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 6 : +MSEL2 : L17 : : : : 6 : +MSEL1 : L18 : : : : 6 : +VCCIO6 : L19 : power : : 2.5V : 6 : +GND : L20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M16 : : : : 5 : +MSEL0 : M17 : : : : 6 : +CONF_DONE : M18 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +GND : N3 : gnd : : : : +VCCIO2 : N4 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 : +VCCINT : P9 : power : : 1.2V : : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P17 : : : : 5 : +VCCIO5 : P18 : power : : 2.5V : 5 : +GND : P19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +GND : R3 : gnd : : : : +VCCIO2 : R4 : power : : 2.5V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +GND+ : T1 : : : : 2 : +GND+ : T2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 : +VCCA1 : T6 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 4 : +VCCINT : T13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 : +VCCIO5 : T19 : power : : 2.5V : 5 : +GND : T20 : gnd : : : : +GND+ : T21 : : : : 5 : +GND+ : T22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +GND : U3 : gnd : : : : +VCCIO2 : U4 : power : : 2.5V : 2 : +GNDA1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 : +VCCINT : U16 : power : : 1.2V : : +VCCINT : U17 : power : : 1.2V : : +VCCA4 : U18 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 : +VCCD_PLL4 : V17 : power : : 1.2V : : +GNDA4 : V18 : gnd : : : : +VCCIO5 : V19 : power : : 2.5V : 5 : +GND : V20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +GND : W3 : gnd : : : : +VCCIO2 : W4 : power : : 2.5V : 2 : +VCCIO3 : W5 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 : +VCCIO3 : W9 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 : +VCCIO3 : W11 : power : : 2.5V : 3 : +VCCIO4 : W12 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 : +VCCIO4 : W16 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 : +VCCIO4 : W18 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 : +GND : Y5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 : +GND : Y9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +GND : Y11 : gnd : : : : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 : +VCCIO4 : Y14 : power : : 2.5V : 4 : +GND : Y15 : gnd : : : : +GND : Y16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +GND : Y18 : gnd : : : : +VCCIO5 : Y19 : power : : 2.5V : 5 : +GND : Y20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 : diff --git a/glue_logic/output_files/glu_Logic.sof b/glue_logic/output_files/glu_Logic.sof Binary files differnew file mode 100644 index 0000000..d84404c --- /dev/null +++ b/glue_logic/output_files/glu_Logic.sof diff --git a/glue_logic/output_files/glu_Logic.sta.rpt b/glue_logic/output_files/glu_Logic.sta.rpt new file mode 100644 index 0000000..1102eb4 --- /dev/null +++ b/glue_logic/output_files/glu_Logic.sta.rpt @@ -0,0 +1,563 @@ +TimeQuest Timing Analyzer report for glu_Logic +Tue Feb 16 15:16:15 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Propagation Delay + 13. Minimum Propagation Delay + 14. Slow 1200mV 85C Model Metastability Report + 15. Slow 1200mV 0C Model Fmax Summary + 16. Slow 1200mV 0C Model Setup Summary + 17. Slow 1200mV 0C Model Hold Summary + 18. Slow 1200mV 0C Model Recovery Summary + 19. Slow 1200mV 0C Model Removal Summary + 20. Slow 1200mV 0C Model Minimum Pulse Width Summary + 21. Propagation Delay + 22. Minimum Propagation Delay + 23. Slow 1200mV 0C Model Metastability Report + 24. Fast 1200mV 0C Model Setup Summary + 25. Fast 1200mV 0C Model Hold Summary + 26. Fast 1200mV 0C Model Recovery Summary + 27. Fast 1200mV 0C Model Removal Summary + 28. Fast 1200mV 0C Model Minimum Pulse Width Summary + 29. Propagation Delay + 30. Minimum Propagation Delay + 31. Fast 1200mV 0C Model Metastability Report + 32. Multicorner Timing Analysis Summary + 33. Progagation Delay + 34. Minimum Progagation Delay + 35. Board Trace Model Assignments + 36. Input Transition Times + 37. Slow Corner Signal Integrity Metrics + 38. Fast Corner Signal Integrity Metrics + 39. Clock Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths + 43. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+--------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ; +; Revision Name ; glu_Logic ; +; Device Family ; Cyclone III ; +; Device Name ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+--------------------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; < 0.1% ; +; Processors 5-8 ; 0.0% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + ++----------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; Input[0] ; Output[0] ; 5.696 ; ; ; 6.097 ; +; Input[1] ; Output[1] ; 5.962 ; ; ; 6.381 ; +; Input[2] ; Output[2] ; 6.904 ; ; ; 7.417 ; +; Input[3] ; Output[3] ; 5.775 ; ; ; 6.192 ; +; Input[4] ; Output[4] ; 5.720 ; ; ; 6.123 ; +; Input[5] ; Output[5] ; 5.734 ; ; ; 6.126 ; +; Input[6] ; Output[6] ; 5.724 ; ; ; 6.101 ; +; Input[7] ; Output[7] ; 5.838 ; ; ; 6.196 ; +; Input[8] ; Output[8] ; 5.683 ; ; ; 6.062 ; +; Input[9] ; Output[9] ; 5.775 ; ; ; 6.153 ; ++------------+-------------+-------+----+----+-------+ + + ++----------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; Input[0] ; Output[0] ; 5.581 ; ; ; 5.970 ; +; Input[1] ; Output[1] ; 5.837 ; ; ; 6.243 ; +; Input[2] ; Output[2] ; 6.788 ; ; ; 7.290 ; +; Input[3] ; Output[3] ; 5.658 ; ; ; 6.062 ; +; Input[4] ; Output[4] ; 5.604 ; ; ; 5.996 ; +; Input[5] ; Output[5] ; 5.618 ; ; ; 5.999 ; +; Input[6] ; Output[6] ; 5.609 ; ; ; 5.975 ; +; Input[7] ; Output[7] ; 5.719 ; ; ; 6.067 ; +; Input[8] ; Output[8] ; 5.570 ; ; ; 5.939 ; +; Input[9] ; Output[9] ; 5.660 ; ; ; 6.027 ; ++------------+-------------+-------+----+----+-------+ + + +---------------------------------------------- +; Slow 1200mV 85C Model Metastability Report ; +---------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + ++----------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; Input[0] ; Output[0] ; 5.307 ; ; ; 5.639 ; +; Input[1] ; Output[1] ; 5.553 ; ; ; 5.885 ; +; Input[2] ; Output[2] ; 6.515 ; ; ; 6.959 ; +; Input[3] ; Output[3] ; 5.382 ; ; ; 5.737 ; +; Input[4] ; Output[4] ; 5.331 ; ; ; 5.665 ; +; Input[5] ; Output[5] ; 5.343 ; ; ; 5.685 ; +; Input[6] ; Output[6] ; 5.334 ; ; ; 5.652 ; +; Input[7] ; Output[7] ; 5.454 ; ; ; 5.737 ; +; Input[8] ; Output[8] ; 5.301 ; ; ; 5.624 ; +; Input[9] ; Output[9] ; 5.387 ; ; ; 5.714 ; ++------------+-------------+-------+----+----+-------+ + + ++----------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; Input[0] ; Output[0] ; 5.211 ; ; ; 5.533 ; +; Input[1] ; Output[1] ; 5.447 ; ; ; 5.770 ; +; Input[2] ; Output[2] ; 6.419 ; ; ; 6.853 ; +; Input[3] ; Output[3] ; 5.283 ; ; ; 5.628 ; +; Input[4] ; Output[4] ; 5.234 ; ; ; 5.559 ; +; Input[5] ; Output[5] ; 5.246 ; ; ; 5.578 ; +; Input[6] ; Output[6] ; 5.237 ; ; ; 5.546 ; +; Input[7] ; Output[7] ; 5.353 ; ; ; 5.629 ; +; Input[8] ; Output[8] ; 5.207 ; ; ; 5.521 ; +; Input[9] ; Output[9] ; 5.291 ; ; ; 5.609 ; ++------------+-------------+-------+----+----+-------+ + + +--------------------------------------------- +; Slow 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + ++----------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; Input[0] ; Output[0] ; 3.452 ; ; ; 3.988 ; +; Input[1] ; Output[1] ; 3.612 ; ; ; 4.166 ; +; Input[2] ; Output[2] ; 4.272 ; ; ; 4.953 ; +; Input[3] ; Output[3] ; 3.494 ; ; ; 4.059 ; +; Input[4] ; Output[4] ; 3.478 ; ; ; 4.012 ; +; Input[5] ; Output[5] ; 3.478 ; ; ; 4.020 ; +; Input[6] ; Output[6] ; 3.470 ; ; ; 4.008 ; +; Input[7] ; Output[7] ; 3.523 ; ; ; 4.054 ; +; Input[8] ; Output[8] ; 3.453 ; ; ; 3.986 ; +; Input[9] ; Output[9] ; 3.532 ; ; ; 4.066 ; ++------------+-------------+-------+----+----+-------+ + + ++----------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; Input[0] ; Output[0] ; 3.383 ; ; ; 3.914 ; +; Input[1] ; Output[1] ; 3.537 ; ; ; 4.085 ; +; Input[2] ; Output[2] ; 4.203 ; ; ; 4.878 ; +; Input[3] ; Output[3] ; 3.424 ; ; ; 3.982 ; +; Input[4] ; Output[4] ; 3.409 ; ; ; 3.937 ; +; Input[5] ; Output[5] ; 3.408 ; ; ; 3.945 ; +; Input[6] ; Output[6] ; 3.401 ; ; ; 3.934 ; +; Input[7] ; Output[7] ; 3.453 ; ; ; 3.979 ; +; Input[8] ; Output[8] ; 3.385 ; ; ; 3.914 ; +; Input[9] ; Output[9] ; 3.463 ; ; ; 3.992 ; ++------------+-------------+-------+----+----+-------+ + + +--------------------------------------------- +; Fast 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++----------------------------------------------------+ +; Progagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; Input[0] ; Output[0] ; 5.696 ; ; ; 6.097 ; +; Input[1] ; Output[1] ; 5.962 ; ; ; 6.381 ; +; Input[2] ; Output[2] ; 6.904 ; ; ; 7.417 ; +; Input[3] ; Output[3] ; 5.775 ; ; ; 6.192 ; +; Input[4] ; Output[4] ; 5.720 ; ; ; 6.123 ; +; Input[5] ; Output[5] ; 5.734 ; ; ; 6.126 ; +; Input[6] ; Output[6] ; 5.724 ; ; ; 6.101 ; +; Input[7] ; Output[7] ; 5.838 ; ; ; 6.196 ; +; Input[8] ; Output[8] ; 5.683 ; ; ; 6.062 ; +; Input[9] ; Output[9] ; 5.775 ; ; ; 6.153 ; ++------------+-------------+-------+----+----+-------+ + + ++----------------------------------------------------+ +; Minimum Progagation Delay ; ++------------+-------------+-------+----+----+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+----+----+-------+ +; Input[0] ; Output[0] ; 3.383 ; ; ; 3.914 ; +; Input[1] ; Output[1] ; 3.537 ; ; ; 4.085 ; +; Input[2] ; Output[2] ; 4.203 ; ; ; 4.878 ; +; Input[3] ; Output[3] ; 3.424 ; ; ; 3.982 ; +; Input[4] ; Output[4] ; 3.409 ; ; ; 3.937 ; +; Input[5] ; Output[5] ; 3.408 ; ; ; 3.945 ; +; Input[6] ; Output[6] ; 3.401 ; ; ; 3.934 ; +; Input[7] ; Output[7] ; 3.453 ; ; ; 3.979 ; +; Input[8] ; Output[8] ; 3.385 ; ; ; 3.914 ; +; Input[9] ; Output[9] ; 3.463 ; ; ; 3.992 ; ++------------+-------------+-------+----+----+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Output[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Output[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Output[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Output[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Output[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Output[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Output[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Output[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Output[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Output[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; Input[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Input[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Input[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Input[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Input[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Input[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Input[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Input[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Input[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Input[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Output[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; Output[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; Output[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; Output[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; Output[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; Output[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; Output[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; Output[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.33 V ; -0.00317 V ; 0.162 V ; 0.063 V ; 3.54e-09 s ; 3.41e-09 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.33 V ; -0.00317 V ; 0.162 V ; 0.063 V ; 3.54e-09 s ; 3.41e-09 s ; Yes ; Yes ; +; Output[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; Output[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.68e-07 V ; 2.35 V ; -0.0132 V ; 0.2 V ; 0.027 V ; 5.26e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 5.68e-07 V ; 2.35 V ; -0.0132 V ; 0.2 V ; 0.027 V ; 5.26e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.36e-07 V ; 2.35 V ; -0.00444 V ; 0.18 V ; 0.019 V ; 7.23e-10 s ; 9.82e-10 s ; Yes ; Yes ; 2.32 V ; 9.36e-07 V ; 2.35 V ; -0.00444 V ; 0.18 V ; 0.019 V ; 7.23e-10 s ; 9.82e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Output[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; Output[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; Output[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; Output[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; Output[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; Output[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; Output[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; Output[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.64 V ; -0.0109 V ; 0.244 V ; 0.16 V ; 2.42e-09 s ; 2.37e-09 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.64 V ; -0.0109 V ; 0.244 V ; 0.16 V ; 2.42e-09 s ; 2.37e-09 s ; No ; Yes ; +; Output[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; Output[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.72 V ; -0.0747 V ; 0.28 V ; 0.169 V ; 3.1e-10 s ; 3.01e-10 s ; No ; Yes ; 2.62 V ; 2.22e-08 V ; 2.72 V ; -0.0747 V ; 0.28 V ; 0.169 V ; 3.1e-10 s ; 3.01e-10 s ; No ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.53e-08 V ; 2.7 V ; -0.0212 V ; 0.204 V ; 0.049 V ; 4.85e-10 s ; 6.73e-10 s ; No ; Yes ; 2.62 V ; 3.53e-08 V ; 2.7 V ; -0.0212 V ; 0.204 V ; 0.049 V ; 4.85e-10 s ; 6.73e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 10 ; 10 ; +; Unconstrained Input Port Paths ; 10 ; 10 ; +; Unconstrained Output Ports ; 10 ; 10 ; +; Unconstrained Output Port Paths ; 10 ; 10 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + Info: Processing started: Tue Feb 16 15:16:11 2016 +Info: Command: quartus_sta glu_Logic -c glu_Logic +Info: qsta_default_script.tcl version: #1 +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 487 megabytes + Info: Processing ended: Tue Feb 16 15:16:15 2016 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/glue_logic/output_files/glu_Logic.sta.summary b/glue_logic/output_files/glu_Logic.sta.summary new file mode 100644 index 0000000..33f7436 --- /dev/null +++ b/glue_logic/output_files/glu_Logic.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ |