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| author | Yann Herklotz <ymherklotz@gmail.com> | 2016-11-15 21:43:12 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-11-15 21:43:12 +0000 |
| commit | 2819e673167ff6a259be4f3caf5ecb7276c3799c (patch) | |
| tree | 48ac152b235630216a2af2defbe402f1323744d9 | |
| parent | 46f258badd3a341940ceb742af84cd99db98e55d (diff) | |
| download | VerilogCoursework-2819e673167ff6a259be4f3caf5ecb7276c3799c.tar.gz VerilogCoursework-2819e673167ff6a259be4f3caf5ecb7276c3799c.zip | |
Update README.md
| -rw-r--r-- | README.md | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -1,2 +1,2 @@ -# digital_verilog_coursework -Digital coursework learning verilog and using quartus to program a Cyclone V FPGA +# Digital Verilog Coursework +Digital coursework learning verilog and using quartus to program a Cyclone V FPGA on a DE1 Terasic board. |