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| author | Yann Herklotz <ymherklotz@gmail.com> | 2016-11-15 21:35:59 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-11-15 21:35:59 +0000 |
| commit | 46f258badd3a341940ceb742af84cd99db98e55d (patch) | |
| tree | c7af6962c415eff0b191b48445e8cdaede53a870 | |
| parent | ee5d729de8ea22b4d7524bf839ba08fcb4b3843d (diff) | |
| download | VerilogCoursework-46f258badd3a341940ceb742af84cd99db98e55d.tar.gz VerilogCoursework-46f258badd3a341940ceb742af84cd99db98e55d.zip | |
Create README.md
| -rw-r--r-- | README.md | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/README.md b/README.md new file mode 100644 index 0000000..0d7a282 --- /dev/null +++ b/README.md @@ -0,0 +1,2 @@ +# digital_verilog_coursework +Digital coursework learning verilog and using quartus to program a Cyclone V FPGA |