diff options
| author | zedarider <ymherklotz@gmail.com> | 2016-11-15 21:33:02 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-11-15 21:33:02 +0000 |
| commit | ee5d729de8ea22b4d7524bf839ba08fcb4b3843d (patch) | |
| tree | a6cbbd40144834affb26acfeaaa8e9159b7cf4a9 | |
| download | VerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.tar.gz VerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.zip | |
adding first project and initial files
500 files changed, 23527 insertions, 0 deletions
diff --git a/Extra/Thumbs.db b/Extra/Thumbs.db Binary files differnew file mode 100644 index 0000000..8fcad45 --- /dev/null +++ b/Extra/Thumbs.db diff --git a/Extra/ex1/Ex1BDF.PNG b/Extra/ex1/Ex1BDF.PNG Binary files differnew file mode 100644 index 0000000..d0c13ee --- /dev/null +++ b/Extra/ex1/Ex1BDF.PNG diff --git a/Extra/ex1/Ex1Sol.PNG b/Extra/ex1/Ex1Sol.PNG Binary files differnew file mode 100644 index 0000000..3342bea --- /dev/null +++ b/Extra/ex1/Ex1Sol.PNG diff --git a/Extra/ex1/Ex1SolTry2.PNG b/Extra/ex1/Ex1SolTry2.PNG Binary files differnew file mode 100644 index 0000000..d78e755 --- /dev/null +++ b/Extra/ex1/Ex1SolTry2.PNG diff --git a/Extra/ex1/PinPlannerEx1.PNG b/Extra/ex1/PinPlannerEx1.PNG Binary files differnew file mode 100644 index 0000000..7f619f7 --- /dev/null +++ b/Extra/ex1/PinPlannerEx1.PNG diff --git a/Extra/ex1/RiseAndFall0degree.PNG b/Extra/ex1/RiseAndFall0degree.PNG Binary files differnew file mode 100644 index 0000000..f3a817f --- /dev/null +++ b/Extra/ex1/RiseAndFall0degree.PNG diff --git a/Extra/ex1/RiseAndFall85degree.PNG b/Extra/ex1/RiseAndFall85degree.PNG Binary files differnew file mode 100644 index 0000000..b2d3376 --- /dev/null +++ b/Extra/ex1/RiseAndFall85degree.PNG diff --git a/Extra/ex1/ex1Schematic.PNG b/Extra/ex1/ex1Schematic.PNG Binary files differnew file mode 100644 index 0000000..54b7992 --- /dev/null +++ b/Extra/ex1/ex1Schematic.PNG diff --git a/Extra/ex2/hex_to_7seg.PNG b/Extra/ex2/hex_to_7seg.PNG Binary files differnew file mode 100644 index 0000000..dd6180b --- /dev/null +++ b/Extra/ex2/hex_to_7seg.PNG diff --git a/Extra/ex2/top_ex2.PNG b/Extra/ex2/top_ex2.PNG Binary files differnew file mode 100644 index 0000000..d547965 --- /dev/null +++ b/Extra/ex2/top_ex2.PNG diff --git a/Extra/ex3/top_level.PNG b/Extra/ex3/top_level.PNG Binary files differnew file mode 100644 index 0000000..28cecbb --- /dev/null +++ b/Extra/ex3/top_level.PNG diff --git a/Extra/ex4/Thumbs.db b/Extra/ex4/Thumbs.db Binary files differnew file mode 100644 index 0000000..37ac678 --- /dev/null +++ b/Extra/ex4/Thumbs.db diff --git a/Extra/ex4/ex4_v.PNG b/Extra/ex4/ex4_v.PNG Binary files differnew file mode 100644 index 0000000..1d179c0 --- /dev/null +++ b/Extra/ex4/ex4_v.PNG diff --git a/Extra/ex4/numComponents10bits.PNG b/Extra/ex4/numComponents10bits.PNG Binary files differnew file mode 100644 index 0000000..640ef6b --- /dev/null +++ b/Extra/ex4/numComponents10bits.PNG diff --git a/Extra/ex4/numComponents16bits.PNG b/Extra/ex4/numComponents16bits.PNG Binary files differnew file mode 100644 index 0000000..c69c90e --- /dev/null +++ b/Extra/ex4/numComponents16bits.PNG diff --git a/part_1/ex1/BDF_Files/My7seg.bdf b/part_1/ex1/BDF_Files/My7seg.bdf new file mode 100644 index 0000000..d410eda --- /dev/null +++ b/part_1/ex1/BDF_Files/My7seg.bdf @@ -0,0 +1,2357 @@ +/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+*/
+//#pragma file_not_in_maxplusii_format
+(header "graphic" (version "1.4"))
+(pin
+ (input)
+ (rect -120 80 48 96)
+ (text "INPUT" (rect 133 0 174 11)(font "Arial" (font_size 6)))
+ (text "in[3..0]" (rect 5 0 71 14)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12))
+ (line (pt 92 4)(pt 117 4))
+ (line (pt 121 8)(pt 168 8))
+ (line (pt 92 12)(pt 92 4))
+ (line (pt 117 4)(pt 121 8))
+ (line (pt 117 12)(pt 121 8))
+ )
+ (text "VCC" (rect 136 7 160 18)(font "Arial" (font_size 6)))
+ (annotation_block (location)(rect -168 96 -112 152))
+)
+(pin
+ (output)
+ (rect 608 728 784 744)
+ (text "OUTPUT" (rect 1 0 50 11)(font "Arial" (font_size 6)))
+ (text "out[6..0]" (rect 90 0 164 14)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8))
+ (line (pt 52 4)(pt 78 4))
+ (line (pt 52 12)(pt 78 12))
+ (line (pt 52 12)(pt 52 4))
+ (line (pt 78 4)(pt 82 8))
+ (line (pt 82 8)(pt 78 12))
+ (line (pt 78 12)(pt 82 8))
+ )
+ (annotation_block (location)(rect 1416 80 1472 128))
+)
+(symbol
+ (rect 160 96 208 128)
+ (text "NOT" (rect 1 0 25 11)(font "Arial" (font_size 6)))
+ (text "inst3" (rect 3 21 44 35)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN" (rect 2 7 13 21)(font "Courier New" (bold))(invisible))
+ (text "IN" (rect 2 7 13 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 13 16))
+ )
+ (port
+ (pt 48 16)
+ (output)
+ (text "OUT" (rect 32 7 49 21)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 32 7 49 21)(font "Courier New" (bold))(invisible))
+ (line (pt 39 16)(pt 48 16))
+ )
+ (drawing
+ (line (pt 13 25)(pt 13 7))
+ (line (pt 13 7)(pt 31 16))
+ (line (pt 13 25)(pt 31 16))
+ (circle (rect 31 12 39 20))
+ )
+)
+(symbol
+ (rect 160 128 208 160)
+ (text "NOT" (rect 1 0 25 11)(font "Arial" (font_size 6)))
+ (text "inst4" (rect 3 21 44 35)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN" (rect 2 7 13 21)(font "Courier New" (bold))(invisible))
+ (text "IN" (rect 2 7 13 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 13 16))
+ )
+ (port
+ (pt 48 16)
+ (output)
+ (text "OUT" (rect 32 7 49 21)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 32 7 49 21)(font "Courier New" (bold))(invisible))
+ (line (pt 39 16)(pt 48 16))
+ )
+ (drawing
+ (line (pt 13 25)(pt 13 7))
+ (line (pt 13 7)(pt 31 16))
+ (line (pt 13 25)(pt 31 16))
+ (circle (rect 31 12 39 20))
+ )
+)
+(symbol
+ (rect 160 160 208 192)
+ (text "NOT" (rect 1 0 25 11)(font "Arial" (font_size 6)))
+ (text "inst5" (rect 3 21 44 35)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN" (rect 2 7 13 21)(font "Courier New" (bold))(invisible))
+ (text "IN" (rect 2 7 13 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 13 16))
+ )
+ (port
+ (pt 48 16)
+ (output)
+ (text "OUT" (rect 32 7 49 21)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 32 7 49 21)(font "Courier New" (bold))(invisible))
+ (line (pt 39 16)(pt 48 16))
+ )
+ (drawing
+ (line (pt 13 25)(pt 13 7))
+ (line (pt 13 7)(pt 31 16))
+ (line (pt 13 25)(pt 31 16))
+ (circle (rect 31 12 39 20))
+ )
+)
+(symbol
+ (rect 160 192 208 224)
+ (text "NOT" (rect 1 0 25 11)(font "Arial" (font_size 6)))
+ (text "inst6" (rect 3 21 44 35)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN" (rect 2 7 13 21)(font "Courier New" (bold))(invisible))
+ (text "IN" (rect 2 7 13 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 13 16))
+ )
+ (port
+ (pt 48 16)
+ (output)
+ (text "OUT" (rect 32 7 49 21)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 32 7 49 21)(font "Courier New" (bold))(invisible))
+ (line (pt 39 16)(pt 48 16))
+ )
+ (drawing
+ (line (pt 13 25)(pt 13 7))
+ (line (pt 13 7)(pt 31 16))
+ (line (pt 13 25)(pt 31 16))
+ (circle (rect 31 12 39 20))
+ )
+)
+(symbol
+ (rect 80 544 144 592)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst10" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 96 600 160 648)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst11" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 96 656 160 704)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst12" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 96 712 160 792)
+ (text "AND4" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst13" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 18 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 18 32))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 18 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 18 64))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 46 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 18 28)(pt 34 28))
+ (line (pt 18 52)(pt 18 28))
+ (line (pt 18 67)(pt 18 13))
+ (line (pt 34 53)(pt 18 53))
+ (arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+ )
+)
+(symbol
+ (rect 184 608 248 688)
+ (text "OR4" (rect 1 0 25 11)(font "Arial" (font_size 6)))
+ (text "inst14" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 13 16))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 15 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 13 64))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 48 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 13 67)(pt 13 51))
+ (line (pt 25 52)(pt 13 52))
+ (line (pt 13 12)(pt 13 29))
+ (line (pt 13 29)(pt 25 29))
+ (arc (pt 7 45)(pt 7 35)(rect -14 24 19 57))
+ (arc (pt 49 40)(pt 25 29)(rect -6 29 57 92))
+ (arc (pt 25 51)(pt 49 40)(rect -6 -11 57 52))
+ )
+)
+(symbol
+ (rect 360 280 424 360)
+ (text "AND4" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst19" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 18 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 18 32))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 18 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 18 64))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 46 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 18 28)(pt 34 28))
+ (line (pt 18 52)(pt 18 28))
+ (line (pt 18 67)(pt 18 13))
+ (line (pt 34 53)(pt 18 53))
+ (arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+ )
+)
+(symbol
+ (rect 360 368 424 416)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst20" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 360 480 424 560)
+ (text "AND4" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst22" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 18 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 18 32))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 18 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 18 64))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 46 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 18 28)(pt 34 28))
+ (line (pt 18 52)(pt 18 28))
+ (line (pt 18 67)(pt 18 13))
+ (line (pt 34 53)(pt 18 53))
+ (arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+ )
+)
+(symbol
+ (rect 456 384 520 464)
+ (text "OR4" (rect 1 0 25 11)(font "Arial" (font_size 6)))
+ (text "inst23" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 13 16))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 15 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 13 64))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 48 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 13 67)(pt 13 51))
+ (line (pt 25 52)(pt 13 52))
+ (line (pt 13 12)(pt 13 29))
+ (line (pt 13 29)(pt 25 29))
+ (arc (pt 7 45)(pt 7 35)(rect -14 24 19 57))
+ (arc (pt 49 40)(pt 25 29)(rect -6 29 57 92))
+ (arc (pt 25 51)(pt 49 40)(rect -6 -11 57 52))
+ )
+)
+(symbol
+ (rect 360 576 424 624)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst24" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 360 632 424 680)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst25" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 360 688 424 768)
+ (text "AND4" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst26" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 18 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 18 32))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 18 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 18 64))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 46 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 18 28)(pt 34 28))
+ (line (pt 18 52)(pt 18 28))
+ (line (pt 18 67)(pt 18 13))
+ (line (pt 34 53)(pt 18 53))
+ (arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+ )
+)
+(symbol
+ (rect 464 632 528 680)
+ (text "OR3" (rect 1 0 25 11)(font "Arial" (font_size 6)))
+ (text "inst27" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 18 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 24 19 38)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 24 19 38)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 47 15 64 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 47 15 64 29)(font "Courier New" (bold))(invisible))
+ (line (pt 49 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 14 13)(pt 25 13))
+ (line (pt 14 36)(pt 25 36))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
+ (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
+ (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
+ )
+)
+(symbol
+ (rect 632 88 696 136)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst28" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 632 144 696 192)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst29" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 632 200 696 280)
+ (text "AND4" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst30" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 18 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 18 32))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 18 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 18 64))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 46 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 18 28)(pt 34 28))
+ (line (pt 18 52)(pt 18 28))
+ (line (pt 18 67)(pt 18 13))
+ (line (pt 34 53)(pt 18 53))
+ (arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+ )
+)
+(symbol
+ (rect 632 288 696 336)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst31" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 720 176 784 256)
+ (text "OR4" (rect 1 0 25 11)(font "Arial" (font_size 6)))
+ (text "inst32" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 13 16))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 15 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 13 64))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 48 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 13 67)(pt 13 51))
+ (line (pt 25 52)(pt 13 52))
+ (line (pt 13 12)(pt 13 29))
+ (line (pt 13 29)(pt 25 29))
+ (arc (pt 7 45)(pt 7 35)(rect -14 24 19 57))
+ (arc (pt 49 40)(pt 25 29)(rect -6 29 57 92))
+ (arc (pt 25 51)(pt 49 40)(rect -6 -11 57 52))
+ )
+)
+(symbol
+ (rect 632 360 696 440)
+ (text "AND4" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst33" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 18 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 18 32))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 18 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 18 64))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 46 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 18 28)(pt 34 28))
+ (line (pt 18 52)(pt 18 28))
+ (line (pt 18 67)(pt 18 13))
+ (line (pt 34 53)(pt 18 53))
+ (arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+ )
+)
+(symbol
+ (rect 632 448 696 528)
+ (text "AND4" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst34" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 18 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 18 32))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 18 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 18 64))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 46 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 18 28)(pt 34 28))
+ (line (pt 18 52)(pt 18 28))
+ (line (pt 18 67)(pt 18 13))
+ (line (pt 34 53)(pt 18 53))
+ (arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+ )
+)
+(symbol
+ (rect 632 536 696 616)
+ (text "AND4" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst35" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 18 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 18 32))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 18 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 18 64))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 46 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 18 28)(pt 34 28))
+ (line (pt 18 52)(pt 18 28))
+ (line (pt 18 67)(pt 18 13))
+ (line (pt 34 53)(pt 18 53))
+ (arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+ )
+)
+(symbol
+ (rect 632 624 696 704)
+ (text "AND4" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst36" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 18 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 18 32))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 18 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 18 64))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 46 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 18 28)(pt 34 28))
+ (line (pt 18 52)(pt 18 28))
+ (line (pt 18 67)(pt 18 13))
+ (line (pt 34 53)(pt 18 53))
+ (arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+ )
+)
+(symbol
+ (rect 736 496 800 576)
+ (text "OR4" (rect 1 0 25 11)(font "Arial" (font_size 6)))
+ (text "inst37" (rect 3 69 52 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 13 16))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 15 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 13 64))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 48 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 13 67)(pt 13 51))
+ (line (pt 25 52)(pt 13 52))
+ (line (pt 13 12)(pt 13 29))
+ (line (pt 13 29)(pt 25 29))
+ (arc (pt 7 45)(pt 7 35)(rect -14 24 19 57))
+ (arc (pt 49 40)(pt 25 29)(rect -6 29 57 92))
+ (arc (pt 25 51)(pt 49 40)(rect -6 -11 57 52))
+ )
+)
+(symbol
+ (rect 352 424 416 472)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst21" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 40 280 104 328)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst" (rect 3 37 36 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 40 336 104 416)
+ (text "AND4" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst1" (rect 3 69 44 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 18 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 18 32))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 18 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 18 64))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 46 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 18 28)(pt 34 28))
+ (line (pt 18 52)(pt 18 28))
+ (line (pt 18 67)(pt 18 13))
+ (line (pt 34 53)(pt 18 53))
+ (arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+ )
+)
+(symbol
+ (rect 40 440 104 520)
+ (text "AND4" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst2" (rect 3 69 44 83)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 18 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 18 32))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 39 19 53)(font "Courier New" (bold))(invisible))
+ (line (pt 0 48)(pt 18 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (text "IN4" (rect 2 55 19 69)(font "Courier New" (bold))(invisible))
+ (line (pt 0 64)(pt 18 64))
+ )
+ (port
+ (pt 64 40)
+ (output)
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 31 65 45)(font "Courier New" (bold))(invisible))
+ (line (pt 46 40)(pt 64 40))
+ )
+ (drawing
+ (line (pt 18 28)(pt 34 28))
+ (line (pt 18 52)(pt 18 28))
+ (line (pt 18 67)(pt 18 13))
+ (line (pt 34 53)(pt 18 53))
+ (arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+ )
+)
+(symbol
+ (rect 144 352 208 400)
+ (text "OR3" (rect 1 0 25 11)(font "Arial" (font_size 6)))
+ (text "inst7" (rect 3 37 44 51)(font "Arial" ))
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 18 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 24 19 38)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 24 19 38)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 47 15 64 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 47 15 64 29)(font "Courier New" (bold))(invisible))
+ (line (pt 49 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 14 13)(pt 25 13))
+ (line (pt 14 36)(pt 25 36))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
+ (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
+ (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
+ )
+)
+(symbol
+ (rect 320 88 384 136)
+ (text "AND2" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst8" (rect 3 37 44 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12))
+ (line (pt 14 37)(pt 31 37))
+ (line (pt 14 12)(pt 14 37))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
+ )
+)
+(symbol
+ (rect 320 144 384 192)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst9" (rect 3 37 44 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 320 200 384 248)
+ (text "AND3" (rect 1 0 34 11)(font "Arial" (font_size 6)))
+ (text "inst15" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 16 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 23 19 37)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 29)(font "Courier New" (bold))(invisible))
+ (line (pt 43 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 16 12)(pt 31 12))
+ (line (pt 16 37)(pt 31 37))
+ (line (pt 16 12)(pt 16 37))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
+ )
+)
+(symbol
+ (rect 448 144 512 192)
+ (text "OR3" (rect 1 0 25 11)(font "Arial" (font_size 6)))
+ (text "inst16" (rect 3 37 52 51)(font "Arial" ))
+ (port
+ (pt 0 24)
+ (input)
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 15 19 29)(font "Courier New" (bold))(invisible))
+ (line (pt 0 24)(pt 18 24))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN3" (rect 2 24 19 38)(font "Courier New" (bold))(invisible))
+ (text "IN3" (rect 2 24 19 38)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 16 32))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 21)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 16 16))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 47 15 64 29)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 47 15 64 29)(font "Courier New" (bold))(invisible))
+ (line (pt 49 24)(pt 64 24))
+ )
+ (drawing
+ (line (pt 14 13)(pt 25 13))
+ (line (pt 14 36)(pt 25 36))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
+ (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
+ (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
+ )
+)
+(connector
+ (pt 128 88)
+ (pt 136 88)
+)
+(connector
+ (text "in[2]" (rect 88 86 102 127)(font "Arial" )(vertical))
+ (pt 104 176)
+ (pt 104 88)
+)
+(connector
+ (pt 104 176)
+ (pt 160 176)
+)
+(connector
+ (text "in[1]" (rect 104 86 118 127)(font "Arial" )(vertical))
+ (pt 120 144)
+ (pt 120 88)
+)
+(connector
+ (pt 120 144)
+ (pt 160 144)
+)
+(connector
+ (pt 120 88)
+ (pt 128 88)
+ (bus)
+)
+(connector
+ (pt 136 88)
+ (pt 136 112)
+)
+(connector
+ (text "in[0]" (rect 147 96 188 110)(font "Arial" ))
+ (pt 136 112)
+ (pt 160 112)
+)
+(connector
+ (text "nin[0]" (rect 216 96 265 110)(font "Arial" ))
+ (pt 208 112)
+ (pt 240 112)
+)
+(connector
+ (text "nin[1]" (rect 222 128 271 142)(font "Arial" ))
+ (pt 208 144)
+ (pt 248 144)
+)
+(connector
+ (text "nin[2]" (rect 216 160 265 174)(font "Arial" ))
+ (pt 208 176)
+ (pt 248 176)
+)
+(connector
+ (text "nin[3]" (rect 216 192 265 206)(font "Arial" ))
+ (pt 208 208)
+ (pt 248 208)
+)
+(connector
+ (pt 104 88)
+ (pt 120 88)
+ (bus)
+)
+(connector
+ (pt 160 208)
+ (pt 72 208)
+)
+(connector
+ (pt 48 88)
+ (pt 72 88)
+ (bus)
+)
+(connector
+ (pt 72 88)
+ (pt 104 88)
+ (bus)
+)
+(connector
+ (text "in[3]" (rect 56 174 70 215)(font "Arial" )(vertical))
+ (pt 72 88)
+ (pt 72 208)
+)
+(connector
+ (text "nin[3]" (rect 88 600 137 614)(font "Arial" ))
+ (pt 96 616)
+ (pt 80 616)
+)
+(connector
+ (text "nin[2]" (rect 80 608 129 622)(font "Arial" ))
+ (pt 96 624)
+ (pt 72 624)
+)
+(connector
+ (text "in[0]" (rect 88 616 129 630)(font "Arial" ))
+ (pt 96 632)
+ (pt 80 632)
+)
+(connector
+ (text "nin[3]" (rect 88 656 137 670)(font "Arial" ))
+ (pt 96 672)
+ (pt 80 672)
+)
+(connector
+ (text "in[1]" (rect 88 664 129 678)(font "Arial" ))
+ (pt 96 680)
+ (pt 80 680)
+)
+(connector
+ (text "in[0]" (rect 88 672 129 686)(font "Arial" ))
+ (pt 96 688)
+ (pt 80 688)
+)
+(connector
+ (text "in[3]" (rect 88 712 129 726)(font "Arial" ))
+ (pt 96 728)
+ (pt 80 728)
+)
+(connector
+ (text "in[2]" (rect 88 728 129 742)(font "Arial" ))
+ (pt 96 744)
+ (pt 80 744)
+)
+(connector
+ (text "nin[1]" (rect 88 744 137 758)(font "Arial" ))
+ (pt 96 760)
+ (pt 80 760)
+)
+(connector
+ (text "in[0]" (rect 88 760 129 774)(font "Arial" ))
+ (pt 96 776)
+ (pt 80 776)
+)
+(connector
+ (pt 184 640)
+ (pt 160 640)
+)
+(connector
+ (pt 160 640)
+ (pt 160 624)
+)
+(connector
+ (pt 184 656)
+ (pt 176 656)
+)
+(connector
+ (pt 176 656)
+ (pt 176 680)
+)
+(connector
+ (pt 160 680)
+ (pt 176 680)
+)
+(connector
+ (pt 184 672)
+ (pt 184 752)
+)
+(connector
+ (pt 160 752)
+ (pt 184 752)
+)
+(connector
+ (text "nin[3]" (rect 312 288 361 302)(font "Arial" ))
+ (pt 360 296)
+ (pt 344 296)
+)
+(connector
+ (text "in[2]" (rect 312 304 353 318)(font "Arial" ))
+ (pt 360 312)
+ (pt 344 312)
+)
+(connector
+ (text "nin[1]" (rect 312 320 361 334)(font "Arial" ))
+ (pt 360 328)
+ (pt 344 328)
+)
+(connector
+ (text "nin[0]" (rect 312 336 361 350)(font "Arial" ))
+ (pt 360 344)
+ (pt 344 344)
+)
+(connector
+ (text "in[3]" (rect 320 480 361 494)(font "Arial" ))
+ (pt 360 496)
+ (pt 344 496)
+)
+(connector
+ (text "nin[2]" (rect 320 504 369 518)(font "Arial" ))
+ (pt 360 512)
+ (pt 344 512)
+)
+(connector
+ (text "in[1]" (rect 328 520 369 534)(font "Arial" ))
+ (pt 360 528)
+ (pt 344 528)
+)
+(connector
+ (pt 456 400)
+ (pt 448 400)
+)
+(connector
+ (pt 448 400)
+ (pt 448 320)
+)
+(connector
+ (pt 424 320)
+ (pt 448 320)
+)
+(connector
+ (pt 456 416)
+ (pt 440 416)
+)
+(connector
+ (pt 456 448)
+ (pt 440 448)
+)
+(connector
+ (pt 440 448)
+ (pt 440 520)
+)
+(connector
+ (pt 424 520)
+ (pt 440 520)
+)
+(connector
+ (text "out[3]" (rect 528 408 577 422)(font "Arial" ))
+ (pt 520 424)
+ (pt 552 424)
+)
+(connector
+ (text "nin[3]" (rect 312 696 361 710)(font "Arial" ))
+ (pt 360 704)
+ (pt 344 704)
+)
+(connector
+ (text "nin[2]" (rect 312 712 361 726)(font "Arial" ))
+ (pt 360 720)
+ (pt 344 720)
+)
+(connector
+ (text "in[1]" (rect 312 728 353 742)(font "Arial" ))
+ (pt 360 736)
+ (pt 344 736)
+)
+(connector
+ (text "nin[0]" (rect 312 744 361 758)(font "Arial" ))
+ (pt 360 752)
+ (pt 344 752)
+)
+(connector
+ (pt 464 648)
+ (pt 456 648)
+)
+(connector
+ (pt 424 600)
+ (pt 456 600)
+)
+(connector
+ (pt 456 600)
+ (pt 456 648)
+)
+(connector
+ (pt 424 656)
+ (pt 464 656)
+)
+(connector
+ (pt 464 664)
+ (pt 440 664)
+)
+(connector
+ (pt 440 664)
+ (pt 440 728)
+)
+(connector
+ (pt 424 728)
+ (pt 440 728)
+)
+(connector
+ (text "in[3]" (rect 576 88 617 102)(font "Arial" ))
+ (pt 600 104)
+ (pt 632 104)
+)
+(connector
+ (text "in[2]" (rect 576 104 617 118)(font "Arial" ))
+ (pt 632 112)
+ (pt 608 112)
+)
+(connector
+ (text "nin[0]" (rect 576 120 625 134)(font "Arial" ))
+ (pt 632 120)
+ (pt 608 120)
+)
+(connector
+ (text "nin[3]" (rect 576 208 625 222)(font "Arial" ))
+ (pt 632 216)
+ (pt 608 216)
+)
+(connector
+ (text "in[2]" (rect 576 224 617 238)(font "Arial" ))
+ (pt 632 232)
+ (pt 608 232)
+)
+(connector
+ (text "nin[1]" (rect 576 240 625 254)(font "Arial" ))
+ (pt 632 248)
+ (pt 608 248)
+)
+(connector
+ (text "in[0]" (rect 576 256 617 270)(font "Arial" ))
+ (pt 632 264)
+ (pt 608 264)
+)
+(connector
+ (text "in[2]" (rect 576 296 617 310)(font "Arial" ))
+ (pt 632 304)
+ (pt 608 304)
+)
+(connector
+ (text "nin[0]" (rect 592 320 641 334)(font "Arial" ))
+ (pt 632 320)
+ (pt 616 320)
+)
+(connector
+ (pt 720 192)
+ (pt 712 192)
+)
+(connector
+ (pt 712 192)
+ (pt 712 112)
+)
+(connector
+ (pt 696 112)
+ (pt 712 112)
+)
+(connector
+ (pt 720 224)
+ (pt 704 224)
+)
+(connector
+ (pt 704 224)
+ (pt 704 240)
+)
+(connector
+ (pt 696 240)
+ (pt 704 240)
+)
+(connector
+ (pt 720 240)
+ (pt 712 240)
+)
+(connector
+ (pt 712 240)
+ (pt 712 312)
+)
+(connector
+ (pt 696 312)
+ (pt 712 312)
+)
+(connector
+ (text "nin[3]" (rect 584 368 633 382)(font "Arial" ))
+ (pt 632 376)
+ (pt 616 376)
+)
+(connector
+ (text "in[2]" (rect 592 384 633 398)(font "Arial" ))
+ (pt 632 392)
+ (pt 616 392)
+)
+(connector
+ (text "nin[1]" (rect 592 400 641 414)(font "Arial" ))
+ (pt 632 408)
+ (pt 616 408)
+)
+(connector
+ (text "nin[0]" (rect 594 416 643 430)(font "Arial" ))
+ (pt 632 424)
+ (pt 624 424)
+)
+(connector
+ (text "nin[3]" (rect 576 456 625 470)(font "Arial" ))
+ (pt 632 464)
+ (pt 608 464)
+)
+(connector
+ (text "nin[2]" (rect 576 472 625 486)(font "Arial" ))
+ (pt 632 480)
+ (pt 608 480)
+)
+(connector
+ (text "nin[1]" (rect 576 488 625 502)(font "Arial" ))
+ (pt 632 496)
+ (pt 608 496)
+)
+(connector
+ (text "in[0]" (rect 576 504 617 518)(font "Arial" ))
+ (pt 632 512)
+ (pt 608 512)
+)
+(connector
+ (text "in[3]" (rect 584 536 625 550)(font "Arial" ))
+ (pt 632 552)
+ (pt 616 552)
+)
+(connector
+ (text "in[2]" (rect 584 560 625 574)(font "Arial" ))
+ (pt 632 568)
+ (pt 616 568)
+)
+(connector
+ (text "nin[1]" (rect 584 576 633 590)(font "Arial" ))
+ (pt 632 584)
+ (pt 616 584)
+)
+(connector
+ (text "in[0]" (rect 592 592 633 606)(font "Arial" ))
+ (pt 632 600)
+ (pt 616 600)
+)
+(connector
+ (text "nin[2]" (rect 584 648 633 662)(font "Arial" ))
+ (pt 632 656)
+ (pt 616 656)
+)
+(connector
+ (text "in[1]" (rect 584 664 625 678)(font "Arial" ))
+ (pt 632 672)
+ (pt 608 672)
+)
+(connector
+ (text "in[0]" (rect 568 680 609 694)(font "Arial" ))
+ (pt 632 688)
+ (pt 592 688)
+)
+(connector
+ (pt 696 400)
+ (pt 736 400)
+)
+(connector
+ (pt 736 400)
+ (pt 736 512)
+)
+(connector
+ (pt 736 528)
+ (pt 712 528)
+)
+(connector
+ (pt 712 528)
+ (pt 712 488)
+)
+(connector
+ (pt 696 488)
+ (pt 712 488)
+)
+(connector
+ (pt 736 544)
+ (pt 712 544)
+)
+(connector
+ (pt 712 544)
+ (pt 712 576)
+)
+(connector
+ (pt 696 576)
+ (pt 712 576)
+)
+(connector
+ (pt 736 560)
+ (pt 720 560)
+)
+(connector
+ (pt 720 560)
+ (pt 720 664)
+)
+(connector
+ (pt 696 664)
+ (pt 720 664)
+)
+(connector
+ (text "out[2]" (rect 536 640 585 654)(font "Arial" ))
+ (pt 528 656)
+ (pt 544 656)
+)
+(connector
+ (text "out[0]" (rect 808 520 857 534)(font "Arial" ))
+ (pt 800 536)
+ (pt 816 536)
+)
+(connector
+ (text "out[1]" (rect 792 200 841 214)(font "Arial" ))
+ (pt 784 216)
+ (pt 808 216)
+)
+(connector
+ (text "nin[3]" (rect 64 544 113 558)(font "Arial" ))
+ (pt 56 560)
+ (pt 80 560)
+)
+(connector
+ (text "nin[2]" (rect 64 552 113 566)(font "Arial" ))
+ (pt 56 568)
+ (pt 80 568)
+)
+(connector
+ (text "in[1]" (rect 64 560 105 574)(font "Arial" ))
+ (pt 56 576)
+ (pt 80 576)
+)
+(connector
+ (pt 184 624)
+ (pt 168 624)
+)
+(connector
+ (pt 168 624)
+ (pt 168 568)
+)
+(connector
+ (pt 144 568)
+ (pt 168 568)
+)
+(connector
+ (text "out[5]" (rect 256 632 305 646)(font "Arial" ))
+ (pt 248 648)
+ (pt 272 648)
+)
+(connector
+ (pt 456 432)
+ (pt 432 432)
+)
+(connector
+ (pt 440 416)
+ (pt 440 392)
+)
+(connector
+ (pt 440 392)
+ (pt 424 392)
+)
+(connector
+ (text "nin[2]" (rect 312 368 361 382)(font "Arial" ))
+ (pt 344 384)
+ (pt 360 384)
+)
+(connector
+ (text "nin[1]" (rect 312 384 361 398)(font "Arial" ))
+ (pt 344 392)
+ (pt 360 392)
+)
+(connector
+ (text "in[0]" (rect 312 400 353 414)(font "Arial" ))
+ (pt 344 400)
+ (pt 360 400)
+)
+(connector
+ (pt 432 432)
+ (pt 432 448)
+)
+(connector
+ (pt 432 448)
+ (pt 416 448)
+)
+(connector
+ (pt 352 456)
+ (pt 344 456)
+)
+(connector
+ (pt 344 456)
+ (pt 344 464)
+)
+(connector
+ (text "in[0]" (rect 288 464 329 478)(font "Arial" ))
+ (pt 344 464)
+ (pt 312 464)
+)
+(connector
+ (text "nin[0]" (rect 312 536 361 550)(font "Arial" ))
+ (pt 360 544)
+ (pt 344 544)
+)
+(connector
+ (text "in[1]" (rect 288 448 329 462)(font "Arial" ))
+ (pt 352 448)
+ (pt 312 448)
+)
+(connector
+ (text "in[2]" (rect 304 424 345 438)(font "Arial" ))
+ (pt 296 440)
+ (pt 352 440)
+)
+(connector
+ (text "in[3]" (rect 304 576 345 590)(font "Arial" ))
+ (pt 360 592)
+ (pt 328 592)
+)
+(connector
+ (text "in[2]" (rect 304 592 345 606)(font "Arial" ))
+ (pt 360 600)
+ (pt 328 600)
+)
+(connector
+ (text "nin[0]" (rect 304 608 353 622)(font "Arial" ))
+ (pt 360 608)
+ (pt 336 608)
+)
+(connector
+ (text "in[3]" (rect 304 632 345 646)(font "Arial" ))
+ (pt 360 648)
+ (pt 328 648)
+)
+(connector
+ (text "in[2]" (rect 304 648 345 662)(font "Arial" ))
+ (pt 360 656)
+ (pt 336 656)
+)
+(connector
+ (text "in[1]" (rect 320 664 361 678)(font "Arial" ))
+ (pt 360 664)
+ (pt 344 664)
+)
+(connector
+ (pt 720 208)
+ (pt 696 208)
+)
+(connector
+ (pt 696 208)
+ (pt 696 168)
+)
+(connector
+ (text "in[3]" (rect 592 144 633 158)(font "Arial" ))
+ (pt 616 160)
+ (pt 632 160)
+)
+(connector
+ (text "in[0]" (rect 592 176 633 190)(font "Arial" ))
+ (pt 616 176)
+ (pt 632 176)
+)
+(connector
+ (text "in[1]" (rect 584 160 625 174)(font "Arial" ))
+ (pt 632 168)
+ (pt 608 168)
+)
+(connector
+ (text "in[1]" (rect 576 312 617 326)(font "Arial" ))
+ (pt 632 312)
+ (pt 600 312)
+)
+(connector
+ (text "in[3]" (rect 584 632 625 646)(font "Arial" ))
+ (pt 632 640)
+ (pt 616 640)
+)
+(connector
+ (pt 104 376)
+ (pt 144 376)
+)
+(connector
+ (pt 104 480)
+ (pt 128 480)
+)
+(connector
+ (pt 144 384)
+ (pt 128 384)
+)
+(connector
+ (pt 128 384)
+ (pt 128 480)
+)
+(connector
+ (pt 144 368)
+ (pt 104 368)
+)
+(connector
+ (pt 104 368)
+ (pt 104 304)
+)
+(connector
+ (text "nin[3]" (rect -27 280 22 294)(font "Arial" ))
+ (pt 0 296)
+ (pt 40 296)
+)
+(connector
+ (text "nin[2]" (rect -40 296 9 310)(font "Arial" ))
+ (pt 40 304)
+ (pt -8 304)
+)
+(connector
+ (pt 40 312)
+ (pt 32 312)
+)
+(connector
+ (pt 32 312)
+ (pt 32 320)
+)
+(connector
+ (text "nin[1]" (rect -40 312 9 326)(font "Arial" ))
+ (pt 32 320)
+ (pt -8 320)
+)
+(connector
+ (pt -8 344)
+ (pt 16 344)
+)
+(connector
+ (pt 16 344)
+ (pt 16 352)
+)
+(connector
+ (text "nin[3]" (rect -40 336 9 350)(font "Arial" ))
+ (pt 16 352)
+ (pt 40 352)
+)
+(connector
+ (text "in[2]" (rect -32 360 9 374)(font "Arial" ))
+ (pt -8 368)
+ (pt 40 368)
+)
+(connector
+ (text "in[1]" (rect -40 376 1 390)(font "Arial" ))
+ (pt -8 384)
+ (pt 40 384)
+)
+(connector
+ (text "in[0]" (rect -40 392 1 406)(font "Arial" ))
+ (pt -8 400)
+ (pt 40 400)
+)
+(connector
+ (text "in[3]" (rect 0 440 41 454)(font "Arial" ))
+ (pt -8 456)
+ (pt 40 456)
+)
+(connector
+ (text "in[2]" (rect 0 456 41 470)(font "Arial" ))
+ (pt -8 472)
+ (pt 40 472)
+)
+(connector
+ (text "nin[1]" (rect 0 472 49 486)(font "Arial" ))
+ (pt -8 488)
+ (pt 40 488)
+)
+(connector
+ (text "nin[0]" (rect 0 488 49 502)(font "Arial" ))
+ (pt -8 504)
+ (pt 40 504)
+)
+(connector
+ (text "out[6]" (rect 216 360 265 374)(font "Arial" ))
+ (pt 248 376)
+ (pt 208 376)
+)
+(connector
+ (pt 608 736)
+ (pt 584 736)
+ (bus)
+)
+(connector
+ (pt 384 168)
+ (pt 448 168)
+)
+(connector
+ (text "in[0]" (rect 280 232 321 246)(font "Arial" ))
+ (pt 320 232)
+ (pt 296 232)
+)
+(connector
+ (text "nin[1]" (rect 280 216 329 230)(font "Arial" ))
+ (pt 320 224)
+ (pt 296 224)
+)
+(connector
+ (text "nin[2]" (rect 280 200 329 214)(font "Arial" ))
+ (pt 320 216)
+ (pt 296 216)
+)
+(connector
+ (text "nin[1]" (rect 268 152 317 166)(font "Arial" ))
+ (pt 320 176)
+ (pt 296 176)
+)
+(connector
+ (text "in[2]" (rect 272 168 313 182)(font "Arial" ))
+ (pt 320 168)
+ (pt 296 168)
+)
+(connector
+ (text "nin[3]" (rect 288 144 337 158)(font "Arial" ))
+ (pt 320 160)
+ (pt 296 160)
+)
+(connector
+ (text "in[0]" (rect 288 112 329 126)(font "Arial" ))
+ (pt 320 120)
+ (pt 296 120)
+)
+(connector
+ (text "nin[3]" (rect 296 80 345 94)(font "Arial" ))
+ (pt 320 104)
+ (pt 296 104)
+)
+(connector
+ (text "out[4]" (rect 520 152 569 166)(font "Arial" ))
+ (pt 512 168)
+ (pt 552 168)
+)
+(connector
+ (pt 384 224)
+ (pt 416 224)
+)
+(connector
+ (pt 448 176)
+ (pt 416 176)
+)
+(connector
+ (pt 416 176)
+ (pt 416 224)
+)
+(connector
+ (pt 384 112)
+ (pt 416 112)
+)
+(connector
+ (pt 448 160)
+ (pt 416 160)
+)
+(connector
+ (pt 416 160)
+ (pt 416 112)
+)
+(junction (pt 104 88))
+(junction (pt 120 88))
+(junction (pt 72 88))
diff --git a/part_1/ex1/BDF_Files/ex1.bdf b/part_1/ex1/BDF_Files/ex1.bdf new file mode 100644 index 0000000..21cfdb1 --- /dev/null +++ b/part_1/ex1/BDF_Files/ex1.bdf @@ -0,0 +1,86 @@ +/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+ (input)
+ (rect 584 248 752 264)
+ (text "INPUT" (rect 125 0 166 11)(font "Arial" (font_size 6)))
+ (text "SW[3..0]" (rect 5 0 72 14)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 84 12)(pt 109 12))
+ (line (pt 84 4)(pt 109 4))
+ (line (pt 113 8)(pt 168 8))
+ (line (pt 84 12)(pt 84 4))
+ (line (pt 109 4)(pt 113 8))
+ (line (pt 109 12)(pt 113 8))
+ )
+ (text "VCC" (rect 128 7 152 18)(font "Arial" (font_size 6)))
+)
+(pin
+ (output)
+ (rect 1144 248 1322 264)
+ (text "OUTPUT" (rect 1 0 50 11)(font "Arial" (font_size 6)))
+ (text "HEX0[6..0]" (rect 90 0 172 14)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8))
+ (line (pt 52 4)(pt 78 4))
+ (line (pt 52 12)(pt 78 12))
+ (line (pt 52 12)(pt 52 4))
+ (line (pt 78 4)(pt 82 8))
+ (line (pt 82 8)(pt 78 12))
+ (line (pt 78 12)(pt 82 8))
+ )
+)
+(symbol
+ (rect 840 224 1056 320)
+ (text "My7seg" (rect 5 0 61 16)(font "Arial" (font_size 8)))
+ (text "inst" (rect 8 78 41 92)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "in[3..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
+ (text "in[3..0]" (rect 21 27 96 43)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 216 32)
+ (output)
+ (text "out[6..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
+ (text "out[6..0]" (rect 111 27 195 43)(font "Arial" (font_size 8)))
+ (line (pt 216 32)(pt 200 32)(line_width 3))
+ )
+ (drawing
+ (rectangle (rect 16 16 200 80))
+ )
+)
+(connector
+ (pt 752 256)
+ (pt 840 256)
+ (bus)
+)
+(connector
+ (pt 1056 256)
+ (pt 1144 256)
+ (bus)
+)
diff --git a/part_1/ex1/Chain1.cdf b/part_1/ex1/Chain1.cdf new file mode 100644 index 0000000..acb1f32 --- /dev/null +++ b/part_1/ex1/Chain1.cdf @@ -0,0 +1,15 @@ +/* Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition */
+JedecChain;
+ FileRevision(JESD32A);
+ DefaultMfr(6E);
+
+ P ActionCode(Ign)
+ Device PartName(5CSEMA5) MfrSpec(OpMask(0));
+ P ActionCode(Cfg)
+ Device PartName(5CSEMA5F31) Path("H:/VERI/part_1/ex1/") File("ex1sol.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+ ChainType(JTAG);
+AlteraEnd;
diff --git a/part_1/ex1/Chain2.cdf b/part_1/ex1/Chain2.cdf new file mode 100644 index 0000000..590eb03 --- /dev/null +++ b/part_1/ex1/Chain2.cdf @@ -0,0 +1,15 @@ +/* Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition */
+JedecChain;
+ FileRevision(JESD32A);
+ DefaultMfr(6E);
+
+ P ActionCode(Ign)
+ Device PartName(5CSEMA5F31) MfrSpec(OpMask(0) FullPath("H:/VERI/part_1/ex1/ex1sol.sof"));
+ P ActionCode(Cfg)
+ Device PartName(5CSEMA5F31) Path("H:/VERI/part_1/ex1/") File("ex1sol.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+ ChainType(JTAG);
+AlteraEnd;
diff --git a/part_1/ex1/Symbol_Files/My7seg.bsf b/part_1/ex1/Symbol_Files/My7seg.bsf new file mode 100644 index 0000000..c348e85 --- /dev/null +++ b/part_1/ex1/Symbol_Files/My7seg.bsf @@ -0,0 +1,44 @@ +/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+ (rect 16 16 232 112)
+ (text "My7seg" (rect 5 0 61 16)(font "Arial" (font_size 8)))
+ (text "inst" (rect 8 78 41 92)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "in[3..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
+ (text "in[3..0]" (rect 21 27 96 43)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 216 32)
+ (output)
+ (text "out[6..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
+ (text "out[6..0]" (rect 111 27 195 43)(font "Arial" (font_size 8)))
+ (line (pt 216 32)(pt 200 32)(line_width 3))
+ )
+ (drawing
+ (rectangle (rect 16 16 200 80))
+ )
+)
diff --git a/part_1/ex1/c5_pin_model_dump.txt b/part_1/ex1/c5_pin_model_dump.txt new file mode 100644 index 0000000..a895a64 --- /dev/null +++ b/part_1/ex1/c5_pin_model_dump.txt @@ -0,0 +1,118 @@ +io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_1/ex1/db/_cmp.kpt b/part_1/ex1/db/_cmp.kpt Binary files differnew file mode 100644 index 0000000..454d272 --- /dev/null +++ b/part_1/ex1/db/_cmp.kpt diff --git a/part_1/ex1/db/ex1.(0).cnf.cdb b/part_1/ex1/db/ex1.(0).cnf.cdb Binary files differnew file mode 100644 index 0000000..e600a11 --- /dev/null +++ b/part_1/ex1/db/ex1.(0).cnf.cdb diff --git a/part_1/ex1/db/ex1.(0).cnf.hdb b/part_1/ex1/db/ex1.(0).cnf.hdb Binary files differnew file mode 100644 index 0000000..7d57a69 --- /dev/null +++ b/part_1/ex1/db/ex1.(0).cnf.hdb diff --git a/part_1/ex1/db/ex1.(1).cnf.cdb b/part_1/ex1/db/ex1.(1).cnf.cdb Binary files differnew file mode 100644 index 0000000..c0402be --- /dev/null +++ b/part_1/ex1/db/ex1.(1).cnf.cdb diff --git a/part_1/ex1/db/ex1.(1).cnf.hdb b/part_1/ex1/db/ex1.(1).cnf.hdb Binary files differnew file mode 100644 index 0000000..b579b27 --- /dev/null +++ b/part_1/ex1/db/ex1.(1).cnf.hdb diff --git a/part_1/ex1/db/ex1.ae.hdb b/part_1/ex1/db/ex1.ae.hdb Binary files differnew file mode 100644 index 0000000..e1dfcb9 --- /dev/null +++ b/part_1/ex1/db/ex1.ae.hdb diff --git a/part_1/ex1/db/ex1.asm.qmsg b/part_1/ex1/db/ex1.asm.qmsg new file mode 100644 index 0000000..48b3c3e --- /dev/null +++ b/part_1/ex1/db/ex1.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479203384105 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479203384108 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 09:49:43 2016 " "Processing started: Tue Nov 15 09:49:43 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479203384108 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479203384108 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex1 -c ex1 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex1 -c ex1" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479203384108 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479203384923 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479203389932 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "892 " "Peak virtual memory: 892 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479203393520 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 09:49:53 2016 " "Processing ended: Tue Nov 15 09:49:53 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479203393520 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479203393520 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479203393520 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479203393520 ""}
diff --git a/part_1/ex1/db/ex1.asm.rdb b/part_1/ex1/db/ex1.asm.rdb Binary files differnew file mode 100644 index 0000000..b6146dc --- /dev/null +++ b/part_1/ex1/db/ex1.asm.rdb diff --git a/part_1/ex1/db/ex1.cbx.xml b/part_1/ex1/db/ex1.cbx.xml new file mode 100644 index 0000000..4417b7d --- /dev/null +++ b/part_1/ex1/db/ex1.cbx.xml @@ -0,0 +1,5 @@ +<?xml version="1.0" ?>
+<LOG_ROOT>
+ <PROJECT NAME="ex1">
+ </PROJECT>
+</LOG_ROOT>
diff --git a/part_1/ex1/db/ex1.cmp.ammdb b/part_1/ex1/db/ex1.cmp.ammdb Binary files differnew file mode 100644 index 0000000..114cc7c --- /dev/null +++ b/part_1/ex1/db/ex1.cmp.ammdb diff --git a/part_1/ex1/db/ex1.cmp.bpm b/part_1/ex1/db/ex1.cmp.bpm Binary files differnew file mode 100644 index 0000000..5af97fb --- /dev/null +++ b/part_1/ex1/db/ex1.cmp.bpm diff --git a/part_1/ex1/db/ex1.cmp.cdb b/part_1/ex1/db/ex1.cmp.cdb Binary files differnew file mode 100644 index 0000000..f8d2ef7 --- /dev/null +++ b/part_1/ex1/db/ex1.cmp.cdb diff --git a/part_1/ex1/db/ex1.cmp.hdb b/part_1/ex1/db/ex1.cmp.hdb Binary files differnew file mode 100644 index 0000000..9939091 --- /dev/null +++ b/part_1/ex1/db/ex1.cmp.hdb diff --git a/part_1/ex1/db/ex1.cmp.idb b/part_1/ex1/db/ex1.cmp.idb Binary files differnew file mode 100644 index 0000000..174bc1b --- /dev/null +++ b/part_1/ex1/db/ex1.cmp.idb diff --git a/part_1/ex1/db/ex1.cmp.logdb b/part_1/ex1/db/ex1.cmp.logdb new file mode 100644 index 0000000..6387fe4 --- /dev/null +++ b/part_1/ex1/db/ex1.cmp.logdb @@ -0,0 +1,51 @@ +v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,11;0;11;0;0;11;11;0;11;11;0;7;0;0;0;0;7;0;0;0;0;7;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;11;0;11;11;0;0;11;0;0;11;4;11;11;11;11;4;11;11;11;11;4;11;11;11;11;11;11,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19,
diff --git a/part_1/ex1/db/ex1.cmp.rdb b/part_1/ex1/db/ex1.cmp.rdb Binary files differnew file mode 100644 index 0000000..c33a804 --- /dev/null +++ b/part_1/ex1/db/ex1.cmp.rdb diff --git a/part_1/ex1/db/ex1.cmp_merge.kpt b/part_1/ex1/db/ex1.cmp_merge.kpt Binary files differnew file mode 100644 index 0000000..83afb45 --- /dev/null +++ b/part_1/ex1/db/ex1.cmp_merge.kpt diff --git a/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_0c_fast.hsd Binary files differnew file mode 100644 index 0000000..5b115d6 --- /dev/null +++ b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_0c_fast.hsd diff --git a/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_85c_fast.hsd Binary files differnew file mode 100644 index 0000000..3a7a497 --- /dev/null +++ b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_85c_fast.hsd diff --git a/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_0c_slow.hsd Binary files differnew file mode 100644 index 0000000..aa473fa --- /dev/null +++ b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_0c_slow.hsd diff --git a/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_85c_slow.hsd Binary files differnew file mode 100644 index 0000000..acc52a8 --- /dev/null +++ b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_85c_slow.hsd diff --git a/part_1/ex1/db/ex1.db_info b/part_1/ex1/db/ex1.db_info new file mode 100644 index 0000000..a96dd54 --- /dev/null +++ b/part_1/ex1/db/ex1.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 15 09:24:05 2016
diff --git a/part_1/ex1/db/ex1.fit.qmsg b/part_1/ex1/db/ex1.fit.qmsg new file mode 100644 index 0000000..89644f0 --- /dev/null +++ b/part_1/ex1/db/ex1.fit.qmsg @@ -0,0 +1,43 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479203350480 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479203350482 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex1 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex1\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479203350790 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479203350854 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479203350854 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479203351272 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479203351823 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479203361959 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203361980 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479203362001 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479203362001 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479203362001 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479203362002 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479203362002 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479203362002 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479203362003 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479203362004 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479203362004 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203362018 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex1.sdc " "Synopsys Design Constraints File file not found: 'ex1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1479203367610 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1479203367611 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1479203367612 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1479203367612 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479203367613 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1479203367613 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1479203367613 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479203367618 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479203367696 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203368226 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479203368593 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479203368841 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203368841 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479203369463 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" { } { { "loc" "" { Generic "H:/VERI/part_1/ex1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479203373739 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479203373739 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479203373919 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479203373919 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479203373919 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203373922 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.07 " "Total time spent on timing analysis during the Fitter is 0.07 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479203375238 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479203375282 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479203375620 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479203375620 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479203375919 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203377837 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/VERI/part_1/ex1/output_files/ex1.fit.smsg " "Generated suppressed messages file H:/VERI/part_1/ex1/output_files/ex1.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479203378187 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2539 " "Peak virtual memory: 2539 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479203380178 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 09:49:40 2016 " "Processing ended: Tue Nov 15 09:49:40 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479203380178 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Elapsed time: 00:00:32" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479203380178 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479203380178 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479203380178 ""}
diff --git a/part_1/ex1/db/ex1.hier_info b/part_1/ex1/db/ex1.hier_info new file mode 100644 index 0000000..224e60b --- /dev/null +++ b/part_1/ex1/db/ex1.hier_info @@ -0,0 +1,73 @@ +|ex1
+HEX0[0] <= My7seg:inst.out[0]
+HEX0[1] <= My7seg:inst.out[1]
+HEX0[2] <= My7seg:inst.out[2]
+HEX0[3] <= My7seg:inst.out[3]
+HEX0[4] <= My7seg:inst.out[4]
+HEX0[5] <= My7seg:inst.out[5]
+HEX0[6] <= My7seg:inst.out[6]
+SW[0] => My7seg:inst.in[0]
+SW[1] => My7seg:inst.in[1]
+SW[2] => My7seg:inst.in[2]
+SW[3] => My7seg:inst.in[3]
+
+
+|ex1|My7seg:inst
+out[0] <= inst37.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= inst32.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= inst27.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= inst23.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= inst16.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= inst14.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= inst7.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => inst3.IN0
+in[0] => inst21.IN2
+in[0] => inst20.IN2
+in[0] => inst35.IN3
+in[0] => inst36.IN3
+in[0] => inst34.IN3
+in[0] => inst30.IN3
+in[0] => inst29.IN2
+in[0] => inst12.IN2
+in[0] => inst13.IN3
+in[0] => inst11.IN2
+in[0] => inst1.IN3
+in[0] => inst15.IN2
+in[0] => inst8.IN1
+in[1] => inst4.IN0
+in[1] => inst21.IN1
+in[1] => inst22.IN2
+in[1] => inst25.IN2
+in[1] => inst26.IN2
+in[1] => inst36.IN2
+in[1] => inst31.IN1
+in[1] => inst29.IN1
+in[1] => inst10.IN2
+in[1] => inst12.IN1
+in[1] => inst1.IN2
+in[2] => inst19.IN1
+in[2] => inst21.IN0
+in[2] => inst5.IN0
+in[2] => inst25.IN1
+in[2] => inst24.IN1
+in[2] => inst33.IN1
+in[2] => inst35.IN1
+in[2] => inst28.IN1
+in[2] => inst30.IN1
+in[2] => inst31.IN0
+in[2] => inst13.IN1
+in[2] => inst1.IN1
+in[2] => inst2.IN1
+in[2] => inst9.IN1
+in[3] => inst6.IN0
+in[3] => inst22.IN0
+in[3] => inst25.IN0
+in[3] => inst24.IN0
+in[3] => inst35.IN0
+in[3] => inst36.IN0
+in[3] => inst28.IN0
+in[3] => inst29.IN0
+in[3] => inst13.IN0
+in[3] => inst2.IN0
+
+
diff --git a/part_1/ex1/db/ex1.hif b/part_1/ex1/db/ex1.hif Binary files differnew file mode 100644 index 0000000..3eeb213 --- /dev/null +++ b/part_1/ex1/db/ex1.hif diff --git a/part_1/ex1/db/ex1.lpc.html b/part_1/ex1/db/ex1.lpc.html new file mode 100644 index 0000000..75daae6 --- /dev/null +++ b/part_1/ex1/db/ex1.lpc.html @@ -0,0 +1,34 @@ +<TABLE>
+<TR bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >inst</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_1/ex1/db/ex1.lpc.rdb b/part_1/ex1/db/ex1.lpc.rdb Binary files differnew file mode 100644 index 0000000..5008357 --- /dev/null +++ b/part_1/ex1/db/ex1.lpc.rdb diff --git a/part_1/ex1/db/ex1.lpc.txt b/part_1/ex1/db/ex1.lpc.txt new file mode 100644 index 0000000..ec1e423 --- /dev/null +++ b/part_1/ex1/db/ex1.lpc.txt @@ -0,0 +1,7 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_1/ex1/db/ex1.map.ammdb b/part_1/ex1/db/ex1.map.ammdb Binary files differnew file mode 100644 index 0000000..174eb00 --- /dev/null +++ b/part_1/ex1/db/ex1.map.ammdb diff --git a/part_1/ex1/db/ex1.map.bpm b/part_1/ex1/db/ex1.map.bpm Binary files differnew file mode 100644 index 0000000..2b712e8 --- /dev/null +++ b/part_1/ex1/db/ex1.map.bpm diff --git a/part_1/ex1/db/ex1.map.cdb b/part_1/ex1/db/ex1.map.cdb Binary files differnew file mode 100644 index 0000000..91d305e --- /dev/null +++ b/part_1/ex1/db/ex1.map.cdb diff --git a/part_1/ex1/db/ex1.map.hdb b/part_1/ex1/db/ex1.map.hdb Binary files differnew file mode 100644 index 0000000..9261c7d --- /dev/null +++ b/part_1/ex1/db/ex1.map.hdb diff --git a/part_1/ex1/db/ex1.map.kpt b/part_1/ex1/db/ex1.map.kpt Binary files differnew file mode 100644 index 0000000..d18a67e --- /dev/null +++ b/part_1/ex1/db/ex1.map.kpt diff --git a/part_1/ex1/db/ex1.map.logdb b/part_1/ex1/db/ex1.map.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex1/db/ex1.map.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex1/db/ex1.map.qmsg b/part_1/ex1/db/ex1.map.qmsg new file mode 100644 index 0000000..8d7aa08 --- /dev/null +++ b/part_1/ex1/db/ex1.map.qmsg @@ -0,0 +1,14 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479203336217 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479203336221 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 09:48:55 2016 " "Processing started: Tue Nov 15 09:48:55 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479203336221 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479203336221 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479203336221 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479203336789 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479203336790 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bdf_files/my7seg.bdf 1 1 " "Found 1 design units, including 1 entities, in source file bdf_files/my7seg.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 My7seg " "Found entity 1: My7seg" { } { { "BDF_Files/My7seg.bdf" "" { Schematic "H:/VERI/part_1/ex1/BDF_Files/My7seg.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479203345325 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479203345325 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "BDF_Files/ex1_top.bdf " "Can't analyze file -- file BDF_Files/ex1_top.bdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1479203345328 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bdf_files/ex1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file bdf_files/ex1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ex1 " "Found entity 1: ex1" { } { { "BDF_Files/ex1.bdf" "" { Schematic "H:/VERI/part_1/ex1/BDF_Files/ex1.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479203345333 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479203345333 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex1 " "Elaborating entity \"ex1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479203345387 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "My7seg My7seg:inst " "Elaborating entity \"My7seg\" for hierarchy \"My7seg:inst\"" { } { { "BDF_Files/ex1.bdf" "inst" { Schematic "H:/VERI/part_1/ex1/BDF_Files/ex1.bdf" { { 224 840 1056 320 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479203345414 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479203346281 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479203346968 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479203346968 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479203347426 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479203347426 ""} { "Info" "ICUT_CUT_TM_LCELLS" "7 " "Implemented 7 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479203347426 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479203347426 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "882 " "Peak virtual memory: 882 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479203347524 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 09:49:07 2016 " "Processing ended: Tue Nov 15 09:49:07 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479203347524 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479203347524 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479203347524 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479203347524 ""}
diff --git a/part_1/ex1/db/ex1.map.rdb b/part_1/ex1/db/ex1.map.rdb Binary files differnew file mode 100644 index 0000000..c9bff7e --- /dev/null +++ b/part_1/ex1/db/ex1.map.rdb diff --git a/part_1/ex1/db/ex1.map_bb.cdb b/part_1/ex1/db/ex1.map_bb.cdb Binary files differnew file mode 100644 index 0000000..4bbea3d --- /dev/null +++ b/part_1/ex1/db/ex1.map_bb.cdb diff --git a/part_1/ex1/db/ex1.map_bb.hdb b/part_1/ex1/db/ex1.map_bb.hdb Binary files differnew file mode 100644 index 0000000..4fbdade --- /dev/null +++ b/part_1/ex1/db/ex1.map_bb.hdb diff --git a/part_1/ex1/db/ex1.map_bb.logdb b/part_1/ex1/db/ex1.map_bb.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex1/db/ex1.map_bb.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex1/db/ex1.pplq.rdb b/part_1/ex1/db/ex1.pplq.rdb Binary files differnew file mode 100644 index 0000000..8627bdd --- /dev/null +++ b/part_1/ex1/db/ex1.pplq.rdb diff --git a/part_1/ex1/db/ex1.pre_map.cdb b/part_1/ex1/db/ex1.pre_map.cdb Binary files differnew file mode 100644 index 0000000..372b591 --- /dev/null +++ b/part_1/ex1/db/ex1.pre_map.cdb diff --git a/part_1/ex1/db/ex1.pre_map.hdb b/part_1/ex1/db/ex1.pre_map.hdb Binary files differnew file mode 100644 index 0000000..717a0a9 --- /dev/null +++ b/part_1/ex1/db/ex1.pre_map.hdb diff --git a/part_1/ex1/db/ex1.root_partition.map.reg_db.cdb b/part_1/ex1/db/ex1.root_partition.map.reg_db.cdb Binary files differnew file mode 100644 index 0000000..4fa69f7 --- /dev/null +++ b/part_1/ex1/db/ex1.root_partition.map.reg_db.cdb diff --git a/part_1/ex1/db/ex1.routing.rdb b/part_1/ex1/db/ex1.routing.rdb Binary files differnew file mode 100644 index 0000000..c469cb8 --- /dev/null +++ b/part_1/ex1/db/ex1.routing.rdb diff --git a/part_1/ex1/db/ex1.rtlv.hdb b/part_1/ex1/db/ex1.rtlv.hdb Binary files differnew file mode 100644 index 0000000..050e289 --- /dev/null +++ b/part_1/ex1/db/ex1.rtlv.hdb diff --git a/part_1/ex1/db/ex1.rtlv_sg.cdb b/part_1/ex1/db/ex1.rtlv_sg.cdb Binary files differnew file mode 100644 index 0000000..99ab5a6 --- /dev/null +++ b/part_1/ex1/db/ex1.rtlv_sg.cdb diff --git a/part_1/ex1/db/ex1.rtlv_sg_swap.cdb b/part_1/ex1/db/ex1.rtlv_sg_swap.cdb Binary files differnew file mode 100644 index 0000000..f5bfe0a --- /dev/null +++ b/part_1/ex1/db/ex1.rtlv_sg_swap.cdb diff --git a/part_1/ex1/db/ex1.sld_design_entry.sci b/part_1/ex1/db/ex1.sld_design_entry.sci Binary files differnew file mode 100644 index 0000000..92c1102 --- /dev/null +++ b/part_1/ex1/db/ex1.sld_design_entry.sci diff --git a/part_1/ex1/db/ex1.sld_design_entry_dsc.sci b/part_1/ex1/db/ex1.sld_design_entry_dsc.sci Binary files differnew file mode 100644 index 0000000..92c1102 --- /dev/null +++ b/part_1/ex1/db/ex1.sld_design_entry_dsc.sci diff --git a/part_1/ex1/db/ex1.smart_action.txt b/part_1/ex1/db/ex1.smart_action.txt new file mode 100644 index 0000000..437a63e --- /dev/null +++ b/part_1/ex1/db/ex1.smart_action.txt @@ -0,0 +1 @@ +DONE
diff --git a/part_1/ex1/db/ex1.sta.qmsg b/part_1/ex1/db/ex1.sta.qmsg new file mode 100644 index 0000000..ad0b311 --- /dev/null +++ b/part_1/ex1/db/ex1.sta.qmsg @@ -0,0 +1,61 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479203395401 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479203395405 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 09:49:54 2016 " "Processing started: Tue Nov 15 09:49:54 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479203395405 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203395405 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex1 -c ex1 " "Command: quartus_sta ex1 -c ex1" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203395406 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203395628 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396254 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396254 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396301 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396301 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex1.sdc " "Synopsys Design Constraints File file not found: 'ex1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396936 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396937 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396938 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396939 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396940 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396942 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203396945 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396989 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203397009 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397012 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397057 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397080 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397103 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397123 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397145 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203397178 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397238 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397753 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397847 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397847 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397847 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397847 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397848 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397882 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397900 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397919 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397939 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397959 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203397987 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398340 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398761 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398849 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398849 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398849 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398849 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398867 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398884 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398907 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398928 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398949 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203398975 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399311 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399311 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399311 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399313 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399329 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399347 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399365 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399386 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399403 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203401578 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203401579 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1173 " "Peak virtual memory: 1173 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479203402045 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 09:50:02 2016 " "Processing ended: Tue Nov 15 09:50:02 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479203402045 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479203402045 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479203402045 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203402045 ""}
diff --git a/part_1/ex1/db/ex1.sta.rdb b/part_1/ex1/db/ex1.sta.rdb Binary files differnew file mode 100644 index 0000000..b4f2a86 --- /dev/null +++ b/part_1/ex1/db/ex1.sta.rdb diff --git a/part_1/ex1/db/ex1.sta_cmp.6_slow_1100mv_85c.tdb b/part_1/ex1/db/ex1.sta_cmp.6_slow_1100mv_85c.tdb Binary files differnew file mode 100644 index 0000000..9b8e12b --- /dev/null +++ b/part_1/ex1/db/ex1.sta_cmp.6_slow_1100mv_85c.tdb diff --git a/part_1/ex1/db/ex1.taw.rdb b/part_1/ex1/db/ex1.taw.rdb Binary files differnew file mode 100644 index 0000000..1728c3f --- /dev/null +++ b/part_1/ex1/db/ex1.taw.rdb diff --git a/part_1/ex1/db/ex1.tis_db_list.ddb b/part_1/ex1/db/ex1.tis_db_list.ddb Binary files differnew file mode 100644 index 0000000..88225e8 --- /dev/null +++ b/part_1/ex1/db/ex1.tis_db_list.ddb diff --git a/part_1/ex1/db/ex1.tiscmp.fast_1100mv_0c.ddb b/part_1/ex1/db/ex1.tiscmp.fast_1100mv_0c.ddb Binary files differnew file mode 100644 index 0000000..bf20fad --- /dev/null +++ b/part_1/ex1/db/ex1.tiscmp.fast_1100mv_0c.ddb diff --git a/part_1/ex1/db/ex1.tiscmp.fast_1100mv_85c.ddb b/part_1/ex1/db/ex1.tiscmp.fast_1100mv_85c.ddb Binary files differnew file mode 100644 index 0000000..6e45a2b --- /dev/null +++ b/part_1/ex1/db/ex1.tiscmp.fast_1100mv_85c.ddb diff --git a/part_1/ex1/db/ex1.tiscmp.slow_1100mv_0c.ddb b/part_1/ex1/db/ex1.tiscmp.slow_1100mv_0c.ddb Binary files differnew file mode 100644 index 0000000..6231e30 --- /dev/null +++ b/part_1/ex1/db/ex1.tiscmp.slow_1100mv_0c.ddb diff --git a/part_1/ex1/db/ex1.tiscmp.slow_1100mv_85c.ddb b/part_1/ex1/db/ex1.tiscmp.slow_1100mv_85c.ddb Binary files differnew file mode 100644 index 0000000..08123f8 --- /dev/null +++ b/part_1/ex1/db/ex1.tiscmp.slow_1100mv_85c.ddb diff --git a/part_1/ex1/db/ex1.tmw_info b/part_1/ex1/db/ex1.tmw_info new file mode 100644 index 0000000..46ba178 --- /dev/null +++ b/part_1/ex1/db/ex1.tmw_info @@ -0,0 +1,3 @@ +start_analysis_synthesis:s:00:00:13-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:35-start_full_compilation
diff --git a/part_1/ex1/db/ex1.vpr.ammdb b/part_1/ex1/db/ex1.vpr.ammdb Binary files differnew file mode 100644 index 0000000..6dccbfa --- /dev/null +++ b/part_1/ex1/db/ex1.vpr.ammdb diff --git a/part_1/ex1/db/ex1_partition_pins.json b/part_1/ex1/db/ex1_partition_pins.json new file mode 100644 index 0000000..4a972c2 --- /dev/null +++ b/part_1/ex1/db/ex1_partition_pins.json @@ -0,0 +1,53 @@ +{
+ "partitions" : [
+ {
+ "name" : "Top",
+ "pins" : [
+ {
+ "name" : "HEX0[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[0]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[2]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[3]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[1]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[0]",
+ "strict" : false
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file diff --git a/part_1/ex1/db/prev_cmp_ex1.qmsg b/part_1/ex1/db/prev_cmp_ex1.qmsg new file mode 100644 index 0000000..d3fbe2f --- /dev/null +++ b/part_1/ex1/db/prev_cmp_ex1.qmsg @@ -0,0 +1,11 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479203131490 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Elaboration Quartus Prime " "Running Quartus Prime Analysis & Elaboration" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479203131493 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 09:45:31 2016 " "Processing started: Tue Nov 15 09:45:31 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479203131493 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479203131493 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1 --analysis_and_elaboration " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1 --analysis_and_elaboration" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479203131493 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479203132012 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479203132012 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bdf_files/my7seg.bdf 1 1 " "Found 1 design units, including 1 entities, in source file bdf_files/my7seg.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 My7seg " "Found entity 1: My7seg" { } { { "BDF_Files/My7seg.bdf" "" { Schematic "H:/VERI/part_1/ex1/BDF_Files/My7seg.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479203140592 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1479203140592 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "BDF_Files/ex1_top.bdf " "Can't analyze file -- file BDF_Files/ex1_top.bdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Design Software" 0 -1 1479203140595 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bdf_files/ex1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file bdf_files/ex1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ex1 " "Found entity 1: ex1" { } { { "BDF_Files/ex1.bdf" "" { Schematic "H:/VERI/part_1/ex1/BDF_Files/ex1.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479203140599 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1479203140599 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex1 " "Elaborating entity \"ex1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Design Software" 0 -1 1479203140636 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "My7seg My7seg:inst " "Elaborating entity \"My7seg\" for hierarchy \"My7seg:inst\"" { } { { "BDF_Files/ex1.bdf" "inst" { Schematic "H:/VERI/part_1/ex1/BDF_Files/ex1.bdf" { { 224 840 1056 320 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Design Software" 0 -1 1479203140689 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Elaboration 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Elaboration was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "837 " "Peak virtual memory: 837 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479203141232 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 09:45:41 2016 " "Processing ended: Tue Nov 15 09:45:41 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479203141232 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479203141232 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479203141232 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479203141232 ""}
diff --git a/part_1/ex1/ex1.qpf b/part_1/ex1/ex1.qpf new file mode 100644 index 0000000..69f0304 --- /dev/null +++ b/part_1/ex1/ex1.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 09:23:51 November 15, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.0"
+DATE = "09:23:51 November 15, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ex1"
diff --git a/part_1/ex1/ex1.qsf b/part_1/ex1/ex1.qsf new file mode 100644 index 0000000..a967e1c --- /dev/null +++ b/part_1/ex1/ex1.qsf @@ -0,0 +1,70 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 09:23:51 November 15, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# ex1_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex1
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:23:51 NOVEMBER 15, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name BDF_FILE BDF_Files/My7seg.bdf
+set_global_assignment -name BDF_FILE BDF_Files/ex1_top.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name BDF_FILE BDF_Files/ex1.bdf
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AB12 -to SW[0]
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name CDF_FILE Chain2.cdf
\ No newline at end of file diff --git a/part_1/ex1/ex1.qws b/part_1/ex1/ex1.qws Binary files differnew file mode 100644 index 0000000..ec61025 --- /dev/null +++ b/part_1/ex1/ex1.qws diff --git a/part_1/ex1/ex1sol.sof b/part_1/ex1/ex1sol.sof Binary files differnew file mode 100644 index 0000000..d3468ea --- /dev/null +++ b/part_1/ex1/ex1sol.sof diff --git a/part_1/ex1/incremental_db/README b/part_1/ex1/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/part_1/ex1/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.db_info b/part_1/ex1/incremental_db/compiled_partitions/ex1.db_info new file mode 100644 index 0000000..2a3e9d6 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 15 09:45:41 2016
diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.ammdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.ammdb Binary files differnew file mode 100644 index 0000000..114cc7c --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.ammdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.cdb Binary files differnew file mode 100644 index 0000000..d3e8b8b --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.dfp b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.dfp Binary files differnew file mode 100644 index 0000000..b1c67d6 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.dfp diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hbdb.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hbdb.cdb Binary files differnew file mode 100644 index 0000000..3d28a4b --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hbdb.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hbdb.hdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hbdb.hdb Binary files differnew file mode 100644 index 0000000..99c0223 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hbdb.hdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hbdb.sig b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hdb Binary files differnew file mode 100644 index 0000000..2849309 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.hdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.logdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.rcfdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.rcfdb Binary files differnew file mode 100644 index 0000000..a796b15 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.cmp.rcfdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.cdb Binary files differnew file mode 100644 index 0000000..7344406 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.dpi b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.dpi Binary files differnew file mode 100644 index 0000000..d9041c8 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.dpi diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.cdb Binary files differnew file mode 100644 index 0000000..4a75bdf --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.hb_info b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.hb_info Binary files differnew file mode 100644 index 0000000..8210c55 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.hb_info diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.hdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.hdb Binary files differnew file mode 100644 index 0000000..5b69841 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.hdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.sig b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hdb Binary files differnew file mode 100644 index 0000000..d07d553 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.hdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.kpt b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.kpt Binary files differnew file mode 100644 index 0000000..83835bb --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.kpt diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.olf.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.olf.cdb Binary files differnew file mode 100644 index 0000000..1e939f1 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.olf.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.olm.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.olm.cdb Binary files differnew file mode 100644 index 0000000..6631958 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.olm.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.oln.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.oln.cdb Binary files differnew file mode 100644 index 0000000..e746406 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.oln.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.opi b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.opi new file mode 100644 index 0000000..56a6051 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.opi @@ -0,0 +1 @@ +1
\ No newline at end of file diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.orf.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.orf.cdb Binary files differnew file mode 100644 index 0000000..1e939f1 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.orf.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.orm.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.orm.cdb Binary files differnew file mode 100644 index 0000000..7079e0f --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.orm.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.orn.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.orn.cdb Binary files differnew file mode 100644 index 0000000..7d06c89 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.map.orn.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.cdb Binary files differnew file mode 100644 index 0000000..7344406 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.hbdb.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.hbdb.cdb Binary files differnew file mode 100644 index 0000000..4a75bdf --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.hbdb.cdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.hbdb.hdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.hbdb.hdb Binary files differnew file mode 100644 index 0000000..5b69841 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.hbdb.hdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.hdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.hdb Binary files differnew file mode 100644 index 0000000..d07d553 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.hdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.kpt b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.kpt Binary files differnew file mode 100644 index 0000000..83835bb --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.root_partition.rrp.kpt diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.rrp.hdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.rrp.hdb Binary files differnew file mode 100644 index 0000000..b3c97c6 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.rrp.hdb diff --git a/part_1/ex1/incremental_db/compiled_partitions/ex1.rrs.cdb b/part_1/ex1/incremental_db/compiled_partitions/ex1.rrs.cdb Binary files differnew file mode 100644 index 0000000..c633497 --- /dev/null +++ b/part_1/ex1/incremental_db/compiled_partitions/ex1.rrs.cdb diff --git a/part_1/ex1/output_files/ex1.asm.rpt b/part_1/ex1/output_files/ex1.asm.rpt new file mode 100644 index 0000000..4aee34e --- /dev/null +++ b/part_1/ex1/output_files/ex1.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for ex1
+Tue Nov 15 09:49:53 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: H:/VERI/part_1/ex1/output_files/ex1.sof
+ 6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Tue Nov 15 09:49:53 2016 ;
+; Revision Name ; ex1 ;
+; Top-level Entity Name ; ex1 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++-----------------------------------------+
+; Assembler Generated Files ;
++-----------------------------------------+
+; File Name ;
++-----------------------------------------+
+; H:/VERI/part_1/ex1/output_files/ex1.sof ;
++-----------------------------------------+
+
+
++-------------------------------------------------------------------+
+; Assembler Device Options: H:/VERI/part_1/ex1/output_files/ex1.sof ;
++----------------+--------------------------------------------------+
+; Option ; Setting ;
++----------------+--------------------------------------------------+
+; Device ; 5CSEMA5F31C6 ;
+; JTAG usercode ; 0x00AF7B25 ;
+; Checksum ; 0x00AF7B25 ;
++----------------+--------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 09:49:43 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex1 -c ex1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 892 megabytes
+ Info: Processing ended: Tue Nov 15 09:49:53 2016
+ Info: Elapsed time: 00:00:10
+ Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_1/ex1/output_files/ex1.done b/part_1/ex1/output_files/ex1.done new file mode 100644 index 0000000..8acbae2 --- /dev/null +++ b/part_1/ex1/output_files/ex1.done @@ -0,0 +1 @@ +Tue Nov 15 09:50:03 2016
diff --git a/part_1/ex1/output_files/ex1.fit.rpt b/part_1/ex1/output_files/ex1.fit.rpt new file mode 100644 index 0000000..c72cc4c --- /dev/null +++ b/part_1/ex1/output_files/ex1.fit.rpt @@ -0,0 +1,1683 @@ +Fitter report for ex1
+Tue Nov 15 09:49:38 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. I/O Assignment Warnings
+ 6. Incremental Compilation Preservation Summary
+ 7. Incremental Compilation Partition Settings
+ 8. Incremental Compilation Placement Preservation
+ 9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. I/O Bank Usage
+ 15. All Package Pins
+ 16. Fitter Resource Utilization by Entity
+ 17. Delay Chain Summary
+ 18. Pad To Core Delay Chain Fanout
+ 19. Routing Usage Summary
+ 20. I/O Rules Summary
+ 21. I/O Rules Details
+ 22. I/O Rules Matrix
+ 23. Fitter Device Options
+ 24. Operating Settings and Conditions
+ 25. Fitter Messages
+ 26. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status ; Successful - Tue Nov 15 09:49:38 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex1 ;
+; Top-level Entity Name ; ex1 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 4 / 32,070 ( < 1 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 11 / 457 ( 2 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total RAM Blocks ; 0 / 397 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
+; Optimize Hold Timing ; All Paths ; All Paths ;
+; Optimize Multi-Corner Timing ; On ; On ;
+; Auto RAM to MLAB Conversion ; On ; On ;
+; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
+; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
+; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
+; SSN Optimization ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
+; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification ; Auto ; Auto ;
+; Enable Beneficial Skew Optimization ; On ; On ;
+; Optimize Design for Metastability ; On ; On ;
+; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+; Clamping Diode ; Off ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
+; Advanced Physical Optimization ; On ; On ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.2% ;
+; Processors 3-4 ; 0.0% ;
++----------------------------+-------------+
+
+
++------------------------------------------+
+; I/O Assignment Warnings ;
++----------+-------------------------------+
+; Pin Name ; Reason ;
++----------+-------------------------------+
+; HEX0[6] ; Incomplete set of assignments ;
+; HEX0[5] ; Incomplete set of assignments ;
+; HEX0[4] ; Incomplete set of assignments ;
+; HEX0[3] ; Incomplete set of assignments ;
+; HEX0[2] ; Incomplete set of assignments ;
+; HEX0[1] ; Incomplete set of assignments ;
+; HEX0[0] ; Incomplete set of assignments ;
+; SW[2] ; Incomplete set of assignments ;
+; SW[3] ; Incomplete set of assignments ;
+; SW[1] ; Incomplete set of assignments ;
+; SW[0] ; Incomplete set of assignments ;
++----------+-------------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Placement (by node) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 30 ) ; 0.00 % ( 0 / 30 ) ; 0.00 % ( 0 / 30 ) ;
+; -- Achieved ; 0.00 % ( 0 / 30 ) ; 0.00 % ( 0 / 30 ) ; 0.00 % ( 0 / 30 ) ;
+; ; ; ; ;
+; Routing (by net) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
+; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
++---------------------+-------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top ; 0.00 % ( 0 / 30 ) ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in H:/VERI/part_1/ex1/output_files/ex1.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource ; Usage ; % ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 4 / 32,070 ; < 1 % ;
+; ALMs needed [=A-B+C] ; 4 ; ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 4 / 32,070 ; < 1 % ;
+; [a] ALMs used for LUT logic and registers ; 0 ; ;
+; [b] ALMs used for LUT logic ; 4 ; ;
+; [c] ALMs used for registers ; 0 ; ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
+; [B] Estimate of ALMs recoverable by dense packing ; 0 / 32,070 ; 0 % ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ;
+; [a] Due to location constrained logic ; 0 ; ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; ;
+; [c] Due to LAB input limits ; 0 ; ;
+; [d] Due to virtual I/Os ; 0 ; ;
+; ; ; ;
+; Difficulty packing design ; Low ; ;
+; ; ; ;
+; Total LABs: partially or completely used ; 2 / 3,207 ; < 1 % ;
+; -- Logic LABs ; 2 ; ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 8 ; ;
+; -- 7 input functions ; 0 ; ;
+; -- 6 input functions ; 0 ; ;
+; -- 5 input functions ; 0 ; ;
+; -- 4 input functions ; 7 ; ;
+; -- <=3 input functions ; 1 ; ;
+; Combinational ALUT usage for route-throughs ; 0 ; ;
+; Dedicated logic registers ; 0 ; ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 0 / 64,140 ; 0 % ;
+; -- Secondary logic registers ; 0 / 64,140 ; 0 % ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 0 ; ;
+; -- Routing optimization registers ; 0 ; ;
+; ; ; ;
+; Virtual pins ; 0 ; ;
+; I/O pins ; 11 / 457 ; 2 % ;
+; -- Clock pins ; 0 / 8 ; 0 % ;
+; -- Dedicated input pins ; 0 / 21 ; 0 % ;
+; ; ; ;
+; Hard processor system peripheral utilization ; ; ;
+; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
+; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
+; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
+; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
+; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
+; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
+; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
+; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
+; -- JTAG ; 0 / 1 ( 0 % ) ; ;
+; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
+; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
+; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
+; -- STM event ; 0 / 1 ( 0 % ) ; ;
+; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
+; -- DMA ; 0 / 1 ( 0 % ) ; ;
+; -- CAN ; 0 / 2 ( 0 % ) ; ;
+; -- EMAC ; 0 / 2 ( 0 % ) ; ;
+; -- I2C ; 0 / 4 ( 0 % ) ; ;
+; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
+; -- QSPI ; 0 / 1 ( 0 % ) ; ;
+; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
+; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
+; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
+; -- UART ; 0 / 2 ( 0 % ) ; ;
+; -- USB ; 0 / 2 ( 0 % ) ; ;
+; ; ; ;
+; Global signals ; 0 ; ;
+; M10K blocks ; 0 / 397 ; 0 % ;
+; Total MLAB memory bits ; 0 ; ;
+; Total block memory bits ; 0 / 4,065,280 ; 0 % ;
+; Total block memory implementation bits ; 0 / 4,065,280 ; 0 % ;
+; ; ; ;
+; Total DSP Blocks ; 0 / 87 ; 0 % ;
+; ; ; ;
+; Fractional PLLs ; 0 / 6 ; 0 % ;
+; Global clocks ; 0 / 16 ; 0 % ;
+; Quadrant clocks ; 0 / 66 ; 0 % ;
+; Horizontal periphery clocks ; 0 / 18 ; 0 % ;
+; SERDES Transmitters ; 0 / 100 ; 0 % ;
+; SERDES Receivers ; 0 / 100 ; 0 % ;
+; JTAGs ; 0 / 1 ; 0 % ;
+; ASMI blocks ; 0 / 1 ; 0 % ;
+; CRC blocks ; 0 / 1 ; 0 % ;
+; Remote update blocks ; 0 / 1 ; 0 % ;
+; Oscillator blocks ; 0 / 1 ; 0 % ;
+; Impedance control blocks ; 0 / 4 ; 0 % ;
+; Hard Memory Controllers ; 0 / 2 ; 0 % ;
+; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ;
+; Peak interconnect usage (total/H/V) ; 0.2% / 0.1% / 0.3% ; ;
+; Maximum fan-out ; 7 ; ;
+; Highest non-global fan-out ; 7 ; ;
+; Total fan-out ; 46 ; ;
+; Average fan-out ; 1.53 ; ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+; Statistic ; Top ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 4 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; ALMs needed [=A-B+C] ; 4 ; 0 ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 4 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] ALMs used for LUT logic and registers ; 0 ; 0 ;
+; [b] ALMs used for LUT logic ; 4 ; 0 ;
+; [c] ALMs used for registers ; 0 ; 0 ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
+; [B] Estimate of ALMs recoverable by dense packing ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] Due to location constrained logic ; 0 ; 0 ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
+; [c] Due to LAB input limits ; 0 ; 0 ;
+; [d] Due to virtual I/Os ; 0 ; 0 ;
+; ; ; ;
+; Difficulty packing design ; Low ; Low ;
+; ; ; ;
+; Total LABs: partially or completely used ; 2 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ;
+; -- Logic LABs ; 2 ; 0 ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 8 ; 0 ;
+; -- 7 input functions ; 0 ; 0 ;
+; -- 6 input functions ; 0 ; 0 ;
+; -- 5 input functions ; 0 ; 0 ;
+; -- 4 input functions ; 7 ; 0 ;
+; -- <=3 input functions ; 1 ; 0 ;
+; Combinational ALUT usage for route-throughs ; 0 ; 0 ;
+; Memory ALUT usage ; 0 ; 0 ;
+; -- 64-address deep ; 0 ; 0 ;
+; -- 32-address deep ; 0 ; 0 ;
+; ; ; ;
+; Dedicated logic registers ; 0 ; 0 ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 0 / 64140 ( 0 % ) ; 0 / 64140 ( 0 % ) ;
+; -- Secondary logic registers ; 0 / 64140 ( 0 % ) ; 0 / 64140 ( 0 % ) ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 0 ; 0 ;
+; -- Routing optimization registers ; 0 ; 0 ;
+; ; ; ;
+; ; ; ;
+; Virtual pins ; 0 ; 0 ;
+; I/O pins ; 11 ; 0 ;
+; I/O registers ; 0 ; 0 ;
+; Total block memory bits ; 0 ; 0 ;
+; Total block memory implementation bits ; 0 ; 0 ;
+; ; ; ;
+; Connections ; ; ;
+; -- Input Connections ; 0 ; 0 ;
+; -- Registered Input Connections ; 0 ; 0 ;
+; -- Output Connections ; 0 ; 0 ;
+; -- Registered Output Connections ; 0 ; 0 ;
+; ; ; ;
+; Internal Connections ; ; ;
+; -- Total Connections ; 46 ; 0 ;
+; -- Registered Connections ; 0 ; 0 ;
+; ; ; ;
+; External Connections ; ; ;
+; -- Top ; 0 ; 0 ;
+; -- hard_block:auto_generated_inst ; 0 ; 0 ;
+; ; ; ;
+; Partition Interface ; ; ;
+; -- Input Ports ; 4 ; 0 ;
+; -- Output Ports ; 7 ; 0 ;
+; -- Bidir Ports ; 0 ; 0 ;
+; ; ; ;
+; Registered Ports ; ; ;
+; -- Registered Input Ports ; 0 ; 0 ;
+; -- Registered Output Ports ; 0 ; 0 ;
+; ; ; ;
+; Port Connectivity ; ; ;
+; -- Input Ports driven by GND ; 0 ; 0 ;
+; -- Output Ports driven by GND ; 0 ; 0 ;
+; -- Input Ports driven by VCC ; 0 ; 0 ;
+; -- Output Ports driven by VCC ; 0 ; 0 ;
+; -- Input Ports with no Source ; 0 ; 0 ;
+; -- Output Ports with no Source ; 0 ; 0 ;
+; -- Input Ports with no Fanout ; 0 ; 0 ;
+; -- Output Ports with no Fanout ; 0 ; 0 ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; SW[0] ; AB12 ; 3A ; 12 ; 0 ; 17 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ;
+; SW[1] ; AC12 ; 3A ; 16 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ;
+; SW[2] ; AF9 ; 3A ; 8 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ;
+; SW[3] ; AF10 ; 3A ; 4 ; 0 ; 51 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++---------------------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+-----------------+---------------+--------------+---------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+-----------------+---------------+--------------+---------------+
+; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; 3A ; 4 / 32 ( 13 % ) ; 2.5V ; -- ; 2.5V ;
+; 3B ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 5A ; 7 / 32 ( 22 % ) ; 2.5V ; -- ; 2.5V ;
+; 5B ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
++----------+-----------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
+; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
+; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA14 ; 122 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA15 ; 120 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA27 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB12 ; 72 ; 3A ; SW[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB14 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB22 ; 225 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB23 ; 227 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB24 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB25 ; 230 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB28 ; 249 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC11 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC12 ; 82 ; 3A ; SW[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC21 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AC25 ; 215 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC27 ; 242 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC28 ; 245 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC29 ; 247 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC30 ; 259 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD8 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD10 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD11 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD12 ; 80 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD25 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD26 ; 240 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD27 ; 222 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD28 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD29 ; 255 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD30 ; 257 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE11 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE12 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE15 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE25 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AE29 ; 253 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AE30 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF9 ; 67 ; 3A ; SW[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; AF10 ; 57 ; 3A ; SW[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF14 ; 114 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AF29 ; 237 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AF30 ; 239 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG4 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AG29 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AG30 ; 243 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH26 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AH29 ; 218 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AH30 ; 241 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ29 ; 216 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
+; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
+; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
+; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
+; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
+; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
+; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
+; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
+; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
+; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
+; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
+; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
+; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
+; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
+; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
+; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U23 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V16 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V18 ; 194 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V22 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V24 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W15 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W16 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W17 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W19 ; 192 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W20 ; 217 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W21 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W23 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y16 ; 128 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y19 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y21 ; 219 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; Y23 ; 232 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
+; |ex1 ; 4.0 (0.5) ; 4.0 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 11 ; 0 ; |ex1 ; ex1 ; work ;
+; |My7seg:inst| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex1|My7seg:inst ; My7seg ; work ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; SW[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++-----------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++-----------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++-----------------------------+-------------------+---------+
+; SW[2] ; ; ;
+; - My7seg:inst|inst7 ; 0 ; 0 ;
+; - My7seg:inst|inst14~0 ; 0 ; 0 ;
+; - My7seg:inst|inst16~0 ; 0 ; 0 ;
+; - My7seg:inst|inst23~0 ; 0 ; 0 ;
+; - My7seg:inst|inst27~0 ; 0 ; 0 ;
+; - My7seg:inst|inst32~0 ; 0 ; 0 ;
+; - My7seg:inst|inst37~0 ; 0 ; 0 ;
+; SW[3] ; ; ;
+; - My7seg:inst|inst7 ; 1 ; 0 ;
+; - My7seg:inst|inst14~0 ; 1 ; 0 ;
+; - My7seg:inst|inst16~0 ; 1 ; 0 ;
+; - My7seg:inst|inst23~0 ; 1 ; 0 ;
+; - My7seg:inst|inst27~0 ; 1 ; 0 ;
+; - My7seg:inst|inst32~0 ; 1 ; 0 ;
+; - My7seg:inst|inst37~0 ; 1 ; 0 ;
+; SW[1] ; ; ;
+; - My7seg:inst|inst7 ; 0 ; 0 ;
+; - My7seg:inst|inst14~0 ; 0 ; 0 ;
+; - My7seg:inst|inst16~0 ; 0 ; 0 ;
+; - My7seg:inst|inst23~0 ; 0 ; 0 ;
+; - My7seg:inst|inst27~0 ; 0 ; 0 ;
+; - My7seg:inst|inst32~0 ; 0 ; 0 ;
+; - My7seg:inst|inst37~0 ; 0 ; 0 ;
+; SW[0] ; ; ;
+; - My7seg:inst|inst7 ; 0 ; 0 ;
+; - My7seg:inst|inst14~0 ; 0 ; 0 ;
+; - My7seg:inst|inst16~0 ; 0 ; 0 ;
+; - My7seg:inst|inst23~0 ; 0 ; 0 ;
+; - My7seg:inst|inst27~0 ; 0 ; 0 ;
+; - My7seg:inst|inst32~0 ; 0 ; 0 ;
+; - My7seg:inst|inst37~0 ; 0 ; 0 ;
++-----------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------+
+; Routing Usage Summary ;
++---------------------------------------------+------------------------+
+; Routing Resource Type ; Usage ;
++---------------------------------------------+------------------------+
+; Block interconnects ; 11 / 289,320 ( < 1 % ) ;
+; C12 interconnects ; 5 / 13,420 ( < 1 % ) ;
+; C2 interconnects ; 4 / 119,108 ( < 1 % ) ;
+; C4 interconnects ; 10 / 56,300 ( < 1 % ) ;
+; DQS bus muxes ; 0 / 25 ( 0 % ) ;
+; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
+; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
+; Direct links ; 0 / 289,320 ( 0 % ) ;
+; Global clocks ; 0 / 16 ( 0 % ) ;
+; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
+; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
+; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
+; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
+; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
+; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
+; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
+; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
+; Local interconnects ; 0 / 84,580 ( 0 % ) ;
+; Quadrant clocks ; 0 / 66 ( 0 % ) ;
+; R14 interconnects ; 22 / 12,676 ( < 1 % ) ;
+; R14/C12 interconnect drivers ; 23 / 20,720 ( < 1 % ) ;
+; R3 interconnects ; 4 / 130,992 ( < 1 % ) ;
+; R6 interconnects ; 9 / 266,960 ( < 1 % ) ;
+; Spine clocks ; 0 / 360 ( 0 % ) ;
+; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
++---------------------------------------------+------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary ;
++----------------------------------+-------+
+; I/O Rules Statistic ; Total ;
++----------------------------------+-------+
+; Total I/O Rules ; 28 ;
+; Number of I/O Rules Passed ; 9 ;
+; Number of I/O Rules Failed ; 0 ;
+; Number of I/O Rules Unchecked ; 0 ;
+; Number of I/O Rules Inapplicable ; 19 ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
+; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
+; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
+; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
+; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
+; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass ; 11 ; 0 ; 11 ; 0 ; 0 ; 11 ; 11 ; 0 ; 11 ; 11 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Inapplicable ; 0 ; 11 ; 0 ; 11 ; 11 ; 0 ; 0 ; 11 ; 0 ; 0 ; 11 ; 4 ; 11 ; 11 ; 11 ; 11 ; 4 ; 11 ; 11 ; 11 ; 11 ; 4 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ;
+; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options ;
++------------------------------------------------------------------+-----------------------------+
+; Option ; Setting ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Passive Serial ;
+; Enable Error Detection CRC_ERROR pin ; Off ;
+; Enable CvP_CONFDONE pin ; Off ;
+; Enable open drain on CRC_ERROR pin ; On ;
+; Enable open drain on CvP_CONFDONE pin ; On ;
+; Enable open drain on INIT_DONE pin ; On ;
+; Enable open drain on Partial Reconfiguration pins ; Off ;
+; Enable open drain on nCEO pin ; On ;
+; Enable Partial Reconfiguration pins ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ;
+; Enable internal scrubbing ; Off ;
+; Active Serial clock source ; 100 MHz Internal Oscillator ;
+; Device initialization clock source ; Internal Oscillator ;
+; Configuration via Protocol ; Off ;
+; Configuration Voltage Level ; Auto ;
+; Force Configuration Voltage Level ; Off ;
+; Enable nCEO output ; Off ;
+; Data[15..8] ; Unreserved ;
+; Data[7..5] ; Unreserved ;
+; Base pin-out file on sameframe device ; Off ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.10 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex1"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (184020): Starting Fitter periphery placement operations
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+ Extra Info (176219): No registers were packed into other blocks
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
+Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info (170201): Optimizations that may affect the design's routability were skipped
+ Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.07 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:02
+Info (144001): Generated suppressed messages file H:/VERI/part_1/ex1/output_files/ex1.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
+ Info: Peak virtual memory: 2539 megabytes
+ Info: Processing ended: Tue Nov 15 09:49:40 2016
+ Info: Elapsed time: 00:00:32
+ Info: Total CPU time (on all processors): 00:00:48
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in H:/VERI/part_1/ex1/output_files/ex1.fit.smsg.
+
+
diff --git a/part_1/ex1/output_files/ex1.fit.smsg b/part_1/ex1/output_files/ex1.fit.smsg new file mode 100644 index 0000000..43eead5 --- /dev/null +++ b/part_1/ex1/output_files/ex1.fit.smsg @@ -0,0 +1,6 @@ +Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_1/ex1/output_files/ex1.fit.summary b/part_1/ex1/output_files/ex1.fit.summary new file mode 100644 index 0000000..47593ce --- /dev/null +++ b/part_1/ex1/output_files/ex1.fit.summary @@ -0,0 +1,20 @@ +Fitter Status : Successful - Tue Nov 15 09:49:38 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex1
+Top-level Entity Name : ex1
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 4 / 32,070 ( < 1 % )
+Total registers : 0
+Total pins : 11 / 457 ( 2 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_1/ex1/output_files/ex1.flow.rpt b/part_1/ex1/output_files/ex1.flow.rpt new file mode 100644 index 0000000..1f5a039 --- /dev/null +++ b/part_1/ex1/output_files/ex1.flow.rpt @@ -0,0 +1,128 @@ +Flow report for ex1
+Tue Nov 15 09:50:01 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+ 8. Flow Messages
+ 9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary ;
++---------------------------------+-------------------------------------------------+
+; Flow Status ; Successful - Tue Nov 15 09:49:53 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex1 ;
+; Top-level Entity Name ; ex1 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 4 / 32,070 ( < 1 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 11 / 457 ( 2 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 11/15/2016 09:48:56 ;
+; Main task ; Compilation ;
+; Revision Name ; ex1 ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 260248564170200.147920333601132 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
+; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 882 MB ; 00:00:22 ;
+; Fitter ; 00:00:30 ; 1.0 ; 2539 MB ; 00:00:47 ;
+; Assembler ; 00:00:10 ; 1.0 ; 892 MB ; 00:00:06 ;
+; TimeQuest Timing Analyzer ; 00:00:07 ; 1.0 ; 1173 MB ; 00:00:05 ;
+; Total ; 00:00:58 ; -- ; -- ; 00:01:20 ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; Fitter ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; Assembler ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; TimeQuest Timing Analyzer ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1
+quartus_fit --read_settings_files=off --write_settings_files=off ex1 -c ex1
+quartus_asm --read_settings_files=off --write_settings_files=off ex1 -c ex1
+quartus_sta ex1 -c ex1
+
+
+
diff --git a/part_1/ex1/output_files/ex1.jdi b/part_1/ex1/output_files/ex1.jdi new file mode 100644 index 0000000..1d96920 --- /dev/null +++ b/part_1/ex1/output_files/ex1.jdi @@ -0,0 +1,8 @@ +<sld_project_info>
+ <project>
+ <hash md5_digest_80b="2f95807438516708754f"/>
+ </project>
+ <file_info>
+ <file device="5CSEMA5F31C6" path="ex1.sof" usercode="0xFFFFFFFF"/>
+ </file_info>
+</sld_project_info>
diff --git a/part_1/ex1/output_files/ex1.map.rpt b/part_1/ex1/output_files/ex1.map.rpt new file mode 100644 index 0000000..ff851a0 --- /dev/null +++ b/part_1/ex1/output_files/ex1.map.rpt @@ -0,0 +1,287 @@ +Analysis & Synthesis report for ex1
+Tue Nov 15 09:49:07 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Source Files Read
+ 6. Analysis & Synthesis Resource Usage Summary
+ 7. Analysis & Synthesis Resource Utilization by Entity
+ 8. General Register Statistics
+ 9. Post-Synthesis Netlist Statistics for Top Partition
+ 10. Elapsed Time Per Partition
+ 11. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Tue Nov 15 09:49:07 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex1 ;
+; Top-level Entity Name ; ex1 ;
+; Family ; Cyclone V ;
+; Logic utilization (in ALMs) ; N/A ;
+; Total registers ; 0 ;
+; Total pins ; 11 ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 ;
+; Total DSP Blocks ; 0 ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Top-level entity name ; ex1 ; ex1 ;
+; Family name ; Cyclone V ; Cyclone V ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Infer RAMs from Raw Logic ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; On ; On ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 3 ; 3 ;
+; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
+; Synthesis Seed ; 1 ; 1 ;
+; Automatic Parallel Synthesis ; On ; On ;
+; Partial Reconfiguration Bitstream ID ; Off ; Off ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 1 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------+---------+
+; BDF_Files/My7seg.bdf ; yes ; User Block Diagram/Schematic File ; H:/VERI/part_1/ex1/BDF_Files/My7seg.bdf ; ;
+; BDF_Files/ex1.bdf ; yes ; User Block Diagram/Schematic File ; H:/VERI/part_1/ex1/BDF_Files/ex1.bdf ; ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------+---------+
+
+
++-----------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+-------------+
+; Resource ; Usage ;
++---------------------------------------------+-------------+
+; Estimate of Logic utilization (ALMs needed) ; 4 ;
+; ; ;
+; Combinational ALUT usage for logic ; 7 ;
+; -- 7 input functions ; 0 ;
+; -- 6 input functions ; 0 ;
+; -- 5 input functions ; 0 ;
+; -- 4 input functions ; 7 ;
+; -- <=3 input functions ; 0 ;
+; ; ;
+; Dedicated logic registers ; 0 ;
+; ; ;
+; I/O pins ; 11 ;
+; ; ;
+; Total DSP Blocks ; 0 ;
+; ; ;
+; Maximum fan-out node ; SW[2]~input ;
+; Maximum fan-out ; 7 ;
+; Total fan-out ; 46 ;
+; Average fan-out ; 1.59 ;
++---------------------------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
+; |ex1 ; 7 (0) ; 0 (0) ; 0 ; 0 ; 11 ; 0 ; |ex1 ; ex1 ; work ;
+; |My7seg:inst| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex1|My7seg:inst ; My7seg ; work ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 0 ;
+; Number of registers using Synchronous Clear ; 0 ;
+; Number of registers using Synchronous Load ; 0 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 0 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type ; Count ;
++-----------------------+-----------------------------+
+; arriav_lcell_comb ; 7 ;
+; normal ; 7 ;
+; 4 data inputs ; 7 ;
+; boundary_port ; 11 ;
+; ; ;
+; Max LUT depth ; 1.00 ;
+; Average LUT depth ; 1.00 ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top ; 00:00:00 ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 09:48:55 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file bdf_files/my7seg.bdf
+ Info (12023): Found entity 1: My7seg
+Warning (12019): Can't analyze file -- file BDF_Files/ex1_top.bdf is missing
+Info (12021): Found 1 design units, including 1 entities, in source file bdf_files/ex1.bdf
+ Info (12023): Found entity 1: ex1
+Info (12127): Elaborating entity "ex1" for the top level hierarchy
+Info (12128): Elaborating entity "My7seg" for hierarchy "My7seg:inst"
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+ Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 18 device resources after synthesis - the final resource count might be different
+ Info (21058): Implemented 4 input pins
+ Info (21059): Implemented 7 output pins
+ Info (21061): Implemented 7 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings
+ Info: Peak virtual memory: 882 megabytes
+ Info: Processing ended: Tue Nov 15 09:49:07 2016
+ Info: Elapsed time: 00:00:12
+ Info: Total CPU time (on all processors): 00:00:22
+
+
diff --git a/part_1/ex1/output_files/ex1.map.summary b/part_1/ex1/output_files/ex1.map.summary new file mode 100644 index 0000000..8f09a10 --- /dev/null +++ b/part_1/ex1/output_files/ex1.map.summary @@ -0,0 +1,17 @@ +Analysis & Synthesis Status : Successful - Tue Nov 15 09:49:07 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex1
+Top-level Entity Name : ex1
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 0
+Total pins : 11
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_1/ex1/output_files/ex1.pin b/part_1/ex1/output_files/ex1.pin new file mode 100644 index 0000000..8575f65 --- /dev/null +++ b/part_1/ex1/output_files/ex1.pin @@ -0,0 +1,976 @@ + -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other
+ -- applicable license agreement, including, without limitation,
+ -- that your use is for the sole purpose of programming logic
+ -- devices manufactured by Altera and sold by Altera or its
+ -- authorized distributors. Please refer to the applicable
+ -- agreement for further details.
+ --
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 3A: 2.5V
+ -- Bank 3B: 2.5V
+ -- Bank 4A: 2.5V
+ -- Bank 5A: 2.5V
+ -- Bank 5B: 2.5V
+ -- Bank 6B: 2.5V
+ -- Bank 6A: 2.5V
+ -- Bank 7A: 2.5V
+ -- Bank 7B: 2.5V
+ -- Bank 7C: 2.5V
+ -- Bank 7D: 2.5V
+ -- Bank 8A: 2.5V
+ -- RREF : External reference resistor for the quad, MUST be connected to
+ -- GND via a 2k Ohm resistor.
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
+ -- must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP "ex1" ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A :
+VCCIO8A : A7 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A :
+GND : A12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C :
+GND : A17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B :
+GND : A22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A :
+GND : A26 : : : : 7A :
+GND : A27 : gnd : : : :
+HPS_TRST : A28 : : : : 7A :
+HPS_TMS : A29 : : : : 7A :
+GND : AA1 : gnd : : : :
+GND : AA2 : gnd : : : :
+GND : AA3 : gnd : : : :
+GND : AA4 : gnd : : : :
+VCC : AA5 : power : : 1.1V : :
+GND : AA6 : gnd : : : :
+DNU : AA7 : : : : :
+VCCA_FPLL : AA8 : power : : 2.5V : :
+GND : AA9 : gnd : : : :
+VCCPD3A : AA10 : power : : 2.5V : 3A :
+GND : AA11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
+VCCIO4A : AA17 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
+GND : AA22 : gnd : : : :
+VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
+VCCIO5B : AA27 : power : : 2.5V : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 5B :
+VREFB5BN0 : AA29 : power : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B :
+GND : AB1 : gnd : : : :
+GND : AB2 : gnd : : : :
+DNU : AB3 : : : : :
+DNU : AB4 : : : : :
+GND : AB5 : gnd : : : :
+VCCA_FPLL : AB6 : power : : 2.5V : :
+GND : AB7 : gnd : : : :
+nCSO, DATA4 : AB8 : : : : 3A :
+TDO : AB9 : output : : : 3A :
+VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX : AB11 : power : : 2.5V : :
+SW[0] : AB12 : input : 2.5 V : : 3A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B :
+VCCIO3B : AB14 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B :
+VCC_AUX : AB16 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
+VCCPD3B4A : AB18 : power : : 2.5V : 3B, 4A :
+GND : AB19 : gnd : : : :
+VCCPD3B4A : AB20 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5A :
+VCCIO5A : AB24 : power : : 2.5V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28 : : : : 5B :
+GND : AB29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B :
+GND : AC1 : gnd : : : :
+GND : AC2 : gnd : : : :
+GND : AC3 : gnd : : : :
+GND : AC4 : gnd : : : :
+TCK : AC5 : input : : : 3A :
+GND : AC6 : gnd : : : :
+AS_DATA3, DATA3 : AC7 : : : : 3A :
+GND : AC8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3A :
+VCCPD3A : AC10 : power : : 2.5V : 3A :
+VCCIO3A : AC11 : power : : 2.5V : 3A :
+SW[1] : AC12 : input : 2.5 V : : 3A : Y
+VCCPD3B4A : AC13 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3B :
+VCCPD3B4A : AC15 : power : : 2.5V : 3B, 4A :
+GND : AC16 : gnd : : : :
+VCCPD3B4A : AC17 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
+VCCPD3B4A : AC19 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
+VCCIO4A : AC21 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
+VREFB5AN0 : AC24 : power : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5A :
+GND : AC26 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC28 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC29 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC30 : : : : 5B :
+GND : AD1 : gnd : : : :
+GND : AD2 : gnd : : : :
+DNU : AD3 : : : : :
+DNU : AD4 : : : : :
+GND : AD5 : gnd : : : :
+VREFB3AN0 : AD6 : power : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
+VCCIO3A : AD8 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3A :
+VCCIO3B : AD13 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B :
+DNU : AD15 : : : : :
+VCCPD3B4A : AD16 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
+VCCIO4A : AD18 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
+VCC_AUX : AD22 : power : : 2.5V : :
+GND : AD23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD27 : : : : 5A :
+VCCIO5A : AD28 : power : : 2.5V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD29 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD30 : : : : 5B :
+GND : AE1 : gnd : : : :
+GND : AE2 : gnd : : : :
+GND : AE3 : gnd : : : :
+GND : AE4 : gnd : : : :
+AS_DATA1, DATA1 : AE5 : : : : 3A :
+AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3A :
+AS_DATA2, DATA2 : AE8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3A :
+GND : AE10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B :
+VCCIO3B : AE15 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
+GND : AE20 : gnd : : : :
+VCCPD3B4A : AE21 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
+VCCIO4A : AE25 : power : : 2.5V : 4A :
+HEX0[0] : AE26 : output : 2.5 V : : 5A : Y
+HEX0[1] : AE27 : output : 2.5 V : : 5A : Y
+HEX0[2] : AE28 : output : 2.5 V : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE29 : : : : 5B :
+VCCIO5B : AE30 : power : : 2.5V : 5B :
+GND : AF1 : gnd : : : :
+GND : AF2 : gnd : : : :
+GND : AF3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A :
+VCCIO3A : AF7 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A :
+SW[2] : AF9 : input : 2.5 V : : 3A : Y
+SW[3] : AF10 : input : 2.5 V : : 3A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
+GND : AF12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
+GND : AF17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
+VCCIO4A : AF22 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A :
+GND : AF27 : gnd : : : :
+HEX0[4] : AF28 : output : 2.5 V : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF29 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF30 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A :
+VCCIO3A : AG4 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3A :
+GND : AG9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B :
+GND : AG14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
+VCCIO4A : AG19 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
+GND : AG24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
+HEX0[3] : AG27 : output : 2.5 V : : 5A : Y
+HEX0[5] : AG28 : output : 2.5 V : : 5A : Y
+VCCIO5A : AG29 : power : : 2.5V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG30 : : : : 5A :
+GND : AH1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A :
+GND : AH6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3B :
+GND : AH11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15 : : : : 3B :
+VCCIO4A : AH16 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A :
+GND : AH21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4A :
+VCCIO4A : AH26 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
+HEX0[6] : AH28 : output : 2.5 V : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH29 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH30 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2 : : : : 3A :
+GND : AJ3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B :
+VCCIO3B : AJ8 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B :
+VCCIO3B : AJ13 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B :
+VREFB3BN0 : AJ15 : power : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A :
+GND : AJ18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 4A :
+VCCIO4A : AJ23 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A :
+GND : AJ28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ29 : : : : 5A :
+GND : AJ30 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4 : : : : 3B :
+GND : AK5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B :
+VCCIO3B : AK10 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B :
+GND : AK15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A :
+VREFB4AN0 : AK17 : power : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A :
+VCCIO4A : AK20 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A :
+GND : AK25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A :
+VCCIO8A : B4 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A :
+GND : B9 : gnd : : : :
+VREFB8AN0 : B10 : power : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A :
+GND : B14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B :
+GND : B19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A :
+GND : B24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A :
+HPS_TDI : B27 : : : : 7A :
+HPS_TDO : B28 : : : : 7A :
+GND : B29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A :
+GND : C1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A :
+GND : C6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A :
+VCCIO8A : C11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D :
+GND : C16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B :
+GND : C21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A :
+GND : C26 : gnd : : : :
+HPS_nRST : C27 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A :
+GND : D3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
+VCCIO8A : D8 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
+GND : D13 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C :
+VCCIO7C_HPS : D18 : power : : 2.5V : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A :
+GND : D23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A :
+HPS_CLK1 : D25 : : : : 7A :
+GND : D26 : : : : 7A :
+HPS_RZQ_0 : D27 : : : : 6A :
+VCCIO6A_HPS : D28 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A :
+VCCIO8A : E5 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
+GND : E10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D :
+VCCIO7D_HPS : E15 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B :
+VCCIO7B_HPS : E20 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B :
+VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A :
+GND : E25 : gnd : : : :
+DNU : E26 : : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A :
+GND : E30 : gnd : : : :
+DNU : F1 : : : : :
+GND : F2 : gnd : : : :
+CONF_DONE : F3 : : : : 9A :
+nSTATUS : F4 : : : : 9A :
+GND : F5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
+GND : F7 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A :
+VCCIO8A : F12 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D :
+GND : F17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B :
+VCCIO7A_HPS : F22 : power : : 2.5V : 7A :
+HPS_nPOR : F23 : : : : 7A :
+HPS_PORSEL : F24 : : : : 7A :
+HPS_CLK2 : F25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
+GND : F27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A :
+GND : G1 : : : : :
+DNU : G2 : : : : :
+GND : G3 : gnd : : : :
+GND : G4 : gnd : : : :
+nCE : G5 : : : : 9A :
+MSEL2 : G6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8A :
+VCCIO8A : G9 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A :
+VCCIO8A : G14 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C :
+VCCIO7B_HPS : G19 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A :
+VCCRSTCLK_HPS : G23 : : : : 7A :
+GND : G24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
+VCCIO6A_HPS : G29 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A :
+GND : H1 : gnd : : : :
+GND : H2 : gnd : : : :
+DNU : H3 : : : : :
+DNU : H4 : : : : :
+GND : H5 : gnd : : : :
+VCCIO8A : H6 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
+VCCBAT : H9 : power : : 1.2V : :
+VCC_AUX : H10 : power : : 2.5V : :
+GND : H11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A :
+VCCIO7D_HPS : H16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A :
+VCCIO7A_HPS : H21 : power : : 2.5V : 7A :
+HPS_TCK : H22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
+VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A :
+GND : J1 : gnd : : : :
+GND : J2 : gnd : : : :
+GND : J3 : gnd : : : :
+GND : J4 : gnd : : : :
+nCONFIG : J5 : : : : 9A :
+GND : J6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
+GND : J8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
+VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A :
+VCCIO8A : J13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8A :
+DNU : J15 : : : : :
+VCC_AUX : J16 : power : : 2.5V : :
+VCCPD7C_HPS : J17 : power : : 2.5V : 7C :
+GND : J18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B :
+VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX_SHARED : J21 : power : : 2.5V : :
+GND : J22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
+GND : J28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A :
+GND : K1 : gnd : : : :
+GND : K2 : gnd : : : :
+DNU : K3 : : : : :
+DNU : K4 : : : : :
+GND : K5 : gnd : : : :
+MSEL1 : K6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
+VCCA_FPLL : K9 : power : : 2.5V : :
+GND : K10 : gnd : : : :
+VCCPD8A : K11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 8A :
+VCCPD8A : K13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A :
+GND : K15 : gnd : : : :
+VCCPD7D_HPS : K16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B :
+VCCPD7B_HPS : K18 : power : : 2.5V : 7B :
+VCCPD7A_HPS : K19 : power : : 2.5V : 7A :
+GND : K20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
+VCCIO6A_HPS : K24 : power : : 2.5V : 6A :
+GND : K25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A :
+VCCIO6A_HPS : K30 : power : : 2.5V : 6A :
+GND : L1 : gnd : : : :
+GND : L2 : gnd : : : :
+GND : L3 : gnd : : : :
+GND : L4 : gnd : : : :
+VCC : L5 : power : : 1.1V : :
+GND : L6 : gnd : : : :
+MSEL3 : L7 : : : : 9A :
+MSEL0 : L8 : : : : 9A :
+MSEL4 : L9 : : : : 9A :
+VCCPD8A : L10 : power : : 2.5V : 8A :
+GND : L11 : gnd : : : :
+VCCPD8A : L12 : power : : 2.5V : 8A :
+GND : L13 : gnd : : : :
+VCCPD8A : L14 : power : : 2.5V : 8A :
+GND : L15 : gnd : : : :
+VCC_HPS : L16 : power : : 1.1V : :
+GND : L17 : gnd : : : :
+VCC_HPS : L18 : power : : 1.1V : :
+GND : L19 : gnd : : : :
+VCC_HPS : L20 : power : : 1.1V : :
+VCCPLL_HPS : L21 : power : : 2.5V : :
+GND : L22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A :
+VCCIO6A_HPS : L27 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A :
+GND : M1 : gnd : : : :
+GND : M2 : gnd : : : :
+DNU : M3 : : : : :
+DNU : M4 : : : : :
+GND : M5 : gnd : : : :
+VCC : M6 : power : : 1.1V : :
+GND : M7 : gnd : : : :
+GND : M8 : gnd : : : :
+VCC : M9 : power : : 1.1V : :
+GND : M10 : gnd : : : :
+VCC : M11 : power : : 1.1V : :
+GND : M12 : gnd : : : :
+VCC : M13 : power : : 1.1V : :
+GND : M14 : gnd : : : :
+VCC_HPS : M15 : power : : 1.1V : :
+GND : M16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D :
+GND : M18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A :
+GND : M20 : gnd : : : :
+VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A :
+VCCIO6A_HPS : M24 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
+GND : M29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A :
+GND : N1 : gnd : : : :
+GND : N2 : gnd : : : :
+GND : N3 : gnd : : : :
+GND : N4 : gnd : : : :
+VCC : N5 : power : : 1.1V : :
+GND : N6 : gnd : : : :
+VCCA_FPLL : N7 : power : : 2.5V : :
+GND : N8 : gnd : : : :
+GND : N9 : gnd : : : :
+VCC : N10 : power : : 1.1V : :
+GND : N11 : gnd : : : :
+VCC : N12 : power : : 1.1V : :
+GND : N13 : gnd : : : :
+VCC : N14 : power : : 1.1V : :
+GND : N15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D :
+GND : N17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A :
+GND : N19 : gnd : : : :
+VCC_HPS : N20 : power : : 1.1V : :
+VCCIO6A_HPS : N21 : power : : 2.5V : 6A :
+VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A :
+GND : N26 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B :
+GND : P1 : gnd : : : :
+GND : P2 : gnd : : : :
+DNU : P3 : : : : :
+DNU : P4 : : : : :
+GND : P5 : gnd : : : :
+VCCA_FPLL : P6 : power : : 2.5V : :
+GND : P7 : gnd : : : :
+GND : P8 : gnd : : : :
+GND : P9 : gnd : : : :
+GND : P10 : gnd : : : :
+VCC : P11 : power : : 1.1V : :
+GND : P12 : gnd : : : :
+VCC : P13 : power : : 1.1V : :
+GND : P14 : gnd : : : :
+VCC_HPS : P15 : power : : 1.1V : :
+GND : P16 : gnd : : : :
+VCC_HPS : P17 : power : : 1.1V : :
+GND : P18 : gnd : : : :
+VCC_HPS : P19 : power : : 1.1V : :
+GND : P20 : gnd : : : :
+VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B :
+VCCIO6B_HPS : P23 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B :
+VCCIO6B_HPS : P28 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B :
+GND : R1 : gnd : : : :
+GND : R2 : gnd : : : :
+GND : R3 : gnd : : : :
+GND : R4 : gnd : : : :
+VCC : R5 : power : : 1.1V : :
+GND : R6 : gnd : : : :
+VCCA_FPLL : R7 : power : : 2.5V : :
+GND : R8 : gnd : : : :
+GND : R9 : gnd : : : :
+VCC : R10 : power : : 1.1V : :
+GND : R11 : gnd : : : :
+VCC : R12 : power : : 1.1V : :
+GND : R13 : gnd : : : :
+VCC : R14 : power : : 1.1V : :
+GND : R15 : gnd : : : :
+VCC_HPS : R16 : power : : 1.1V : :
+GND : R17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B :
+VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B :
+VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
+VCCIO6B_HPS : R25 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B :
+GND : R30 : gnd : : : :
+GND : T1 : gnd : : : :
+GND : T2 : gnd : : : :
+DNU : T3 : : : : :
+DNU : T4 : : : : :
+GND : T5 : gnd : : : :
+VCC : T6 : power : : 1.1V : :
+GND : T7 : gnd : : : :
+GND : T8 : gnd : : : :
+GND : T9 : gnd : : : :
+GND : T10 : gnd : : : :
+VCC : T11 : power : : 1.1V : :
+GND : T12 : gnd : : : :
+VCC : T13 : power : : 1.1V : :
+GND : T14 : gnd : : : :
+GND : T15 : gnd : : : :
+GND : T16 : gnd : : : :
+VCC_HPS : T17 : power : : 1.1V : :
+GND : T18 : gnd : : : :
+VCC_HPS : T19 : power : : 1.1V : :
+GND : T20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B :
+VCCIO6B_HPS : T22 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
+GND : T27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B :
+GND : U1 : gnd : : : :
+GND : U2 : gnd : : : :
+GND : U3 : gnd : : : :
+GND : U4 : gnd : : : :
+VCC : U5 : power : : 1.1V : :
+GND : U6 : gnd : : : :
+DCLK : U7 : : : : 3A :
+TDI : U8 : input : : : 3A :
+GND : U9 : gnd : : : :
+VCC : U10 : power : : 1.1V : :
+GND : U11 : gnd : : : :
+VCC : U12 : power : : 1.1V : :
+GND : U13 : gnd : : : :
+VCC : U14 : power : : 1.1V : :
+GND : U15 : gnd : : : :
+VCC_HPS : U16 : power : : 1.1V : :
+GND : U17 : gnd : : : :
+VCC_HPS : U18 : power : : 1.1V : :
+VCCIO6B_HPS : U19 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B :
+VCC : U21 : power : : 1.1V : :
+GND : U22 : gnd : : : :
+VCCPD5B : U23 : power : : 2.5V : 5B :
+GND : U24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
+GND : U29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B :
+GND : V1 : gnd : : : :
+GND : V2 : gnd : : : :
+DNU : V3 : : : : :
+DNU : V4 : : : : :
+GND : V5 : gnd : : : :
+VCCA_FPLL : V6 : power : : 2.5V : :
+GND : V7 : gnd : : : :
+VCCA_FPLL : V8 : power : : 2.5V : :
+TMS : V9 : input : : : 3A :
+GND : V10 : gnd : : : :
+VCC : V11 : power : : 1.1V : :
+GND : V12 : gnd : : : :
+VCC : V13 : power : : 1.1V : :
+GND : V14 : gnd : : : :
+VCC : V15 : power : : 1.1V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
+GND : V19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
+GND : V21 : gnd : : : :
+VCCPD5A : V22 : power : : 2.5V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5A :
+VCCPD5A : V24 : power : : 2.5V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
+VCCIO6B_HPS : V26 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B :
+GND : W1 : gnd : : : :
+GND : W2 : gnd : : : :
+GND : W3 : gnd : : : :
+GND : W4 : gnd : : : :
+VCC : W5 : power : : 1.1V : :
+GND : W6 : gnd : : : :
+GND : W7 : gnd : : : :
+GND : W8 : gnd : : : :
+GND : W9 : gnd : : : :
+VCC : W10 : power : : 1.1V : :
+GND : W11 : gnd : : : :
+VCC : W12 : power : : 1.1V : :
+GND : W13 : gnd : : : :
+VCC : W14 : power : : 1.1V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
+GND : W18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5A :
+VCCIO5A : W23 : power : : 2.5V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W24 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B :
+GND : W28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B :
+GND : Y1 : gnd : : : :
+GND : Y2 : gnd : : : :
+DNU : Y3 : : : : :
+DNU : Y4 : : : : :
+GND : Y5 : gnd : : : :
+VCC : Y6 : power : : 1.1V : :
+GND : Y7 : gnd : : : :
+GND : Y8 : gnd : : : :
+VCC : Y9 : power : : 1.1V : :
+GND : Y10 : gnd : : : :
+VCC : Y11 : power : : 1.1V : :
+GND : Y12 : gnd : : : :
+VCC : Y13 : power : : 1.1V : :
+GND : Y14 : gnd : : : :
+GND : Y15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
+GND : Y20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5A :
+VCCA_FPLL : Y22 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A :
+GND : Y25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B :
+GND : Y30 : gnd : : : :
diff --git a/part_1/ex1/output_files/ex1.sld b/part_1/ex1/output_files/ex1.sld new file mode 100644 index 0000000..41a6030 --- /dev/null +++ b/part_1/ex1/output_files/ex1.sld @@ -0,0 +1 @@ +<sld_project_info/>
diff --git a/part_1/ex1/output_files/ex1.sof b/part_1/ex1/output_files/ex1.sof Binary files differnew file mode 100644 index 0000000..c7f4077 --- /dev/null +++ b/part_1/ex1/output_files/ex1.sof diff --git a/part_1/ex1/output_files/ex1.sta.rpt b/part_1/ex1/output_files/ex1.sta.rpt new file mode 100644 index 0000000..b9ddcf3 --- /dev/null +++ b/part_1/ex1/output_files/ex1.sta.rpt @@ -0,0 +1,533 @@ +TimeQuest Timing Analyzer report for ex1
+Tue Nov 15 09:50:02 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. TimeQuest Timing Analyzer Summary
+ 3. Parallel Compilation
+ 4. Clocks
+ 5. Slow 1100mV 85C Model Fmax Summary
+ 6. Timing Closure Recommendations
+ 7. Slow 1100mV 85C Model Setup Summary
+ 8. Slow 1100mV 85C Model Hold Summary
+ 9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Clock Transfers
+ 40. Report TCCS
+ 41. Report RSKM
+ 42. Unconstrained Paths Summary
+ 43. Unconstrained Input Ports
+ 44. Unconstrained Output Ports
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer ; TimeQuest ;
+; Revision Name ; ex1 ;
+; Device Family ; Cyclone V ;
+; Device Name ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Delay Model ; Combined ;
+; Rise/Fall Delays ; Enabled ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.01 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.9% ;
+; Processors 3-4 ; 0.2% ;
++----------------------------+-------------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+---------------------------------------
+; Fast 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Fast 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
+; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------+
+; Input Transition Times ;
++-------+--------------+-----------------+-----------------+
+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------+--------------+-----------------+-----------------+
+; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
++-------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
+; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
+; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
+; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
+; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
+; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
+; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
+; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
+; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
+; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
+; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
+; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
+; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
+; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
+; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
+; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
+; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
+; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
+; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
+; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary ;
++---------------------------------+-------+------+
+; Property ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks ; 0 ; 0 ;
+; Unconstrained Clocks ; 0 ; 0 ;
+; Unconstrained Input Ports ; 4 ; 4 ;
+; Unconstrained Input Port Paths ; 28 ; 28 ;
+; Unconstrained Output Ports ; 7 ; 7 ;
+; Unconstrained Output Port Paths ; 28 ; 28 ;
++---------------------------------+-------+------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 09:49:54 2016
+Info: Command: quartus_sta ex1 -c ex1
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1100mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
+ Info: Peak virtual memory: 1173 megabytes
+ Info: Processing ended: Tue Nov 15 09:50:02 2016
+ Info: Elapsed time: 00:00:08
+ Info: Total CPU time (on all processors): 00:00:05
+
+
diff --git a/part_1/ex1/output_files/ex1.sta.summary b/part_1/ex1/output_files/ex1.sta.summary new file mode 100644 index 0000000..6640100 --- /dev/null +++ b/part_1/ex1/output_files/ex1.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/part_1/ex2/c5_pin_model_dump.txt b/part_1/ex2/c5_pin_model_dump.txt new file mode 100644 index 0000000..a895a64 --- /dev/null +++ b/part_1/ex2/c5_pin_model_dump.txt @@ -0,0 +1,118 @@ +io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_1/ex2/db/_cmp.kpt b/part_1/ex2/db/_cmp.kpt Binary files differnew file mode 100644 index 0000000..8d0efe5 --- /dev/null +++ b/part_1/ex2/db/_cmp.kpt diff --git a/part_1/ex2/db/ex2.(0).cnf.cdb b/part_1/ex2/db/ex2.(0).cnf.cdb Binary files differnew file mode 100644 index 0000000..4d38dcb --- /dev/null +++ b/part_1/ex2/db/ex2.(0).cnf.cdb diff --git a/part_1/ex2/db/ex2.(0).cnf.hdb b/part_1/ex2/db/ex2.(0).cnf.hdb Binary files differnew file mode 100644 index 0000000..b7c0f0f --- /dev/null +++ b/part_1/ex2/db/ex2.(0).cnf.hdb diff --git a/part_1/ex2/db/ex2.(1).cnf.cdb b/part_1/ex2/db/ex2.(1).cnf.cdb Binary files differnew file mode 100644 index 0000000..8568158 --- /dev/null +++ b/part_1/ex2/db/ex2.(1).cnf.cdb diff --git a/part_1/ex2/db/ex2.(1).cnf.hdb b/part_1/ex2/db/ex2.(1).cnf.hdb Binary files differnew file mode 100644 index 0000000..9d7c66c --- /dev/null +++ b/part_1/ex2/db/ex2.(1).cnf.hdb diff --git a/part_1/ex2/db/ex2.ae.hdb b/part_1/ex2/db/ex2.ae.hdb Binary files differnew file mode 100644 index 0000000..46309a6 --- /dev/null +++ b/part_1/ex2/db/ex2.ae.hdb diff --git a/part_1/ex2/db/ex2.analyze_file.qmsg b/part_1/ex2/db/ex2.analyze_file.qmsg new file mode 100644 index 0000000..57383cc --- /dev/null +++ b/part_1/ex2/db/ex2.analyze_file.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479205540582 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479205540583 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 10:25:40 2016 " "Processing started: Tue Nov 15 10:25:40 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479205540583 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479205540583 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex2 -c ex2 --analyze_file=H:/VERI/part_1/ex2/ex2.v " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex2 -c ex2 --analyze_file=H:/VERI/part_1/ex2/ex2.v" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479205540584 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479205541047 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479205541047 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1 Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "830 " "Peak virtual memory: 830 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479205549426 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:25:49 2016 " "Processing ended: Tue Nov 15 10:25:49 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479205549426 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479205549426 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479205549426 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479205549426 ""}
diff --git a/part_1/ex2/db/ex2.asm.qmsg b/part_1/ex2/db/ex2.asm.qmsg new file mode 100644 index 0000000..614bb7f --- /dev/null +++ b/part_1/ex2/db/ex2.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479206322465 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479206322469 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 10:38:42 2016 " "Processing started: Tue Nov 15 10:38:42 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479206322469 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479206322469 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex2 -c ex2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex2 -c ex2" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479206322469 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479206323320 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479206328048 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479206332140 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:38:52 2016 " "Processing ended: Tue Nov 15 10:38:52 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479206332140 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479206332140 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479206332140 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479206332140 ""}
diff --git a/part_1/ex2/db/ex2.asm.rdb b/part_1/ex2/db/ex2.asm.rdb Binary files differnew file mode 100644 index 0000000..541780a --- /dev/null +++ b/part_1/ex2/db/ex2.asm.rdb diff --git a/part_1/ex2/db/ex2.cbx.xml b/part_1/ex2/db/ex2.cbx.xml new file mode 100644 index 0000000..6e0a223 --- /dev/null +++ b/part_1/ex2/db/ex2.cbx.xml @@ -0,0 +1,5 @@ +<?xml version="1.0" ?>
+<LOG_ROOT>
+ <PROJECT NAME="ex2">
+ </PROJECT>
+</LOG_ROOT>
diff --git a/part_1/ex2/db/ex2.cmp.ammdb b/part_1/ex2/db/ex2.cmp.ammdb Binary files differnew file mode 100644 index 0000000..4435177 --- /dev/null +++ b/part_1/ex2/db/ex2.cmp.ammdb diff --git a/part_1/ex2/db/ex2.cmp.bpm b/part_1/ex2/db/ex2.cmp.bpm Binary files differnew file mode 100644 index 0000000..df9556e --- /dev/null +++ b/part_1/ex2/db/ex2.cmp.bpm diff --git a/part_1/ex2/db/ex2.cmp.cdb b/part_1/ex2/db/ex2.cmp.cdb Binary files differnew file mode 100644 index 0000000..6513727 --- /dev/null +++ b/part_1/ex2/db/ex2.cmp.cdb diff --git a/part_1/ex2/db/ex2.cmp.hdb b/part_1/ex2/db/ex2.cmp.hdb Binary files differnew file mode 100644 index 0000000..1e01dd6 --- /dev/null +++ b/part_1/ex2/db/ex2.cmp.hdb diff --git a/part_1/ex2/db/ex2.cmp.idb b/part_1/ex2/db/ex2.cmp.idb Binary files differnew file mode 100644 index 0000000..9271319 --- /dev/null +++ b/part_1/ex2/db/ex2.cmp.idb diff --git a/part_1/ex2/db/ex2.cmp.logdb b/part_1/ex2/db/ex2.cmp.logdb new file mode 100644 index 0000000..e19a40d --- /dev/null +++ b/part_1/ex2/db/ex2.cmp.logdb @@ -0,0 +1,50 @@ +v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,11;0;11;0;0;11;11;0;11;11;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;11;0;11;11;0;0;11;0;0;11;11;11;11;11;11;11;11;11;11;11;11;11;11;11;11;11;11,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_1/ex2/db/ex2.cmp.rdb b/part_1/ex2/db/ex2.cmp.rdb Binary files differnew file mode 100644 index 0000000..cd80642 --- /dev/null +++ b/part_1/ex2/db/ex2.cmp.rdb diff --git a/part_1/ex2/db/ex2.cmp_merge.kpt b/part_1/ex2/db/ex2.cmp_merge.kpt Binary files differnew file mode 100644 index 0000000..da43dba --- /dev/null +++ b/part_1/ex2/db/ex2.cmp_merge.kpt diff --git a/part_1/ex2/db/ex2.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_1/ex2/db/ex2.cyclonev_io_sim_cache.ff_0c_fast.hsd Binary files differnew file mode 100644 index 0000000..5b115d6 --- /dev/null +++ b/part_1/ex2/db/ex2.cyclonev_io_sim_cache.ff_0c_fast.hsd diff --git a/part_1/ex2/db/ex2.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_1/ex2/db/ex2.cyclonev_io_sim_cache.ff_85c_fast.hsd Binary files differnew file mode 100644 index 0000000..3a7a497 --- /dev/null +++ b/part_1/ex2/db/ex2.cyclonev_io_sim_cache.ff_85c_fast.hsd diff --git a/part_1/ex2/db/ex2.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_1/ex2/db/ex2.cyclonev_io_sim_cache.tt_0c_slow.hsd Binary files differnew file mode 100644 index 0000000..aa473fa --- /dev/null +++ b/part_1/ex2/db/ex2.cyclonev_io_sim_cache.tt_0c_slow.hsd diff --git a/part_1/ex2/db/ex2.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_1/ex2/db/ex2.cyclonev_io_sim_cache.tt_85c_slow.hsd Binary files differnew file mode 100644 index 0000000..dce4f6b --- /dev/null +++ b/part_1/ex2/db/ex2.cyclonev_io_sim_cache.tt_85c_slow.hsd diff --git a/part_1/ex2/db/ex2.db_info b/part_1/ex2/db/ex2.db_info new file mode 100644 index 0000000..20dcd21 --- /dev/null +++ b/part_1/ex2/db/ex2.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 15 10:05:40 2016
diff --git a/part_1/ex2/db/ex2.fit.qmsg b/part_1/ex2/db/ex2.fit.qmsg new file mode 100644 index 0000000..adf3870 --- /dev/null +++ b/part_1/ex2/db/ex2.fit.qmsg @@ -0,0 +1,45 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479206287999 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479206288001 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex2 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex2\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479206288256 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479206288315 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479206288315 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479206288716 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479206288873 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479206298961 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479206298980 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479206298982 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479206298982 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479206298982 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479206298982 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479206298983 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479206298983 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479206298983 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479206298985 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479206298985 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479206298999 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479206298999 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479206299035 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex2.sdc " "Synopsys Design Constraints File file not found: 'ex2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1479206304473 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1479206304474 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1479206304474 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1479206304475 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479206304475 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1479206304476 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1479206304477 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479206304478 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479206304536 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479206304916 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479206305261 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479206305479 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479206305479 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479206306486 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" { } { { "loc" "" { Generic "H:/VERI/part_1/ex2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479206310760 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479206310760 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479206310930 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479206310930 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479206310930 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479206310936 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.07 " "Total time spent on timing analysis during the Fitter is 0.07 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479206312568 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479206312603 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479206312919 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479206312919 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479206313243 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479206315142 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479206315365 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/VERI/part_1/ex2/output_files/ex2.fit.smsg " "Generated suppressed messages file H:/VERI/part_1/ex2/output_files/ex2.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479206315514 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 76 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 76 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2575 " "Peak virtual memory: 2575 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479206317586 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:38:37 2016 " "Processing ended: Tue Nov 15 10:38:37 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479206317586 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Elapsed time: 00:00:31" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479206317586 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479206317586 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479206317586 ""}
diff --git a/part_1/ex2/db/ex2.hier_info b/part_1/ex2/db/ex2.hier_info new file mode 100644 index 0000000..206a739 --- /dev/null +++ b/part_1/ex2/db/ex2.hier_info @@ -0,0 +1,28 @@ +|ex2
+SW[0] => SW[0].IN1
+SW[1] => SW[1].IN1
+SW[2] => SW[2].IN1
+SW[3] => SW[3].IN1
+HEX0[0] << hex_to_7seg:SEG0.port0
+HEX0[1] << hex_to_7seg:SEG0.port0
+HEX0[2] << hex_to_7seg:SEG0.port0
+HEX0[3] << hex_to_7seg:SEG0.port0
+HEX0[4] << hex_to_7seg:SEG0.port0
+HEX0[5] << hex_to_7seg:SEG0.port0
+HEX0[6] << hex_to_7seg:SEG0.port0
+
+
+|ex2|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_1/ex2/db/ex2.hif b/part_1/ex2/db/ex2.hif Binary files differnew file mode 100644 index 0000000..f4b7621 --- /dev/null +++ b/part_1/ex2/db/ex2.hif diff --git a/part_1/ex2/db/ex2.lpc.html b/part_1/ex2/db/ex2.lpc.html new file mode 100644 index 0000000..0a962f2 --- /dev/null +++ b/part_1/ex2/db/ex2.lpc.html @@ -0,0 +1,34 @@ +<TABLE>
+<TR bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_1/ex2/db/ex2.lpc.rdb b/part_1/ex2/db/ex2.lpc.rdb Binary files differnew file mode 100644 index 0000000..9ce8d10 --- /dev/null +++ b/part_1/ex2/db/ex2.lpc.rdb diff --git a/part_1/ex2/db/ex2.lpc.txt b/part_1/ex2/db/ex2.lpc.txt new file mode 100644 index 0000000..2aca00a --- /dev/null +++ b/part_1/ex2/db/ex2.lpc.txt @@ -0,0 +1,7 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG0 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_1/ex2/db/ex2.map.ammdb b/part_1/ex2/db/ex2.map.ammdb Binary files differnew file mode 100644 index 0000000..174eb00 --- /dev/null +++ b/part_1/ex2/db/ex2.map.ammdb diff --git a/part_1/ex2/db/ex2.map.bpm b/part_1/ex2/db/ex2.map.bpm Binary files differnew file mode 100644 index 0000000..692393a --- /dev/null +++ b/part_1/ex2/db/ex2.map.bpm diff --git a/part_1/ex2/db/ex2.map.cdb b/part_1/ex2/db/ex2.map.cdb Binary files differnew file mode 100644 index 0000000..e2a24e1 --- /dev/null +++ b/part_1/ex2/db/ex2.map.cdb diff --git a/part_1/ex2/db/ex2.map.hdb b/part_1/ex2/db/ex2.map.hdb Binary files differnew file mode 100644 index 0000000..3dc7315 --- /dev/null +++ b/part_1/ex2/db/ex2.map.hdb diff --git a/part_1/ex2/db/ex2.map.kpt b/part_1/ex2/db/ex2.map.kpt Binary files differnew file mode 100644 index 0000000..9a6af13 --- /dev/null +++ b/part_1/ex2/db/ex2.map.kpt diff --git a/part_1/ex2/db/ex2.map.logdb b/part_1/ex2/db/ex2.map.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex2/db/ex2.map.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex2/db/ex2.map.qmsg b/part_1/ex2/db/ex2.map.qmsg new file mode 100644 index 0000000..4f2052f --- /dev/null +++ b/part_1/ex2/db/ex2.map.qmsg @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479206274164 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479206274168 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 10:37:53 2016 " "Processing started: Tue Nov 15 10:37:53 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479206274168 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479206274168 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex2 -c ex2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex2 -c ex2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479206274168 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479206274796 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479206274796 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/VERI/part_1/ex2/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479206283266 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479206283266 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex2.v 1 1 " "Found 1 design units, including 1 entities, in source file ex2.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex2 " "Found entity 1: ex2" { } { { "ex2.v" "" { Text "H:/VERI/part_1/ex2/ex2.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479206283269 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479206283269 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex2 " "Elaborating entity \"ex2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479206283364 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "ex2.v" "SEG0" { Text "H:/VERI/part_1/ex2/ex2.v" 7 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479206283387 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479206284279 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479206285011 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479206285011 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479206285298 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479206285298 ""} { "Info" "ICUT_CUT_TM_LCELLS" "7 " "Implemented 7 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479206285298 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479206285298 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "881 " "Peak virtual memory: 881 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479206285410 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:38:05 2016 " "Processing ended: Tue Nov 15 10:38:05 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479206285410 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479206285410 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479206285410 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479206285410 ""}
diff --git a/part_1/ex2/db/ex2.map.rdb b/part_1/ex2/db/ex2.map.rdb Binary files differnew file mode 100644 index 0000000..dbc9b44 --- /dev/null +++ b/part_1/ex2/db/ex2.map.rdb diff --git a/part_1/ex2/db/ex2.map_bb.cdb b/part_1/ex2/db/ex2.map_bb.cdb Binary files differnew file mode 100644 index 0000000..e7480d0 --- /dev/null +++ b/part_1/ex2/db/ex2.map_bb.cdb diff --git a/part_1/ex2/db/ex2.map_bb.hdb b/part_1/ex2/db/ex2.map_bb.hdb Binary files differnew file mode 100644 index 0000000..5904c00 --- /dev/null +++ b/part_1/ex2/db/ex2.map_bb.hdb diff --git a/part_1/ex2/db/ex2.map_bb.logdb b/part_1/ex2/db/ex2.map_bb.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex2/db/ex2.map_bb.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex2/db/ex2.pre_map.cdb b/part_1/ex2/db/ex2.pre_map.cdb Binary files differnew file mode 100644 index 0000000..c7c060d --- /dev/null +++ b/part_1/ex2/db/ex2.pre_map.cdb diff --git a/part_1/ex2/db/ex2.pre_map.hdb b/part_1/ex2/db/ex2.pre_map.hdb Binary files differnew file mode 100644 index 0000000..a670bc3 --- /dev/null +++ b/part_1/ex2/db/ex2.pre_map.hdb diff --git a/part_1/ex2/db/ex2.root_partition.map.reg_db.cdb b/part_1/ex2/db/ex2.root_partition.map.reg_db.cdb Binary files differnew file mode 100644 index 0000000..f9c02c7 --- /dev/null +++ b/part_1/ex2/db/ex2.root_partition.map.reg_db.cdb diff --git a/part_1/ex2/db/ex2.routing.rdb b/part_1/ex2/db/ex2.routing.rdb Binary files differnew file mode 100644 index 0000000..8358cdd --- /dev/null +++ b/part_1/ex2/db/ex2.routing.rdb diff --git a/part_1/ex2/db/ex2.rtlv.hdb b/part_1/ex2/db/ex2.rtlv.hdb Binary files differnew file mode 100644 index 0000000..decb36d --- /dev/null +++ b/part_1/ex2/db/ex2.rtlv.hdb diff --git a/part_1/ex2/db/ex2.rtlv_sg.cdb b/part_1/ex2/db/ex2.rtlv_sg.cdb Binary files differnew file mode 100644 index 0000000..4dd25fb --- /dev/null +++ b/part_1/ex2/db/ex2.rtlv_sg.cdb diff --git a/part_1/ex2/db/ex2.rtlv_sg_swap.cdb b/part_1/ex2/db/ex2.rtlv_sg_swap.cdb Binary files differnew file mode 100644 index 0000000..e771dd4 --- /dev/null +++ b/part_1/ex2/db/ex2.rtlv_sg_swap.cdb diff --git a/part_1/ex2/db/ex2.sld_design_entry.sci b/part_1/ex2/db/ex2.sld_design_entry.sci Binary files differnew file mode 100644 index 0000000..92c1102 --- /dev/null +++ b/part_1/ex2/db/ex2.sld_design_entry.sci diff --git a/part_1/ex2/db/ex2.sld_design_entry_dsc.sci b/part_1/ex2/db/ex2.sld_design_entry_dsc.sci Binary files differnew file mode 100644 index 0000000..92c1102 --- /dev/null +++ b/part_1/ex2/db/ex2.sld_design_entry_dsc.sci diff --git a/part_1/ex2/db/ex2.smart_action.txt b/part_1/ex2/db/ex2.smart_action.txt new file mode 100644 index 0000000..437a63e --- /dev/null +++ b/part_1/ex2/db/ex2.smart_action.txt @@ -0,0 +1 @@ +DONE
diff --git a/part_1/ex2/db/ex2.sta.qmsg b/part_1/ex2/db/ex2.sta.qmsg new file mode 100644 index 0000000..abf1a25 --- /dev/null +++ b/part_1/ex2/db/ex2.sta.qmsg @@ -0,0 +1,61 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479206334135 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479206334137 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 10:38:53 2016 " "Processing started: Tue Nov 15 10:38:53 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479206334137 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206334137 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex2 -c ex2 " "Command: quartus_sta ex2 -c ex2" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206334137 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479206334262 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206334861 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206334861 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206334909 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206334909 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex2.sdc " "Synopsys Design Constraints File file not found: 'ex2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335593 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335593 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335594 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335595 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335596 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335599 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479206335601 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335658 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479206335682 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335684 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335725 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335743 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335766 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335789 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335811 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479206335834 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206335888 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206336583 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206336677 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206336677 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206336677 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206336677 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206336678 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206336715 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206336741 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206336765 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206336783 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206336802 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479206336823 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206337131 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206337705 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206337802 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206337802 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206337802 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206337802 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206337822 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206337844 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206337863 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206337881 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206337898 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479206337920 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206338314 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206338315 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206338315 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206338317 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206338336 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206338354 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206338375 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206338396 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206338416 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206340647 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206340648 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1203 " "Peak virtual memory: 1203 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479206340964 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:39:00 2016 " "Processing ended: Tue Nov 15 10:39:00 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479206340964 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479206340964 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479206340964 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479206340964 ""}
diff --git a/part_1/ex2/db/ex2.sta.rdb b/part_1/ex2/db/ex2.sta.rdb Binary files differnew file mode 100644 index 0000000..cfaa191 --- /dev/null +++ b/part_1/ex2/db/ex2.sta.rdb diff --git a/part_1/ex2/db/ex2.sta_cmp.6_slow_1100mv_85c.tdb b/part_1/ex2/db/ex2.sta_cmp.6_slow_1100mv_85c.tdb Binary files differnew file mode 100644 index 0000000..683d078 --- /dev/null +++ b/part_1/ex2/db/ex2.sta_cmp.6_slow_1100mv_85c.tdb diff --git a/part_1/ex2/db/ex2.tis_db_list.ddb b/part_1/ex2/db/ex2.tis_db_list.ddb Binary files differnew file mode 100644 index 0000000..88225e8 --- /dev/null +++ b/part_1/ex2/db/ex2.tis_db_list.ddb diff --git a/part_1/ex2/db/ex2.tiscmp.fast_1100mv_0c.ddb b/part_1/ex2/db/ex2.tiscmp.fast_1100mv_0c.ddb Binary files differnew file mode 100644 index 0000000..27bdb38 --- /dev/null +++ b/part_1/ex2/db/ex2.tiscmp.fast_1100mv_0c.ddb diff --git a/part_1/ex2/db/ex2.tiscmp.fast_1100mv_85c.ddb b/part_1/ex2/db/ex2.tiscmp.fast_1100mv_85c.ddb Binary files differnew file mode 100644 index 0000000..faa69bc --- /dev/null +++ b/part_1/ex2/db/ex2.tiscmp.fast_1100mv_85c.ddb diff --git a/part_1/ex2/db/ex2.tiscmp.slow_1100mv_0c.ddb b/part_1/ex2/db/ex2.tiscmp.slow_1100mv_0c.ddb Binary files differnew file mode 100644 index 0000000..d5e9f5b --- /dev/null +++ b/part_1/ex2/db/ex2.tiscmp.slow_1100mv_0c.ddb diff --git a/part_1/ex2/db/ex2.tiscmp.slow_1100mv_85c.ddb b/part_1/ex2/db/ex2.tiscmp.slow_1100mv_85c.ddb Binary files differnew file mode 100644 index 0000000..5b0b66a --- /dev/null +++ b/part_1/ex2/db/ex2.tiscmp.slow_1100mv_85c.ddb diff --git a/part_1/ex2/db/ex2.tmw_info b/part_1/ex2/db/ex2.tmw_info new file mode 100644 index 0000000..07c1634 --- /dev/null +++ b/part_1/ex2/db/ex2.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:01:10
+start_analysis_synthesis:s:00:00:14-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:35-start_full_compilation
+start_assembler:s:00:00:12-start_full_compilation
+start_timing_analyzer:s:00:00:09-start_full_compilation
diff --git a/part_1/ex2/db/ex2.vpr.ammdb b/part_1/ex2/db/ex2.vpr.ammdb Binary files differnew file mode 100644 index 0000000..647c89f --- /dev/null +++ b/part_1/ex2/db/ex2.vpr.ammdb diff --git a/part_1/ex2/db/ex2_partition_pins.json b/part_1/ex2/db/ex2_partition_pins.json new file mode 100644 index 0000000..ecd585e --- /dev/null +++ b/part_1/ex2/db/ex2_partition_pins.json @@ -0,0 +1,53 @@ +{
+ "partitions" : [
+ {
+ "name" : "Top",
+ "pins" : [
+ {
+ "name" : "HEX0[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[6]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[0]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[1]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[2]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[3]",
+ "strict" : false
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file diff --git a/part_1/ex2/db/prev_cmp_ex2.qmsg b/part_1/ex2/db/prev_cmp_ex2.qmsg new file mode 100644 index 0000000..65b52d2 --- /dev/null +++ b/part_1/ex2/db/prev_cmp_ex2.qmsg @@ -0,0 +1,10 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479206013044 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Elaboration Quartus Prime " "Running Quartus Prime Analysis & Elaboration" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479206013047 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 10:33:32 2016 " "Processing started: Tue Nov 15 10:33:32 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479206013047 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479206013047 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex2 -c ex2 --analysis_and_elaboration " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex2 -c ex2 --analysis_and_elaboration" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479206013047 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479206013606 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479206013606 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/VERI/part_1/ex2/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479206022016 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1479206022016 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex2.v 1 1 " "Found 1 design units, including 1 entities, in source file ex2.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex2 " "Found entity 1: ex2" { } { { "ex2.v" "" { Text "H:/VERI/part_1/ex2/ex2.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479206022020 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1479206022020 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex2 " "Elaborating entity \"ex2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Design Software" 0 -1 1479206022068 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "ex2.v" "SEG0" { Text "H:/VERI/part_1/ex2/ex2.v" 7 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Design Software" 0 -1 1479206022123 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Elaboration 0 s 1 Quartus Prime " "Quartus Prime Analysis & Elaboration was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "832 " "Peak virtual memory: 832 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479206022612 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:33:42 2016 " "Processing ended: Tue Nov 15 10:33:42 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479206022612 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479206022612 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479206022612 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479206022612 ""}
diff --git a/part_1/ex2/ex2.qpf b/part_1/ex2/ex2.qpf new file mode 100644 index 0000000..1f354dd --- /dev/null +++ b/part_1/ex2/ex2.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 10:05:39 November 15, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.0"
+DATE = "10:05:39 November 15, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ex2"
diff --git a/part_1/ex2/ex2.qsf b/part_1/ex2/ex2.qsf new file mode 100644 index 0000000..81dbde1 --- /dev/null +++ b/part_1/ex2/ex2.qsf @@ -0,0 +1,267 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 10:05:39 November 15, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# ex2_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+##============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex2
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:05:39 NOVEMBER 15, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name VERILOG_FILE ex2.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/part_1/ex2/ex2.qsf.bak b/part_1/ex2/ex2.qsf.bak new file mode 100644 index 0000000..fcc2918 --- /dev/null +++ b/part_1/ex2/ex2.qsf.bak @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 10:05:39 November 15, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# ex2_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex2
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:05:39 NOVEMBER 15, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name VERILOG_FILE ex2.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/part_1/ex2/ex2.qws b/part_1/ex2/ex2.qws Binary files differnew file mode 100644 index 0000000..63563b7 --- /dev/null +++ b/part_1/ex2/ex2.qws diff --git a/part_1/ex2/ex2.v b/part_1/ex2/ex2.v new file mode 100644 index 0000000..c15111c --- /dev/null +++ b/part_1/ex2/ex2.v @@ -0,0 +1,9 @@ +module ex2(SW,
+ HEX0);
+
+ input [3:0] SW;
+ output [6:0] HEX0;
+
+ hex_to_7seg SEG0(HEX0, SW);
+
+endmodule
diff --git a/part_1/ex2/ex2.v.bak b/part_1/ex2/ex2.v.bak new file mode 100644 index 0000000..24dc138 --- /dev/null +++ b/part_1/ex2/ex2.v.bak @@ -0,0 +1,10 @@ +module ex2_top(SW,
+ HEX0);
+
+ input [3:0] SW;
+ output [6:0] HEX0;
+
+ hex_to_7seg SEG0(HEX0, SW);
+
+endmodule
+
\ No newline at end of file diff --git a/part_1/ex2/extra_files/pin_assignment.txt b/part_1/ex2/extra_files/pin_assignment.txt new file mode 100644 index 0000000..04a3a75 --- /dev/null +++ b/part_1/ex2/extra_files/pin_assignment.txt @@ -0,0 +1,211 @@ +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_AF14 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# Add-on Card Interface Pins +#============================================================ +set_location_assignment PIN_AJ20 -to PWM_OUT +set_location_assignment PIN_AK21 -to DAC_LD +set_location_assignment PIN_AD20 -to DAC_CS +set_location_assignment PIN_AF20 -to DAC_SCK +set_location_assignment PIN_AF21 -to ADC_SCK +set_location_assignment PIN_AG21 -to ADC_SDI +set_location_assignment PIN_AG20 -to ADC_CS +set_location_assignment PIN_AG18 -to DAC_SDI +set_location_assignment PIN_AJ21 -to ADC_SDO +set_location_assignment PIN_Y17 -to OLED_CS +set_location_assignment PIN_Y18 -to OLED_RST +set_location_assignment PIN_AK18 -to OLED_DC +set_location_assignment PIN_AJ19 -to OLED_CLK +set_location_assignment PIN_AJ16 -to OLED_DATA + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + + +#============================================================ +# HEX0 +#============================================================ +set_location_assignment PIN_AE26 -to HEX0[0] +set_location_assignment PIN_AE27 -to HEX0[1] +set_location_assignment PIN_AE28 -to HEX0[2] +set_location_assignment PIN_AG27 -to HEX0[3] +set_location_assignment PIN_AF28 -to HEX0[4] +set_location_assignment PIN_AG28 -to HEX0[5] +set_location_assignment PIN_AH28 -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] + +#============================================================ +# HEX1 +#============================================================ +set_location_assignment PIN_AJ29 -to HEX1[0] +set_location_assignment PIN_AH29 -to HEX1[1] +set_location_assignment PIN_AH30 -to HEX1[2] +set_location_assignment PIN_AG30 -to HEX1[3] +set_location_assignment PIN_AF29 -to HEX1[4] +set_location_assignment PIN_AF30 -to HEX1[5] +set_location_assignment PIN_AD27 -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] + +#============================================================ +# HEX2 +#============================================================ +set_location_assignment PIN_AB23 -to HEX2[0] +set_location_assignment PIN_AE29 -to HEX2[1] +set_location_assignment PIN_AD29 -to HEX2[2] +set_location_assignment PIN_AC28 -to HEX2[3] +set_location_assignment PIN_AD30 -to HEX2[4] +set_location_assignment PIN_AC29 -to HEX2[5] +set_location_assignment PIN_AC30 -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] + +#============================================================ +# HEX3 +#============================================================ +set_location_assignment PIN_AD26 -to HEX3[0] +set_location_assignment PIN_AC27 -to HEX3[1] +set_location_assignment PIN_AD25 -to HEX3[2] +set_location_assignment PIN_AC25 -to HEX3[3] +set_location_assignment PIN_AB28 -to HEX3[4] +set_location_assignment PIN_AB25 -to HEX3[5] +set_location_assignment PIN_AB22 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] + +#============================================================ +# HEX4 +#============================================================ +set_location_assignment PIN_AA24 -to HEX4[0] +set_location_assignment PIN_Y23 -to HEX4[1] +set_location_assignment PIN_Y24 -to HEX4[2] +set_location_assignment PIN_W22 -to HEX4[3] +set_location_assignment PIN_W24 -to HEX4[4] +set_location_assignment PIN_V23 -to HEX4[5] +set_location_assignment PIN_W25 -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] + +#============================================================ +# HEX5 +#============================================================ +set_location_assignment PIN_V25 -to HEX5[0] +set_location_assignment PIN_AA28 -to HEX5[1] +set_location_assignment PIN_Y27 -to HEX5[2] +set_location_assignment PIN_AB27 -to HEX5[3] +set_location_assignment PIN_AB26 -to HEX5[4] +set_location_assignment PIN_AA26 -to HEX5[5] +set_location_assignment PIN_AA25 -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_AA14 -to KEY[0] +set_location_assignment PIN_AA15 -to KEY[1] +set_location_assignment PIN_W15 -to KEY[2] +set_location_assignment PIN_Y16 -to KEY[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] + +#============================================================ +# LEDR +#============================================================ +set_location_assignment PIN_V16 -to LEDR[0] +set_location_assignment PIN_W16 -to LEDR[1] +set_location_assignment PIN_V17 -to LEDR[2] +set_location_assignment PIN_V18 -to LEDR[3] +set_location_assignment PIN_W17 -to LEDR[4] +set_location_assignment PIN_W19 -to LEDR[5] +set_location_assignment PIN_Y19 -to LEDR[6] +set_location_assignment PIN_W20 -to LEDR[7] +set_location_assignment PIN_W21 -to LEDR[8] +set_location_assignment PIN_Y21 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_AB12 -to SW[0] +set_location_assignment PIN_AC12 -to SW[1] +set_location_assignment PIN_AF9 -to SW[2] +set_location_assignment PIN_AF10 -to SW[3] +set_location_assignment PIN_AD11 -to SW[4] +set_location_assignment PIN_AD12 -to SW[5] +set_location_assignment PIN_AE11 -to SW[6] +set_location_assignment PIN_AC9 -to SW[7] +set_location_assignment PIN_AD10 -to SW[8] +set_location_assignment PIN_AE12 -to SW[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] + +#============================================================ +# End of pin and io_standard assignments +#============================================================
\ No newline at end of file diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.db_info b/part_1/ex2/incremental_db/compiled_partitions/ex2.db_info new file mode 100644 index 0000000..3a9e05c --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 15 10:19:02 2016
diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.ammdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.ammdb Binary files differnew file mode 100644 index 0000000..4435177 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.ammdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.cdb Binary files differnew file mode 100644 index 0000000..08b3c17 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.dfp b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.dfp Binary files differnew file mode 100644 index 0000000..b1c67d6 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.dfp diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hbdb.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hbdb.cdb Binary files differnew file mode 100644 index 0000000..f35d5dd --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hbdb.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hbdb.hdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hbdb.hdb Binary files differnew file mode 100644 index 0000000..a762796 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hbdb.hdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hbdb.sig b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hdb Binary files differnew file mode 100644 index 0000000..b03c058 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.hdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.logdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.rcfdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.rcfdb Binary files differnew file mode 100644 index 0000000..225de98 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.cmp.rcfdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.cdb Binary files differnew file mode 100644 index 0000000..ef88aa8 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.dpi b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.dpi Binary files differnew file mode 100644 index 0000000..415246e --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.dpi diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.cdb Binary files differnew file mode 100644 index 0000000..1a16bbe --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.hb_info b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.hb_info Binary files differnew file mode 100644 index 0000000..8210c55 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.hb_info diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.hdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.hdb Binary files differnew file mode 100644 index 0000000..ccdd49c --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.hdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.sig b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hdb Binary files differnew file mode 100644 index 0000000..351e3ec --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.hdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.kpt b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.kpt Binary files differnew file mode 100644 index 0000000..b304dfc --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.kpt diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.olf.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.olf.cdb Binary files differnew file mode 100644 index 0000000..1e939f1 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.olf.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.olm.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.olm.cdb Binary files differnew file mode 100644 index 0000000..1e23a9d --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.olm.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.oln.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.oln.cdb Binary files differnew file mode 100644 index 0000000..332703c --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.oln.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.opi b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.opi new file mode 100644 index 0000000..56a6051 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.opi @@ -0,0 +1 @@ +1
\ No newline at end of file diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.orf.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.orf.cdb Binary files differnew file mode 100644 index 0000000..1e939f1 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.orf.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.orm.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.orm.cdb Binary files differnew file mode 100644 index 0000000..c63166c --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.orm.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.orn.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.orn.cdb Binary files differnew file mode 100644 index 0000000..e20ea46 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.map.orn.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.cdb Binary files differnew file mode 100644 index 0000000..ef88aa8 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.hbdb.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.hbdb.cdb Binary files differnew file mode 100644 index 0000000..1a16bbe --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.hbdb.cdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.hbdb.hdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.hbdb.hdb Binary files differnew file mode 100644 index 0000000..ccdd49c --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.hbdb.hdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.hdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.hdb Binary files differnew file mode 100644 index 0000000..351e3ec --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.hdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.kpt b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.kpt Binary files differnew file mode 100644 index 0000000..b304dfc --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.root_partition.rrp.kpt diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.rrp.hdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.rrp.hdb Binary files differnew file mode 100644 index 0000000..5857b8c --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.rrp.hdb diff --git a/part_1/ex2/incremental_db/compiled_partitions/ex2.rrs.cdb b/part_1/ex2/incremental_db/compiled_partitions/ex2.rrs.cdb Binary files differnew file mode 100644 index 0000000..d26bd30 --- /dev/null +++ b/part_1/ex2/incremental_db/compiled_partitions/ex2.rrs.cdb diff --git a/part_1/ex2/output_files/ex2.asm.rpt b/part_1/ex2/output_files/ex2.asm.rpt new file mode 100644 index 0000000..e6471a6 --- /dev/null +++ b/part_1/ex2/output_files/ex2.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for ex2
+Tue Nov 15 10:38:51 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: H:/VERI/part_1/ex2/output_files/ex2.sof
+ 6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Tue Nov 15 10:38:51 2016 ;
+; Revision Name ; ex2 ;
+; Top-level Entity Name ; ex2 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++-----------------------------------------+
+; Assembler Generated Files ;
++-----------------------------------------+
+; File Name ;
++-----------------------------------------+
+; H:/VERI/part_1/ex2/output_files/ex2.sof ;
++-----------------------------------------+
+
+
++-------------------------------------------------------------------+
+; Assembler Device Options: H:/VERI/part_1/ex2/output_files/ex2.sof ;
++----------------+--------------------------------------------------+
+; Option ; Setting ;
++----------------+--------------------------------------------------+
+; Device ; 5CSEMA5F31C6 ;
+; JTAG usercode ; 0x00AF7D85 ;
+; Checksum ; 0x00AF7D85 ;
++----------------+--------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 10:38:42 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex2 -c ex2
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 896 megabytes
+ Info: Processing ended: Tue Nov 15 10:38:52 2016
+ Info: Elapsed time: 00:00:10
+ Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_1/ex2/output_files/ex2.done b/part_1/ex2/output_files/ex2.done new file mode 100644 index 0000000..3453956 --- /dev/null +++ b/part_1/ex2/output_files/ex2.done @@ -0,0 +1 @@ +Tue Nov 15 10:39:03 2016
diff --git a/part_1/ex2/output_files/ex2.fit.rpt b/part_1/ex2/output_files/ex2.fit.rpt new file mode 100644 index 0000000..1db4f26 --- /dev/null +++ b/part_1/ex2/output_files/ex2.fit.rpt @@ -0,0 +1,1899 @@ +Fitter report for ex2
+Tue Nov 15 10:38:35 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. I/O Assignment Warnings
+ 6. Ignored Assignments
+ 7. Incremental Compilation Preservation Summary
+ 8. Incremental Compilation Partition Settings
+ 9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Routing Usage Summary
+ 21. I/O Rules Summary
+ 22. I/O Rules Details
+ 23. I/O Rules Matrix
+ 24. Fitter Device Options
+ 25. Operating Settings and Conditions
+ 26. Fitter Messages
+ 27. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status ; Successful - Tue Nov 15 10:38:35 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex2 ;
+; Top-level Entity Name ; ex2 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 4 / 32,070 ( < 1 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 11 / 457 ( 2 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total RAM Blocks ; 0 / 397 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
+; Optimize Hold Timing ; All Paths ; All Paths ;
+; Optimize Multi-Corner Timing ; On ; On ;
+; Auto RAM to MLAB Conversion ; On ; On ;
+; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
+; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
+; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
+; SSN Optimization ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
+; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification ; Auto ; Auto ;
+; Enable Beneficial Skew Optimization ; On ; On ;
+; Optimize Design for Metastability ; On ; On ;
+; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+; Clamping Diode ; Off ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
+; Advanced Physical Optimization ; On ; On ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.1% ;
+; Processors 3-4 ; 0.0% ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings ;
++----------+--------------------------------------+
+; Pin Name ; Reason ;
++----------+--------------------------------------+
+; HEX0[0] ; Missing drive strength and slew rate ;
+; HEX0[1] ; Missing drive strength and slew rate ;
+; HEX0[2] ; Missing drive strength and slew rate ;
+; HEX0[3] ; Missing drive strength and slew rate ;
+; HEX0[4] ; Missing drive strength and slew rate ;
+; HEX0[5] ; Missing drive strength and slew rate ;
+; HEX0[6] ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location ; ; ; ADC_CS ; PIN_AG20 ; QSF Assignment ;
+; Location ; ; ; ADC_SCK ; PIN_AF21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDI ; PIN_AG21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDO ; PIN_AJ21 ; QSF Assignment ;
+; Location ; ; ; CLOCK_50 ; PIN_AF14 ; QSF Assignment ;
+; Location ; ; ; DAC_CS ; PIN_AD20 ; QSF Assignment ;
+; Location ; ; ; DAC_LD ; PIN_AK21 ; QSF Assignment ;
+; Location ; ; ; DAC_SCK ; PIN_AF20 ; QSF Assignment ;
+; Location ; ; ; DAC_SDI ; PIN_AG18 ; QSF Assignment ;
+; Location ; ; ; HEX1[0] ; PIN_AJ29 ; QSF Assignment ;
+; Location ; ; ; HEX1[1] ; PIN_AH29 ; QSF Assignment ;
+; Location ; ; ; HEX1[2] ; PIN_AH30 ; QSF Assignment ;
+; Location ; ; ; HEX1[3] ; PIN_AG30 ; QSF Assignment ;
+; Location ; ; ; HEX1[4] ; PIN_AF29 ; QSF Assignment ;
+; Location ; ; ; HEX1[5] ; PIN_AF30 ; QSF Assignment ;
+; Location ; ; ; HEX1[6] ; PIN_AD27 ; QSF Assignment ;
+; Location ; ; ; HEX2[0] ; PIN_AB23 ; QSF Assignment ;
+; Location ; ; ; HEX2[1] ; PIN_AE29 ; QSF Assignment ;
+; Location ; ; ; HEX2[2] ; PIN_AD29 ; QSF Assignment ;
+; Location ; ; ; HEX2[3] ; PIN_AC28 ; QSF Assignment ;
+; Location ; ; ; HEX2[4] ; PIN_AD30 ; QSF Assignment ;
+; Location ; ; ; HEX2[5] ; PIN_AC29 ; QSF Assignment ;
+; Location ; ; ; HEX2[6] ; PIN_AC30 ; QSF Assignment ;
+; Location ; ; ; HEX3[0] ; PIN_AD26 ; QSF Assignment ;
+; Location ; ; ; HEX3[1] ; PIN_AC27 ; QSF Assignment ;
+; Location ; ; ; HEX3[2] ; PIN_AD25 ; QSF Assignment ;
+; Location ; ; ; HEX3[3] ; PIN_AC25 ; QSF Assignment ;
+; Location ; ; ; HEX3[4] ; PIN_AB28 ; QSF Assignment ;
+; Location ; ; ; HEX3[5] ; PIN_AB25 ; QSF Assignment ;
+; Location ; ; ; HEX3[6] ; PIN_AB22 ; QSF Assignment ;
+; Location ; ; ; HEX4[0] ; PIN_AA24 ; QSF Assignment ;
+; Location ; ; ; HEX4[1] ; PIN_Y23 ; QSF Assignment ;
+; Location ; ; ; HEX4[2] ; PIN_Y24 ; QSF Assignment ;
+; Location ; ; ; HEX4[3] ; PIN_W22 ; QSF Assignment ;
+; Location ; ; ; HEX4[4] ; PIN_W24 ; QSF Assignment ;
+; Location ; ; ; HEX4[5] ; PIN_V23 ; QSF Assignment ;
+; Location ; ; ; HEX4[6] ; PIN_W25 ; QSF Assignment ;
+; Location ; ; ; HEX5[0] ; PIN_V25 ; QSF Assignment ;
+; Location ; ; ; HEX5[1] ; PIN_AA28 ; QSF Assignment ;
+; Location ; ; ; HEX5[2] ; PIN_Y27 ; QSF Assignment ;
+; Location ; ; ; HEX5[3] ; PIN_AB27 ; QSF Assignment ;
+; Location ; ; ; HEX5[4] ; PIN_AB26 ; QSF Assignment ;
+; Location ; ; ; HEX5[5] ; PIN_AA26 ; QSF Assignment ;
+; Location ; ; ; HEX5[6] ; PIN_AA25 ; QSF Assignment ;
+; Location ; ; ; KEY[0] ; PIN_AA14 ; QSF Assignment ;
+; Location ; ; ; KEY[1] ; PIN_AA15 ; QSF Assignment ;
+; Location ; ; ; KEY[2] ; PIN_W15 ; QSF Assignment ;
+; Location ; ; ; KEY[3] ; PIN_Y16 ; QSF Assignment ;
+; Location ; ; ; LEDR[0] ; PIN_V16 ; QSF Assignment ;
+; Location ; ; ; LEDR[1] ; PIN_W16 ; QSF Assignment ;
+; Location ; ; ; LEDR[2] ; PIN_V17 ; QSF Assignment ;
+; Location ; ; ; LEDR[3] ; PIN_V18 ; QSF Assignment ;
+; Location ; ; ; LEDR[4] ; PIN_W17 ; QSF Assignment ;
+; Location ; ; ; LEDR[5] ; PIN_W19 ; QSF Assignment ;
+; Location ; ; ; LEDR[6] ; PIN_Y19 ; QSF Assignment ;
+; Location ; ; ; LEDR[7] ; PIN_W20 ; QSF Assignment ;
+; Location ; ; ; LEDR[8] ; PIN_W21 ; QSF Assignment ;
+; Location ; ; ; LEDR[9] ; PIN_Y21 ; QSF Assignment ;
+; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ;
+; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ;
+; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ;
+; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ;
+; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ;
+; Location ; ; ; PWM_OUT ; PIN_AJ20 ; QSF Assignment ;
+; Location ; ; ; SW[4] ; PIN_AD11 ; QSF Assignment ;
+; Location ; ; ; SW[5] ; PIN_AD12 ; QSF Assignment ;
+; Location ; ; ; SW[6] ; PIN_AE11 ; QSF Assignment ;
+; Location ; ; ; SW[7] ; PIN_AC9 ; QSF Assignment ;
+; Location ; ; ; SW[8] ; PIN_AD10 ; QSF Assignment ;
+; Location ; ; ; SW[9] ; PIN_AE12 ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; ADC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; ADC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; ADC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; ADC_SDO ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; CLOCK_50 ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; DAC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; DAC_LD ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; DAC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; DAC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX1[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX1[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX1[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX1[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX1[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX1[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX1[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX2[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX2[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX2[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX2[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX2[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX2[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX2[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX3[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX3[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX3[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX3[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX3[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX3[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX3[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX4[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX4[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX4[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX4[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX4[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX4[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX4[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; KEY[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; KEY[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; KEY[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; KEY[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; LEDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; LEDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; LEDR[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; LEDR[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; LEDR[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; LEDR[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; LEDR[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; LEDR[7] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; LEDR[8] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; LEDR[9] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; PWM_OUT ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; SW[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; SW[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; SW[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; SW[7] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; SW[8] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex2 ; ; SW[9] ; 3.3-V LVTTL ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Placement (by node) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 30 ) ; 0.00 % ( 0 / 30 ) ; 0.00 % ( 0 / 30 ) ;
+; -- Achieved ; 0.00 % ( 0 / 30 ) ; 0.00 % ( 0 / 30 ) ; 0.00 % ( 0 / 30 ) ;
+; ; ; ; ;
+; Routing (by net) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
+; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
++---------------------+-------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top ; 0.00 % ( 0 / 30 ) ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in H:/VERI/part_1/ex2/output_files/ex2.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource ; Usage ; % ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 4 / 32,070 ; < 1 % ;
+; ALMs needed [=A-B+C] ; 4 ; ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 4 / 32,070 ; < 1 % ;
+; [a] ALMs used for LUT logic and registers ; 0 ; ;
+; [b] ALMs used for LUT logic ; 4 ; ;
+; [c] ALMs used for registers ; 0 ; ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
+; [B] Estimate of ALMs recoverable by dense packing ; 0 / 32,070 ; 0 % ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ;
+; [a] Due to location constrained logic ; 0 ; ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; ;
+; [c] Due to LAB input limits ; 0 ; ;
+; [d] Due to virtual I/Os ; 0 ; ;
+; ; ; ;
+; Difficulty packing design ; Low ; ;
+; ; ; ;
+; Total LABs: partially or completely used ; 2 / 3,207 ; < 1 % ;
+; -- Logic LABs ; 2 ; ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 8 ; ;
+; -- 7 input functions ; 0 ; ;
+; -- 6 input functions ; 0 ; ;
+; -- 5 input functions ; 0 ; ;
+; -- 4 input functions ; 7 ; ;
+; -- <=3 input functions ; 1 ; ;
+; Combinational ALUT usage for route-throughs ; 0 ; ;
+; Dedicated logic registers ; 0 ; ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 0 / 64,140 ; 0 % ;
+; -- Secondary logic registers ; 0 / 64,140 ; 0 % ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 0 ; ;
+; -- Routing optimization registers ; 0 ; ;
+; ; ; ;
+; Virtual pins ; 0 ; ;
+; I/O pins ; 11 / 457 ; 2 % ;
+; -- Clock pins ; 0 / 8 ; 0 % ;
+; -- Dedicated input pins ; 0 / 21 ; 0 % ;
+; ; ; ;
+; Hard processor system peripheral utilization ; ; ;
+; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
+; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
+; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
+; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
+; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
+; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
+; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
+; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
+; -- JTAG ; 0 / 1 ( 0 % ) ; ;
+; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
+; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
+; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
+; -- STM event ; 0 / 1 ( 0 % ) ; ;
+; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
+; -- DMA ; 0 / 1 ( 0 % ) ; ;
+; -- CAN ; 0 / 2 ( 0 % ) ; ;
+; -- EMAC ; 0 / 2 ( 0 % ) ; ;
+; -- I2C ; 0 / 4 ( 0 % ) ; ;
+; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
+; -- QSPI ; 0 / 1 ( 0 % ) ; ;
+; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
+; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
+; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
+; -- UART ; 0 / 2 ( 0 % ) ; ;
+; -- USB ; 0 / 2 ( 0 % ) ; ;
+; ; ; ;
+; Global signals ; 0 ; ;
+; M10K blocks ; 0 / 397 ; 0 % ;
+; Total MLAB memory bits ; 0 ; ;
+; Total block memory bits ; 0 / 4,065,280 ; 0 % ;
+; Total block memory implementation bits ; 0 / 4,065,280 ; 0 % ;
+; ; ; ;
+; Total DSP Blocks ; 0 / 87 ; 0 % ;
+; ; ; ;
+; Fractional PLLs ; 0 / 6 ; 0 % ;
+; Global clocks ; 0 / 16 ; 0 % ;
+; Quadrant clocks ; 0 / 66 ; 0 % ;
+; Horizontal periphery clocks ; 0 / 18 ; 0 % ;
+; SERDES Transmitters ; 0 / 100 ; 0 % ;
+; SERDES Receivers ; 0 / 100 ; 0 % ;
+; JTAGs ; 0 / 1 ; 0 % ;
+; ASMI blocks ; 0 / 1 ; 0 % ;
+; CRC blocks ; 0 / 1 ; 0 % ;
+; Remote update blocks ; 0 / 1 ; 0 % ;
+; Oscillator blocks ; 0 / 1 ; 0 % ;
+; Impedance control blocks ; 0 / 4 ; 0 % ;
+; Hard Memory Controllers ; 0 / 2 ; 0 % ;
+; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ;
+; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.2% ; ;
+; Maximum fan-out ; 7 ; ;
+; Highest non-global fan-out ; 7 ; ;
+; Total fan-out ; 46 ; ;
+; Average fan-out ; 1.53 ; ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+; Statistic ; Top ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 4 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; ALMs needed [=A-B+C] ; 4 ; 0 ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 4 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] ALMs used for LUT logic and registers ; 0 ; 0 ;
+; [b] ALMs used for LUT logic ; 4 ; 0 ;
+; [c] ALMs used for registers ; 0 ; 0 ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
+; [B] Estimate of ALMs recoverable by dense packing ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] Due to location constrained logic ; 0 ; 0 ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
+; [c] Due to LAB input limits ; 0 ; 0 ;
+; [d] Due to virtual I/Os ; 0 ; 0 ;
+; ; ; ;
+; Difficulty packing design ; Low ; Low ;
+; ; ; ;
+; Total LABs: partially or completely used ; 2 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ;
+; -- Logic LABs ; 2 ; 0 ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 8 ; 0 ;
+; -- 7 input functions ; 0 ; 0 ;
+; -- 6 input functions ; 0 ; 0 ;
+; -- 5 input functions ; 0 ; 0 ;
+; -- 4 input functions ; 7 ; 0 ;
+; -- <=3 input functions ; 1 ; 0 ;
+; Combinational ALUT usage for route-throughs ; 0 ; 0 ;
+; Memory ALUT usage ; 0 ; 0 ;
+; -- 64-address deep ; 0 ; 0 ;
+; -- 32-address deep ; 0 ; 0 ;
+; ; ; ;
+; Dedicated logic registers ; 0 ; 0 ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 0 / 64140 ( 0 % ) ; 0 / 64140 ( 0 % ) ;
+; -- Secondary logic registers ; 0 / 64140 ( 0 % ) ; 0 / 64140 ( 0 % ) ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 0 ; 0 ;
+; -- Routing optimization registers ; 0 ; 0 ;
+; ; ; ;
+; ; ; ;
+; Virtual pins ; 0 ; 0 ;
+; I/O pins ; 11 ; 0 ;
+; I/O registers ; 0 ; 0 ;
+; Total block memory bits ; 0 ; 0 ;
+; Total block memory implementation bits ; 0 ; 0 ;
+; ; ; ;
+; Connections ; ; ;
+; -- Input Connections ; 0 ; 0 ;
+; -- Registered Input Connections ; 0 ; 0 ;
+; -- Output Connections ; 0 ; 0 ;
+; -- Registered Output Connections ; 0 ; 0 ;
+; ; ; ;
+; Internal Connections ; ; ;
+; -- Total Connections ; 46 ; 0 ;
+; -- Registered Connections ; 0 ; 0 ;
+; ; ; ;
+; External Connections ; ; ;
+; -- Top ; 0 ; 0 ;
+; -- hard_block:auto_generated_inst ; 0 ; 0 ;
+; ; ; ;
+; Partition Interface ; ; ;
+; -- Input Ports ; 4 ; 0 ;
+; -- Output Ports ; 7 ; 0 ;
+; -- Bidir Ports ; 0 ; 0 ;
+; ; ; ;
+; Registered Ports ; ; ;
+; -- Registered Input Ports ; 0 ; 0 ;
+; -- Registered Output Ports ; 0 ; 0 ;
+; ; ; ;
+; Port Connectivity ; ; ;
+; -- Input Ports driven by GND ; 0 ; 0 ;
+; -- Output Ports driven by GND ; 0 ; 0 ;
+; -- Input Ports driven by VCC ; 0 ; 0 ;
+; -- Output Ports driven by VCC ; 0 ; 0 ;
+; -- Input Ports with no Source ; 0 ; 0 ;
+; -- Output Ports with no Source ; 0 ; 0 ;
+; -- Input Ports with no Fanout ; 0 ; 0 ;
+; -- Output Ports with no Fanout ; 0 ; 0 ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; SW[0] ; AB12 ; 3A ; 12 ; 0 ; 17 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[1] ; AC12 ; 3A ; 16 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[2] ; AF9 ; 3A ; 8 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[3] ; AF10 ; 3A ; 4 ; 0 ; 51 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++---------------------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+-----------------+---------------+--------------+---------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+-----------------+---------------+--------------+---------------+
+; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; 3A ; 4 / 32 ( 13 % ) ; 3.3V ; -- ; 3.3V ;
+; 3B ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 5A ; 7 / 32 ( 22 % ) ; 3.3V ; -- ; 3.3V ;
+; 5B ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
++----------+-----------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
+; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
+; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA14 ; 122 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA15 ; 120 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA27 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB12 ; 72 ; 3A ; SW[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB14 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB22 ; 225 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB23 ; 227 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB25 ; 230 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB28 ; 249 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC11 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC12 ; 82 ; 3A ; SW[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC21 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AC25 ; 215 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC27 ; 242 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC28 ; 245 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC29 ; 247 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC30 ; 259 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD8 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD10 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD11 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD12 ; 80 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD25 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD26 ; 240 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD27 ; 222 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD29 ; 255 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD30 ; 257 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE11 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE12 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE15 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE25 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE29 ; 253 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AE30 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF7 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF9 ; 67 ; 3A ; SW[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AF10 ; 57 ; 3A ; SW[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF14 ; 114 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AF29 ; 237 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AF30 ; 239 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG4 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG30 ; 243 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH26 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH29 ; 218 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AH30 ; 241 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ29 ; 216 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
+; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
+; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
+; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
+; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
+; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
+; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
+; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
+; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
+; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
+; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
+; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
+; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
+; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
+; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
+; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U23 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V16 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V18 ; 194 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W15 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W16 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W17 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W19 ; 192 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W20 ; 217 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W21 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y16 ; 128 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y19 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y21 ; 219 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; Y23 ; 232 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------+-------------+--------------+
+; |ex2 ; 4.0 (0.5) ; 4.0 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 11 ; 0 ; |ex2 ; ex2 ; work ;
+; |hex_to_7seg:SEG0| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex2|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; SW[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++-----------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++-----------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++-----------------------------------+-------------------+---------+
+; SW[0] ; ; ;
+; - hex_to_7seg:SEG0|WideOr6~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr5~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr4~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr3~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr2~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr1~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr0~0 ; 1 ; 0 ;
+; SW[1] ; ; ;
+; - hex_to_7seg:SEG0|WideOr6~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr5~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr4~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr3~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr2~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr1~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr0~0 ; 0 ; 0 ;
+; SW[2] ; ; ;
+; - hex_to_7seg:SEG0|WideOr6~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr5~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr4~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr3~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr2~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr1~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr0~0 ; 1 ; 0 ;
+; SW[3] ; ; ;
+; - hex_to_7seg:SEG0|WideOr6~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr5~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr4~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr3~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr2~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr1~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr0~0 ; 1 ; 0 ;
++-----------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------+
+; Routing Usage Summary ;
++---------------------------------------------+------------------------+
+; Routing Resource Type ; Usage ;
++---------------------------------------------+------------------------+
+; Block interconnects ; 11 / 289,320 ( < 1 % ) ;
+; C12 interconnects ; 5 / 13,420 ( < 1 % ) ;
+; C2 interconnects ; 4 / 119,108 ( < 1 % ) ;
+; C4 interconnects ; 7 / 56,300 ( < 1 % ) ;
+; DQS bus muxes ; 0 / 25 ( 0 % ) ;
+; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
+; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
+; Direct links ; 0 / 289,320 ( 0 % ) ;
+; Global clocks ; 0 / 16 ( 0 % ) ;
+; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
+; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
+; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
+; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
+; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
+; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
+; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
+; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
+; Local interconnects ; 0 / 84,580 ( 0 % ) ;
+; Quadrant clocks ; 0 / 66 ( 0 % ) ;
+; R14 interconnects ; 22 / 12,676 ( < 1 % ) ;
+; R14/C12 interconnect drivers ; 23 / 20,720 ( < 1 % ) ;
+; R3 interconnects ; 5 / 130,992 ( < 1 % ) ;
+; R6 interconnects ; 2 / 266,960 ( < 1 % ) ;
+; Spine clocks ; 0 / 360 ( 0 % ) ;
+; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
++---------------------------------------------+------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary ;
++----------------------------------+-------+
+; I/O Rules Statistic ; Total ;
++----------------------------------+-------+
+; Total I/O Rules ; 28 ;
+; Number of I/O Rules Passed ; 6 ;
+; Number of I/O Rules Failed ; 0 ;
+; Number of I/O Rules Unchecked ; 0 ;
+; Number of I/O Rules Inapplicable ; 22 ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
+; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
+; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
+; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass ; 11 ; 0 ; 11 ; 0 ; 0 ; 11 ; 11 ; 0 ; 11 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Inapplicable ; 0 ; 11 ; 0 ; 11 ; 11 ; 0 ; 0 ; 11 ; 0 ; 0 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ; 11 ;
+; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options ;
++------------------------------------------------------------------+-----------------------------+
+; Option ; Setting ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Passive Serial ;
+; Enable Error Detection CRC_ERROR pin ; Off ;
+; Enable CvP_CONFDONE pin ; Off ;
+; Enable open drain on CRC_ERROR pin ; On ;
+; Enable open drain on CvP_CONFDONE pin ; On ;
+; Enable open drain on INIT_DONE pin ; On ;
+; Enable open drain on Partial Reconfiguration pins ; Off ;
+; Enable open drain on nCEO pin ; On ;
+; Enable Partial Reconfiguration pins ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ;
+; Enable internal scrubbing ; Off ;
+; Active Serial clock source ; 100 MHz Internal Oscillator ;
+; Device initialization clock source ; Internal Oscillator ;
+; Configuration via Protocol ; Off ;
+; Configuration Voltage Level ; Auto ;
+; Force Configuration Voltage Level ; Off ;
+; Enable nCEO output ; Off ;
+; Data[15..8] ; Unreserved ;
+; Data[7..5] ; Unreserved ;
+; Base pin-out file on sameframe device ; Off ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.10 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex2"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (184020): Starting Fitter periphery placement operations
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+ Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+ Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
+Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info (170201): Optimizations that may affect the design's routability were skipped
+ Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (11888): Total time spent on timing analysis during the Fitter is 0.07 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file H:/VERI/part_1/ex2/output_files/ex2.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 76 warnings
+ Info: Peak virtual memory: 2575 megabytes
+ Info: Processing ended: Tue Nov 15 10:38:37 2016
+ Info: Elapsed time: 00:00:31
+ Info: Total CPU time (on all processors): 00:00:48
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in H:/VERI/part_1/ex2/output_files/ex2.fit.smsg.
+
+
diff --git a/part_1/ex2/output_files/ex2.fit.smsg b/part_1/ex2/output_files/ex2.fit.smsg new file mode 100644 index 0000000..43eead5 --- /dev/null +++ b/part_1/ex2/output_files/ex2.fit.smsg @@ -0,0 +1,6 @@ +Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_1/ex2/output_files/ex2.fit.summary b/part_1/ex2/output_files/ex2.fit.summary new file mode 100644 index 0000000..e34e158 --- /dev/null +++ b/part_1/ex2/output_files/ex2.fit.summary @@ -0,0 +1,20 @@ +Fitter Status : Successful - Tue Nov 15 10:38:35 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex2
+Top-level Entity Name : ex2
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 4 / 32,070 ( < 1 % )
+Total registers : 0
+Total pins : 11 / 457 ( 2 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_1/ex2/output_files/ex2.flow.rpt b/part_1/ex2/output_files/ex2.flow.rpt new file mode 100644 index 0000000..139c1ec --- /dev/null +++ b/part_1/ex2/output_files/ex2.flow.rpt @@ -0,0 +1,128 @@ +Flow report for ex2
+Tue Nov 15 10:39:00 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+ 8. Flow Messages
+ 9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary ;
++---------------------------------+-------------------------------------------------+
+; Flow Status ; Successful - Tue Nov 15 10:38:51 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex2 ;
+; Top-level Entity Name ; ex2 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 4 / 32,070 ( < 1 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 11 / 457 ( 2 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 11/15/2016 10:37:54 ;
+; Main task ; Compilation ;
+; Revision Name ; ex2 ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 260248564170200.147920627406516 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
+; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 881 MB ; 00:00:21 ;
+; Fitter ; 00:00:29 ; 1.0 ; 2575 MB ; 00:00:47 ;
+; Assembler ; 00:00:09 ; 1.0 ; 895 MB ; 00:00:06 ;
+; TimeQuest Timing Analyzer ; 00:00:07 ; 1.0 ; 1203 MB ; 00:00:05 ;
+; Total ; 00:00:56 ; -- ; -- ; 00:01:19 ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; Fitter ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; Assembler ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; TimeQuest Timing Analyzer ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex2 -c ex2
+quartus_fit --read_settings_files=off --write_settings_files=off ex2 -c ex2
+quartus_asm --read_settings_files=off --write_settings_files=off ex2 -c ex2
+quartus_sta ex2 -c ex2
+
+
+
diff --git a/part_1/ex2/output_files/ex2.jdi b/part_1/ex2/output_files/ex2.jdi new file mode 100644 index 0000000..f5b01a0 --- /dev/null +++ b/part_1/ex2/output_files/ex2.jdi @@ -0,0 +1,8 @@ +<sld_project_info>
+ <project>
+ <hash md5_digest_80b="d85a7b7273e7ef9c6506"/>
+ </project>
+ <file_info>
+ <file device="5CSEMA5F31C6" path="ex2.sof" usercode="0xFFFFFFFF"/>
+ </file_info>
+</sld_project_info>
diff --git a/part_1/ex2/output_files/ex2.map.rpt b/part_1/ex2/output_files/ex2.map.rpt new file mode 100644 index 0000000..fcc36dc --- /dev/null +++ b/part_1/ex2/output_files/ex2.map.rpt @@ -0,0 +1,287 @@ +Analysis & Synthesis report for ex2
+Tue Nov 15 10:38:05 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Source Files Read
+ 6. Analysis & Synthesis Resource Usage Summary
+ 7. Analysis & Synthesis Resource Utilization by Entity
+ 8. General Register Statistics
+ 9. Post-Synthesis Netlist Statistics for Top Partition
+ 10. Elapsed Time Per Partition
+ 11. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Tue Nov 15 10:38:05 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex2 ;
+; Top-level Entity Name ; ex2 ;
+; Family ; Cyclone V ;
+; Logic utilization (in ALMs) ; N/A ;
+; Total registers ; 0 ;
+; Total pins ; 11 ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 ;
+; Total DSP Blocks ; 0 ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Top-level entity name ; ex2 ; ex2 ;
+; Family name ; Cyclone V ; Cyclone V ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Infer RAMs from Raw Logic ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; On ; On ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 3 ; 3 ;
+; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
+; Synthesis Seed ; 1 ; 1 ;
+; Automatic Parallel Synthesis ; On ; On ;
+; Partial Reconfiguration Bitstream ID ; Off ; Off ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 1 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------+------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------+------------------------------------------------+---------+
+; verilog_files/hex_to_7seg.v ; yes ; User Verilog HDL File ; H:/VERI/part_1/ex2/verilog_files/hex_to_7seg.v ; ;
+; ex2.v ; yes ; User Verilog HDL File ; H:/VERI/part_1/ex2/ex2.v ; ;
++----------------------------------+-----------------+------------------------+------------------------------------------------+---------+
+
+
++-----------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+-------------+
+; Resource ; Usage ;
++---------------------------------------------+-------------+
+; Estimate of Logic utilization (ALMs needed) ; 4 ;
+; ; ;
+; Combinational ALUT usage for logic ; 7 ;
+; -- 7 input functions ; 0 ;
+; -- 6 input functions ; 0 ;
+; -- 5 input functions ; 0 ;
+; -- 4 input functions ; 7 ;
+; -- <=3 input functions ; 0 ;
+; ; ;
+; Dedicated logic registers ; 0 ;
+; ; ;
+; I/O pins ; 11 ;
+; ; ;
+; Total DSP Blocks ; 0 ;
+; ; ;
+; Maximum fan-out node ; SW[0]~input ;
+; Maximum fan-out ; 7 ;
+; Total fan-out ; 46 ;
+; Average fan-out ; 1.59 ;
++---------------------------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------+-------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------+-------------+--------------+
+; |ex2 ; 7 (0) ; 0 (0) ; 0 ; 0 ; 11 ; 0 ; |ex2 ; ex2 ; work ;
+; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex2|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 0 ;
+; Number of registers using Synchronous Clear ; 0 ;
+; Number of registers using Synchronous Load ; 0 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 0 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type ; Count ;
++-----------------------+-----------------------------+
+; arriav_lcell_comb ; 8 ;
+; normal ; 8 ;
+; 1 data inputs ; 1 ;
+; 4 data inputs ; 7 ;
+; boundary_port ; 11 ;
+; ; ;
+; Max LUT depth ; 2.00 ;
+; Average LUT depth ; 1.50 ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top ; 00:00:00 ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 10:37:53 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex2 -c ex2
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+ Info (12023): Found entity 1: hex_to_7seg File: H:/VERI/part_1/ex2/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file ex2.v
+ Info (12023): Found entity 1: ex2 File: H:/VERI/part_1/ex2/ex2.v Line: 1
+Info (12127): Elaborating entity "ex2" for the top level hierarchy
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/VERI/part_1/ex2/ex2.v Line: 7
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+ Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 18 device resources after synthesis - the final resource count might be different
+ Info (21058): Implemented 4 input pins
+ Info (21059): Implemented 7 output pins
+ Info (21061): Implemented 7 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 881 megabytes
+ Info: Processing ended: Tue Nov 15 10:38:05 2016
+ Info: Elapsed time: 00:00:12
+ Info: Total CPU time (on all processors): 00:00:22
+
+
diff --git a/part_1/ex2/output_files/ex2.map.summary b/part_1/ex2/output_files/ex2.map.summary new file mode 100644 index 0000000..d6d6992 --- /dev/null +++ b/part_1/ex2/output_files/ex2.map.summary @@ -0,0 +1,17 @@ +Analysis & Synthesis Status : Successful - Tue Nov 15 10:38:05 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex2
+Top-level Entity Name : ex2
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 0
+Total pins : 11
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_1/ex2/output_files/ex2.pin b/part_1/ex2/output_files/ex2.pin new file mode 100644 index 0000000..e308c9f --- /dev/null +++ b/part_1/ex2/output_files/ex2.pin @@ -0,0 +1,976 @@ + -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other
+ -- applicable license agreement, including, without limitation,
+ -- that your use is for the sole purpose of programming logic
+ -- devices manufactured by Altera and sold by Altera or its
+ -- authorized distributors. Please refer to the applicable
+ -- agreement for further details.
+ --
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 3A: 3.3V
+ -- Bank 3B: 2.5V
+ -- Bank 4A: 2.5V
+ -- Bank 5A: 3.3V
+ -- Bank 5B: 2.5V
+ -- Bank 6B: 2.5V
+ -- Bank 6A: 2.5V
+ -- Bank 7A: 2.5V
+ -- Bank 7B: 2.5V
+ -- Bank 7C: 2.5V
+ -- Bank 7D: 2.5V
+ -- Bank 8A: 2.5V
+ -- RREF : External reference resistor for the quad, MUST be connected to
+ -- GND via a 2k Ohm resistor.
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
+ -- must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP "ex2" ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A :
+VCCIO8A : A7 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A :
+GND : A12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C :
+GND : A17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B :
+GND : A22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A :
+GND : A26 : : : : 7A :
+GND : A27 : gnd : : : :
+HPS_TRST : A28 : : : : 7A :
+HPS_TMS : A29 : : : : 7A :
+GND : AA1 : gnd : : : :
+GND : AA2 : gnd : : : :
+GND : AA3 : gnd : : : :
+GND : AA4 : gnd : : : :
+VCC : AA5 : power : : 1.1V : :
+GND : AA6 : gnd : : : :
+DNU : AA7 : : : : :
+VCCA_FPLL : AA8 : power : : 2.5V : :
+GND : AA9 : gnd : : : :
+VCCPD3A : AA10 : power : : 3.3V : 3A :
+GND : AA11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
+VCCIO4A : AA17 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
+GND : AA22 : gnd : : : :
+VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
+VCCIO5B : AA27 : power : : 2.5V : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 5B :
+VREFB5BN0 : AA29 : power : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B :
+GND : AB1 : gnd : : : :
+GND : AB2 : gnd : : : :
+DNU : AB3 : : : : :
+DNU : AB4 : : : : :
+GND : AB5 : gnd : : : :
+VCCA_FPLL : AB6 : power : : 2.5V : :
+GND : AB7 : gnd : : : :
+nCSO, DATA4 : AB8 : : : : 3A :
+TDO : AB9 : output : : : 3A :
+VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX : AB11 : power : : 2.5V : :
+SW[0] : AB12 : input : 3.3-V LVTTL : : 3A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B :
+VCCIO3B : AB14 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B :
+VCC_AUX : AB16 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
+VCCPD3B4A : AB18 : power : : 2.5V : 3B, 4A :
+GND : AB19 : gnd : : : :
+VCCPD3B4A : AB20 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5A :
+VCCIO5A : AB24 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28 : : : : 5B :
+GND : AB29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B :
+GND : AC1 : gnd : : : :
+GND : AC2 : gnd : : : :
+GND : AC3 : gnd : : : :
+GND : AC4 : gnd : : : :
+TCK : AC5 : input : : : 3A :
+GND : AC6 : gnd : : : :
+AS_DATA3, DATA3 : AC7 : : : : 3A :
+GND : AC8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3A :
+VCCPD3A : AC10 : power : : 3.3V : 3A :
+VCCIO3A : AC11 : power : : 3.3V : 3A :
+SW[1] : AC12 : input : 3.3-V LVTTL : : 3A : Y
+VCCPD3B4A : AC13 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3B :
+VCCPD3B4A : AC15 : power : : 2.5V : 3B, 4A :
+GND : AC16 : gnd : : : :
+VCCPD3B4A : AC17 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
+VCCPD3B4A : AC19 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
+VCCIO4A : AC21 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
+VREFB5AN0 : AC24 : power : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5A :
+GND : AC26 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC28 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC29 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC30 : : : : 5B :
+GND : AD1 : gnd : : : :
+GND : AD2 : gnd : : : :
+DNU : AD3 : : : : :
+DNU : AD4 : : : : :
+GND : AD5 : gnd : : : :
+VREFB3AN0 : AD6 : power : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
+VCCIO3A : AD8 : power : : 3.3V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3A :
+VCCIO3B : AD13 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B :
+DNU : AD15 : : : : :
+VCCPD3B4A : AD16 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
+VCCIO4A : AD18 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
+VCC_AUX : AD22 : power : : 2.5V : :
+GND : AD23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD27 : : : : 5A :
+VCCIO5A : AD28 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD29 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD30 : : : : 5B :
+GND : AE1 : gnd : : : :
+GND : AE2 : gnd : : : :
+GND : AE3 : gnd : : : :
+GND : AE4 : gnd : : : :
+AS_DATA1, DATA1 : AE5 : : : : 3A :
+AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3A :
+AS_DATA2, DATA2 : AE8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3A :
+GND : AE10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B :
+VCCIO3B : AE15 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
+GND : AE20 : gnd : : : :
+VCCPD3B4A : AE21 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
+VCCIO4A : AE25 : power : : 2.5V : 4A :
+HEX0[0] : AE26 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[1] : AE27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[2] : AE28 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE29 : : : : 5B :
+VCCIO5B : AE30 : power : : 2.5V : 5B :
+GND : AF1 : gnd : : : :
+GND : AF2 : gnd : : : :
+GND : AF3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A :
+VCCIO3A : AF7 : power : : 3.3V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A :
+SW[2] : AF9 : input : 3.3-V LVTTL : : 3A : Y
+SW[3] : AF10 : input : 3.3-V LVTTL : : 3A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
+GND : AF12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
+GND : AF17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
+VCCIO4A : AF22 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A :
+GND : AF27 : gnd : : : :
+HEX0[4] : AF28 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF29 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF30 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A :
+VCCIO3A : AG4 : power : : 3.3V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3A :
+GND : AG9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B :
+GND : AG14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
+VCCIO4A : AG19 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
+GND : AG24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
+HEX0[3] : AG27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[5] : AG28 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AG29 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG30 : : : : 5A :
+GND : AH1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A :
+GND : AH6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3B :
+GND : AH11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15 : : : : 3B :
+VCCIO4A : AH16 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A :
+GND : AH21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4A :
+VCCIO4A : AH26 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
+HEX0[6] : AH28 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH29 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH30 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2 : : : : 3A :
+GND : AJ3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B :
+VCCIO3B : AJ8 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B :
+VCCIO3B : AJ13 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B :
+VREFB3BN0 : AJ15 : power : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A :
+GND : AJ18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 4A :
+VCCIO4A : AJ23 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A :
+GND : AJ28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ29 : : : : 5A :
+GND : AJ30 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4 : : : : 3B :
+GND : AK5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B :
+VCCIO3B : AK10 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B :
+GND : AK15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A :
+VREFB4AN0 : AK17 : power : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A :
+VCCIO4A : AK20 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A :
+GND : AK25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A :
+VCCIO8A : B4 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A :
+GND : B9 : gnd : : : :
+VREFB8AN0 : B10 : power : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A :
+GND : B14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B :
+GND : B19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A :
+GND : B24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A :
+HPS_TDI : B27 : : : : 7A :
+HPS_TDO : B28 : : : : 7A :
+GND : B29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A :
+GND : C1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A :
+GND : C6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A :
+VCCIO8A : C11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D :
+GND : C16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B :
+GND : C21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A :
+GND : C26 : gnd : : : :
+HPS_nRST : C27 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A :
+GND : D3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
+VCCIO8A : D8 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
+GND : D13 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C :
+VCCIO7C_HPS : D18 : power : : 2.5V : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A :
+GND : D23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A :
+HPS_CLK1 : D25 : : : : 7A :
+GND : D26 : : : : 7A :
+HPS_RZQ_0 : D27 : : : : 6A :
+VCCIO6A_HPS : D28 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A :
+VCCIO8A : E5 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
+GND : E10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D :
+VCCIO7D_HPS : E15 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B :
+VCCIO7B_HPS : E20 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B :
+VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A :
+GND : E25 : gnd : : : :
+DNU : E26 : : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A :
+GND : E30 : gnd : : : :
+DNU : F1 : : : : :
+GND : F2 : gnd : : : :
+CONF_DONE : F3 : : : : 9A :
+nSTATUS : F4 : : : : 9A :
+GND : F5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
+GND : F7 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A :
+VCCIO8A : F12 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D :
+GND : F17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B :
+VCCIO7A_HPS : F22 : power : : 2.5V : 7A :
+HPS_nPOR : F23 : : : : 7A :
+HPS_PORSEL : F24 : : : : 7A :
+HPS_CLK2 : F25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
+GND : F27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A :
+GND : G1 : : : : :
+DNU : G2 : : : : :
+GND : G3 : gnd : : : :
+GND : G4 : gnd : : : :
+nCE : G5 : : : : 9A :
+MSEL2 : G6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8A :
+VCCIO8A : G9 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A :
+VCCIO8A : G14 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C :
+VCCIO7B_HPS : G19 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A :
+VCCRSTCLK_HPS : G23 : : : : 7A :
+GND : G24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
+VCCIO6A_HPS : G29 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A :
+GND : H1 : gnd : : : :
+GND : H2 : gnd : : : :
+DNU : H3 : : : : :
+DNU : H4 : : : : :
+GND : H5 : gnd : : : :
+VCCIO8A : H6 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
+VCCBAT : H9 : power : : 1.2V : :
+VCC_AUX : H10 : power : : 2.5V : :
+GND : H11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A :
+VCCIO7D_HPS : H16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A :
+VCCIO7A_HPS : H21 : power : : 2.5V : 7A :
+HPS_TCK : H22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
+VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A :
+GND : J1 : gnd : : : :
+GND : J2 : gnd : : : :
+GND : J3 : gnd : : : :
+GND : J4 : gnd : : : :
+nCONFIG : J5 : : : : 9A :
+GND : J6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
+GND : J8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
+VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A :
+VCCIO8A : J13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8A :
+DNU : J15 : : : : :
+VCC_AUX : J16 : power : : 2.5V : :
+VCCPD7C_HPS : J17 : power : : 2.5V : 7C :
+GND : J18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B :
+VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX_SHARED : J21 : power : : 2.5V : :
+GND : J22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
+GND : J28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A :
+GND : K1 : gnd : : : :
+GND : K2 : gnd : : : :
+DNU : K3 : : : : :
+DNU : K4 : : : : :
+GND : K5 : gnd : : : :
+MSEL1 : K6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
+VCCA_FPLL : K9 : power : : 2.5V : :
+GND : K10 : gnd : : : :
+VCCPD8A : K11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 8A :
+VCCPD8A : K13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A :
+GND : K15 : gnd : : : :
+VCCPD7D_HPS : K16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B :
+VCCPD7B_HPS : K18 : power : : 2.5V : 7B :
+VCCPD7A_HPS : K19 : power : : 2.5V : 7A :
+GND : K20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
+VCCIO6A_HPS : K24 : power : : 2.5V : 6A :
+GND : K25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A :
+VCCIO6A_HPS : K30 : power : : 2.5V : 6A :
+GND : L1 : gnd : : : :
+GND : L2 : gnd : : : :
+GND : L3 : gnd : : : :
+GND : L4 : gnd : : : :
+VCC : L5 : power : : 1.1V : :
+GND : L6 : gnd : : : :
+MSEL3 : L7 : : : : 9A :
+MSEL0 : L8 : : : : 9A :
+MSEL4 : L9 : : : : 9A :
+VCCPD8A : L10 : power : : 2.5V : 8A :
+GND : L11 : gnd : : : :
+VCCPD8A : L12 : power : : 2.5V : 8A :
+GND : L13 : gnd : : : :
+VCCPD8A : L14 : power : : 2.5V : 8A :
+GND : L15 : gnd : : : :
+VCC_HPS : L16 : power : : 1.1V : :
+GND : L17 : gnd : : : :
+VCC_HPS : L18 : power : : 1.1V : :
+GND : L19 : gnd : : : :
+VCC_HPS : L20 : power : : 1.1V : :
+VCCPLL_HPS : L21 : power : : 2.5V : :
+GND : L22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A :
+VCCIO6A_HPS : L27 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A :
+GND : M1 : gnd : : : :
+GND : M2 : gnd : : : :
+DNU : M3 : : : : :
+DNU : M4 : : : : :
+GND : M5 : gnd : : : :
+VCC : M6 : power : : 1.1V : :
+GND : M7 : gnd : : : :
+GND : M8 : gnd : : : :
+VCC : M9 : power : : 1.1V : :
+GND : M10 : gnd : : : :
+VCC : M11 : power : : 1.1V : :
+GND : M12 : gnd : : : :
+VCC : M13 : power : : 1.1V : :
+GND : M14 : gnd : : : :
+VCC_HPS : M15 : power : : 1.1V : :
+GND : M16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D :
+GND : M18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A :
+GND : M20 : gnd : : : :
+VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A :
+VCCIO6A_HPS : M24 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
+GND : M29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A :
+GND : N1 : gnd : : : :
+GND : N2 : gnd : : : :
+GND : N3 : gnd : : : :
+GND : N4 : gnd : : : :
+VCC : N5 : power : : 1.1V : :
+GND : N6 : gnd : : : :
+VCCA_FPLL : N7 : power : : 2.5V : :
+GND : N8 : gnd : : : :
+GND : N9 : gnd : : : :
+VCC : N10 : power : : 1.1V : :
+GND : N11 : gnd : : : :
+VCC : N12 : power : : 1.1V : :
+GND : N13 : gnd : : : :
+VCC : N14 : power : : 1.1V : :
+GND : N15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D :
+GND : N17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A :
+GND : N19 : gnd : : : :
+VCC_HPS : N20 : power : : 1.1V : :
+VCCIO6A_HPS : N21 : power : : 2.5V : 6A :
+VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A :
+GND : N26 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B :
+GND : P1 : gnd : : : :
+GND : P2 : gnd : : : :
+DNU : P3 : : : : :
+DNU : P4 : : : : :
+GND : P5 : gnd : : : :
+VCCA_FPLL : P6 : power : : 2.5V : :
+GND : P7 : gnd : : : :
+GND : P8 : gnd : : : :
+GND : P9 : gnd : : : :
+GND : P10 : gnd : : : :
+VCC : P11 : power : : 1.1V : :
+GND : P12 : gnd : : : :
+VCC : P13 : power : : 1.1V : :
+GND : P14 : gnd : : : :
+VCC_HPS : P15 : power : : 1.1V : :
+GND : P16 : gnd : : : :
+VCC_HPS : P17 : power : : 1.1V : :
+GND : P18 : gnd : : : :
+VCC_HPS : P19 : power : : 1.1V : :
+GND : P20 : gnd : : : :
+VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B :
+VCCIO6B_HPS : P23 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B :
+VCCIO6B_HPS : P28 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B :
+GND : R1 : gnd : : : :
+GND : R2 : gnd : : : :
+GND : R3 : gnd : : : :
+GND : R4 : gnd : : : :
+VCC : R5 : power : : 1.1V : :
+GND : R6 : gnd : : : :
+VCCA_FPLL : R7 : power : : 2.5V : :
+GND : R8 : gnd : : : :
+GND : R9 : gnd : : : :
+VCC : R10 : power : : 1.1V : :
+GND : R11 : gnd : : : :
+VCC : R12 : power : : 1.1V : :
+GND : R13 : gnd : : : :
+VCC : R14 : power : : 1.1V : :
+GND : R15 : gnd : : : :
+VCC_HPS : R16 : power : : 1.1V : :
+GND : R17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B :
+VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B :
+VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
+VCCIO6B_HPS : R25 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B :
+GND : R30 : gnd : : : :
+GND : T1 : gnd : : : :
+GND : T2 : gnd : : : :
+DNU : T3 : : : : :
+DNU : T4 : : : : :
+GND : T5 : gnd : : : :
+VCC : T6 : power : : 1.1V : :
+GND : T7 : gnd : : : :
+GND : T8 : gnd : : : :
+GND : T9 : gnd : : : :
+GND : T10 : gnd : : : :
+VCC : T11 : power : : 1.1V : :
+GND : T12 : gnd : : : :
+VCC : T13 : power : : 1.1V : :
+GND : T14 : gnd : : : :
+GND : T15 : gnd : : : :
+GND : T16 : gnd : : : :
+VCC_HPS : T17 : power : : 1.1V : :
+GND : T18 : gnd : : : :
+VCC_HPS : T19 : power : : 1.1V : :
+GND : T20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B :
+VCCIO6B_HPS : T22 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
+GND : T27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B :
+GND : U1 : gnd : : : :
+GND : U2 : gnd : : : :
+GND : U3 : gnd : : : :
+GND : U4 : gnd : : : :
+VCC : U5 : power : : 1.1V : :
+GND : U6 : gnd : : : :
+DCLK : U7 : : : : 3A :
+TDI : U8 : input : : : 3A :
+GND : U9 : gnd : : : :
+VCC : U10 : power : : 1.1V : :
+GND : U11 : gnd : : : :
+VCC : U12 : power : : 1.1V : :
+GND : U13 : gnd : : : :
+VCC : U14 : power : : 1.1V : :
+GND : U15 : gnd : : : :
+VCC_HPS : U16 : power : : 1.1V : :
+GND : U17 : gnd : : : :
+VCC_HPS : U18 : power : : 1.1V : :
+VCCIO6B_HPS : U19 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B :
+VCC : U21 : power : : 1.1V : :
+GND : U22 : gnd : : : :
+VCCPD5B : U23 : power : : 2.5V : 5B :
+GND : U24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
+GND : U29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B :
+GND : V1 : gnd : : : :
+GND : V2 : gnd : : : :
+DNU : V3 : : : : :
+DNU : V4 : : : : :
+GND : V5 : gnd : : : :
+VCCA_FPLL : V6 : power : : 2.5V : :
+GND : V7 : gnd : : : :
+VCCA_FPLL : V8 : power : : 2.5V : :
+TMS : V9 : input : : : 3A :
+GND : V10 : gnd : : : :
+VCC : V11 : power : : 1.1V : :
+GND : V12 : gnd : : : :
+VCC : V13 : power : : 1.1V : :
+GND : V14 : gnd : : : :
+VCC : V15 : power : : 1.1V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
+GND : V19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
+GND : V21 : gnd : : : :
+VCCPD5A : V22 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5A :
+VCCPD5A : V24 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
+VCCIO6B_HPS : V26 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B :
+GND : W1 : gnd : : : :
+GND : W2 : gnd : : : :
+GND : W3 : gnd : : : :
+GND : W4 : gnd : : : :
+VCC : W5 : power : : 1.1V : :
+GND : W6 : gnd : : : :
+GND : W7 : gnd : : : :
+GND : W8 : gnd : : : :
+GND : W9 : gnd : : : :
+VCC : W10 : power : : 1.1V : :
+GND : W11 : gnd : : : :
+VCC : W12 : power : : 1.1V : :
+GND : W13 : gnd : : : :
+VCC : W14 : power : : 1.1V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
+GND : W18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5A :
+VCCIO5A : W23 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W24 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B :
+GND : W28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B :
+GND : Y1 : gnd : : : :
+GND : Y2 : gnd : : : :
+DNU : Y3 : : : : :
+DNU : Y4 : : : : :
+GND : Y5 : gnd : : : :
+VCC : Y6 : power : : 1.1V : :
+GND : Y7 : gnd : : : :
+GND : Y8 : gnd : : : :
+VCC : Y9 : power : : 1.1V : :
+GND : Y10 : gnd : : : :
+VCC : Y11 : power : : 1.1V : :
+GND : Y12 : gnd : : : :
+VCC : Y13 : power : : 1.1V : :
+GND : Y14 : gnd : : : :
+GND : Y15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
+GND : Y20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5A :
+VCCA_FPLL : Y22 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A :
+GND : Y25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B :
+GND : Y30 : gnd : : : :
diff --git a/part_1/ex2/output_files/ex2.sld b/part_1/ex2/output_files/ex2.sld new file mode 100644 index 0000000..41a6030 --- /dev/null +++ b/part_1/ex2/output_files/ex2.sld @@ -0,0 +1 @@ +<sld_project_info/>
diff --git a/part_1/ex2/output_files/ex2.sof b/part_1/ex2/output_files/ex2.sof Binary files differnew file mode 100644 index 0000000..5628bd7 --- /dev/null +++ b/part_1/ex2/output_files/ex2.sof diff --git a/part_1/ex2/output_files/ex2.sta.rpt b/part_1/ex2/output_files/ex2.sta.rpt new file mode 100644 index 0000000..1c421d8 --- /dev/null +++ b/part_1/ex2/output_files/ex2.sta.rpt @@ -0,0 +1,533 @@ +TimeQuest Timing Analyzer report for ex2
+Tue Nov 15 10:39:00 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. TimeQuest Timing Analyzer Summary
+ 3. Parallel Compilation
+ 4. Clocks
+ 5. Slow 1100mV 85C Model Fmax Summary
+ 6. Timing Closure Recommendations
+ 7. Slow 1100mV 85C Model Setup Summary
+ 8. Slow 1100mV 85C Model Hold Summary
+ 9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Clock Transfers
+ 40. Report TCCS
+ 41. Report RSKM
+ 42. Unconstrained Paths Summary
+ 43. Unconstrained Input Ports
+ 44. Unconstrained Output Ports
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer ; TimeQuest ;
+; Revision Name ; ex2 ;
+; Device Family ; Cyclone V ;
+; Device Name ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Delay Model ; Combined ;
+; Rise/Fall Delays ; Enabled ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.01 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.8% ;
+; Processors 3-4 ; 0.1% ;
++----------------------------+-------------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+---------------------------------------
+; Fast 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Fast 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
+; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------+
+; Input Transition Times ;
++-------+--------------+-----------------+-----------------+
+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------+--------------+-----------------+-----------------+
+; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
++-------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary ;
++---------------------------------+-------+------+
+; Property ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks ; 0 ; 0 ;
+; Unconstrained Clocks ; 0 ; 0 ;
+; Unconstrained Input Ports ; 4 ; 4 ;
+; Unconstrained Input Port Paths ; 28 ; 28 ;
+; Unconstrained Output Ports ; 7 ; 7 ;
+; Unconstrained Output Port Paths ; 28 ; 28 ;
++---------------------------------+-------+------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 10:38:53 2016
+Info: Command: quartus_sta ex2 -c ex2
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1100mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
+ Info: Peak virtual memory: 1203 megabytes
+ Info: Processing ended: Tue Nov 15 10:39:00 2016
+ Info: Elapsed time: 00:00:07
+ Info: Total CPU time (on all processors): 00:00:05
+
+
diff --git a/part_1/ex2/output_files/ex2.sta.summary b/part_1/ex2/output_files/ex2.sta.summary new file mode 100644 index 0000000..6640100 --- /dev/null +++ b/part_1/ex2/output_files/ex2.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/part_1/ex2/verilog_files/hex_to_7seg.v b/part_1/ex2/verilog_files/hex_to_7seg.v new file mode 100644 index 0000000..82aa9a5 --- /dev/null +++ b/part_1/ex2/verilog_files/hex_to_7seg.v @@ -0,0 +1,27 @@ +module hex_to_7seg (out, in);
+
+ output [6:0] out;
+ input [3:0] in;
+
+ reg [6:0] out;
+
+ always @ (*)
+ case(in)
+ 4'h0: out = 7'b1000000;
+ 4'h1: out = 7'b1111001;
+ 4'h2: out = 7'b0100100;
+ 4'h3: out = 7'b0110000;
+ 4'h4: out = 7'b0011001;
+ 4'h5: out = 7'b0010010;
+ 4'h6: out = 7'b0000010;
+ 4'h7: out = 7'b1111000;
+ 4'h8: out = 7'b0000000;
+ 4'h9: out = 7'b0011000;
+ 4'ha: out = 7'b0001000;
+ 4'hb: out = 7'b0000011;
+ 4'hc: out = 7'b1000110;
+ 4'hd: out = 7'b0100001;
+ 4'he: out = 7'b0000110;
+ 4'hf: out = 7'b0001110;
+ endcase
+endmodule
diff --git a/part_1/ex3/c5_pin_model_dump.txt b/part_1/ex3/c5_pin_model_dump.txt new file mode 100644 index 0000000..a895a64 --- /dev/null +++ b/part_1/ex3/c5_pin_model_dump.txt @@ -0,0 +1,118 @@ +io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_1/ex3/db/_cmp.kpt b/part_1/ex3/db/_cmp.kpt Binary files differnew file mode 100644 index 0000000..bdb612b --- /dev/null +++ b/part_1/ex3/db/_cmp.kpt diff --git a/part_1/ex3/db/ex3.(0).cnf.cdb b/part_1/ex3/db/ex3.(0).cnf.cdb Binary files differnew file mode 100644 index 0000000..e746c9d --- /dev/null +++ b/part_1/ex3/db/ex3.(0).cnf.cdb diff --git a/part_1/ex3/db/ex3.(0).cnf.hdb b/part_1/ex3/db/ex3.(0).cnf.hdb Binary files differnew file mode 100644 index 0000000..52e8410 --- /dev/null +++ b/part_1/ex3/db/ex3.(0).cnf.hdb diff --git a/part_1/ex3/db/ex3.(1).cnf.cdb b/part_1/ex3/db/ex3.(1).cnf.cdb Binary files differnew file mode 100644 index 0000000..6627ad7 --- /dev/null +++ b/part_1/ex3/db/ex3.(1).cnf.cdb diff --git a/part_1/ex3/db/ex3.(1).cnf.hdb b/part_1/ex3/db/ex3.(1).cnf.hdb Binary files differnew file mode 100644 index 0000000..684a21e --- /dev/null +++ b/part_1/ex3/db/ex3.(1).cnf.hdb diff --git a/part_1/ex3/db/ex3.ae.hdb b/part_1/ex3/db/ex3.ae.hdb Binary files differnew file mode 100644 index 0000000..1b71cb2 --- /dev/null +++ b/part_1/ex3/db/ex3.ae.hdb diff --git a/part_1/ex3/db/ex3.analyze_file.qmsg b/part_1/ex3/db/ex3.analyze_file.qmsg new file mode 100644 index 0000000..09a9df5 --- /dev/null +++ b/part_1/ex3/db/ex3.analyze_file.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479207336847 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479207336850 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 10:55:36 2016 " "Processing started: Tue Nov 15 10:55:36 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479207336850 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479207336850 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex3 -c ex3 --analyze_file=H:/VERI/part_1/ex3/ex3.v " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex3 -c ex3 --analyze_file=H:/VERI/part_1/ex3/ex3.v" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479207336851 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479207337367 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479207337367 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1 Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "831 " "Peak virtual memory: 831 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479207345917 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:55:45 2016 " "Processing ended: Tue Nov 15 10:55:45 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479207345917 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479207345917 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479207345917 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479207345917 ""}
diff --git a/part_1/ex3/db/ex3.asm.qmsg b/part_1/ex3/db/ex3.asm.qmsg new file mode 100644 index 0000000..9e1ba3d --- /dev/null +++ b/part_1/ex3/db/ex3.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479207493282 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479207493285 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 10:58:12 2016 " "Processing started: Tue Nov 15 10:58:12 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479207493285 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479207493285 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex3 -c ex3 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex3 -c ex3" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479207493286 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479207494181 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479207499113 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "893 " "Peak virtual memory: 893 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479207503199 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:58:23 2016 " "Processing ended: Tue Nov 15 10:58:23 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479207503199 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479207503199 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479207503199 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479207503199 ""}
diff --git a/part_1/ex3/db/ex3.asm.rdb b/part_1/ex3/db/ex3.asm.rdb Binary files differnew file mode 100644 index 0000000..f021282 --- /dev/null +++ b/part_1/ex3/db/ex3.asm.rdb diff --git a/part_1/ex3/db/ex3.cbx.xml b/part_1/ex3/db/ex3.cbx.xml new file mode 100644 index 0000000..141f72a --- /dev/null +++ b/part_1/ex3/db/ex3.cbx.xml @@ -0,0 +1,5 @@ +<?xml version="1.0" ?>
+<LOG_ROOT>
+ <PROJECT NAME="ex3">
+ </PROJECT>
+</LOG_ROOT>
diff --git a/part_1/ex3/db/ex3.cmp.ammdb b/part_1/ex3/db/ex3.cmp.ammdb Binary files differnew file mode 100644 index 0000000..87d96f8 --- /dev/null +++ b/part_1/ex3/db/ex3.cmp.ammdb diff --git a/part_1/ex3/db/ex3.cmp.bpm b/part_1/ex3/db/ex3.cmp.bpm Binary files differnew file mode 100644 index 0000000..ea9e263 --- /dev/null +++ b/part_1/ex3/db/ex3.cmp.bpm diff --git a/part_1/ex3/db/ex3.cmp.cdb b/part_1/ex3/db/ex3.cmp.cdb Binary files differnew file mode 100644 index 0000000..2911412 --- /dev/null +++ b/part_1/ex3/db/ex3.cmp.cdb diff --git a/part_1/ex3/db/ex3.cmp.hdb b/part_1/ex3/db/ex3.cmp.hdb Binary files differnew file mode 100644 index 0000000..dddc535 --- /dev/null +++ b/part_1/ex3/db/ex3.cmp.hdb diff --git a/part_1/ex3/db/ex3.cmp.idb b/part_1/ex3/db/ex3.cmp.idb Binary files differnew file mode 100644 index 0000000..7dd7003 --- /dev/null +++ b/part_1/ex3/db/ex3.cmp.idb diff --git a/part_1/ex3/db/ex3.cmp.logdb b/part_1/ex3/db/ex3.cmp.logdb new file mode 100644 index 0000000..b3ee177 --- /dev/null +++ b/part_1/ex3/db/ex3.cmp.logdb @@ -0,0 +1,70 @@ +v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,31;0;31;0;0;31;31;0;31;31;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;31;0;31;31;0;0;31;0;0;31;31;31;31;31;31;31;31;31;31;31;31;31;31;31;31;31;31,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_1/ex3/db/ex3.cmp.rdb b/part_1/ex3/db/ex3.cmp.rdb Binary files differnew file mode 100644 index 0000000..111ecbb --- /dev/null +++ b/part_1/ex3/db/ex3.cmp.rdb diff --git a/part_1/ex3/db/ex3.cmp_merge.kpt b/part_1/ex3/db/ex3.cmp_merge.kpt Binary files differnew file mode 100644 index 0000000..d035d63 --- /dev/null +++ b/part_1/ex3/db/ex3.cmp_merge.kpt diff --git a/part_1/ex3/db/ex3.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_1/ex3/db/ex3.cyclonev_io_sim_cache.ff_0c_fast.hsd Binary files differnew file mode 100644 index 0000000..5b115d6 --- /dev/null +++ b/part_1/ex3/db/ex3.cyclonev_io_sim_cache.ff_0c_fast.hsd diff --git a/part_1/ex3/db/ex3.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_1/ex3/db/ex3.cyclonev_io_sim_cache.ff_85c_fast.hsd Binary files differnew file mode 100644 index 0000000..3a7a497 --- /dev/null +++ b/part_1/ex3/db/ex3.cyclonev_io_sim_cache.ff_85c_fast.hsd diff --git a/part_1/ex3/db/ex3.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_1/ex3/db/ex3.cyclonev_io_sim_cache.tt_0c_slow.hsd Binary files differnew file mode 100644 index 0000000..aa473fa --- /dev/null +++ b/part_1/ex3/db/ex3.cyclonev_io_sim_cache.tt_0c_slow.hsd diff --git a/part_1/ex3/db/ex3.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_1/ex3/db/ex3.cyclonev_io_sim_cache.tt_85c_slow.hsd Binary files differnew file mode 100644 index 0000000..dce4f6b --- /dev/null +++ b/part_1/ex3/db/ex3.cyclonev_io_sim_cache.tt_85c_slow.hsd diff --git a/part_1/ex3/db/ex3.db_info b/part_1/ex3/db/ex3.db_info new file mode 100644 index 0000000..1bbb78a --- /dev/null +++ b/part_1/ex3/db/ex3.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 15 10:48:27 2016
diff --git a/part_1/ex3/db/ex3.fit.qmsg b/part_1/ex3/db/ex3.fit.qmsg new file mode 100644 index 0000000..31b387b --- /dev/null +++ b/part_1/ex3/db/ex3.fit.qmsg @@ -0,0 +1,45 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479207458296 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479207458298 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex3 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex3\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479207458581 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479207458642 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479207458642 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479207459051 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479207459208 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479207469298 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479207469329 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479207469331 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479207469331 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479207469331 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479207469332 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479207469332 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479207469332 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479207469332 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479207469334 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479207469334 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479207469359 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479207469359 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479207469369 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex3.sdc " "Synopsys Design Constraints File file not found: 'ex3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1479207474780 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1479207474781 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1479207474781 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1479207474781 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479207474782 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1479207474782 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1479207474784 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479207474786 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479207474855 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479207475262 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479207475606 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479207475840 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479207475841 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479207476496 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" { } { { "loc" "" { Generic "H:/VERI/part_1/ex3/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479207480744 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479207480744 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479207480902 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479207480902 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479207480902 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479207480906 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.07 " "Total time spent on timing analysis during the Fitter is 0.07 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479207482213 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479207482252 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479207482625 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479207482625 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479207482985 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479207485088 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479207485313 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/VERI/part_1/ex3/output_files/ex3.fit.smsg " "Generated suppressed messages file H:/VERI/part_1/ex3/output_files/ex3.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479207485906 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 56 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 56 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2537 " "Peak virtual memory: 2537 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479207488044 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:58:08 2016 " "Processing ended: Tue Nov 15 10:58:08 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479207488044 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Elapsed time: 00:00:31" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479207488044 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479207488044 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479207488044 ""}
diff --git a/part_1/ex3/db/ex3.hier_info b/part_1/ex3/db/ex3.hier_info new file mode 100644 index 0000000..04bebea --- /dev/null +++ b/part_1/ex3/db/ex3.hier_info @@ -0,0 +1,76 @@ +|ex3
+SW[0] => SW[0].IN1
+SW[1] => SW[1].IN1
+SW[2] => SW[2].IN1
+SW[3] => SW[3].IN1
+SW[4] => SW[4].IN1
+SW[5] => SW[5].IN1
+SW[6] => SW[6].IN1
+SW[7] => SW[7].IN1
+SW[8] => SW[8].IN1
+SW[9] => SW[9].IN1
+HEX0[0] << hex_to_7seg:SEG0.port0
+HEX0[1] << hex_to_7seg:SEG0.port0
+HEX0[2] << hex_to_7seg:SEG0.port0
+HEX0[3] << hex_to_7seg:SEG0.port0
+HEX0[4] << hex_to_7seg:SEG0.port0
+HEX0[5] << hex_to_7seg:SEG0.port0
+HEX0[6] << hex_to_7seg:SEG0.port0
+HEX1[0] << hex_to_7seg:SEG1.port0
+HEX1[1] << hex_to_7seg:SEG1.port0
+HEX1[2] << hex_to_7seg:SEG1.port0
+HEX1[3] << hex_to_7seg:SEG1.port0
+HEX1[4] << hex_to_7seg:SEG1.port0
+HEX1[5] << hex_to_7seg:SEG1.port0
+HEX1[6] << hex_to_7seg:SEG1.port0
+HEX2[0] << hex_to_7seg:SEG2.port0
+HEX2[1] << hex_to_7seg:SEG2.port0
+HEX2[2] << hex_to_7seg:SEG2.port0
+HEX2[3] << hex_to_7seg:SEG2.port0
+HEX2[4] << hex_to_7seg:SEG2.port0
+HEX2[5] << hex_to_7seg:SEG2.port0
+HEX2[6] << hex_to_7seg:SEG2.port0
+
+
+|ex3|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex3|hex_to_7seg:SEG1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex3|hex_to_7seg:SEG2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_1/ex3/db/ex3.hif b/part_1/ex3/db/ex3.hif Binary files differnew file mode 100644 index 0000000..8965f94 --- /dev/null +++ b/part_1/ex3/db/ex3.hif diff --git a/part_1/ex3/db/ex3.lpc.html b/part_1/ex3/db/ex3.lpc.html new file mode 100644 index 0000000..eb80eca --- /dev/null +++ b/part_1/ex3/db/ex3.lpc.html @@ -0,0 +1,66 @@ +<TABLE>
+<TR bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >7</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_1/ex3/db/ex3.lpc.rdb b/part_1/ex3/db/ex3.lpc.rdb Binary files differnew file mode 100644 index 0000000..98dd811 --- /dev/null +++ b/part_1/ex3/db/ex3.lpc.rdb diff --git a/part_1/ex3/db/ex3.lpc.txt b/part_1/ex3/db/ex3.lpc.txt new file mode 100644 index 0000000..d941493 --- /dev/null +++ b/part_1/ex3/db/ex3.lpc.txt @@ -0,0 +1,9 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG2 ; 4 ; 2 ; 0 ; 2 ; 7 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG1 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG0 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_1/ex3/db/ex3.map.ammdb b/part_1/ex3/db/ex3.map.ammdb Binary files differnew file mode 100644 index 0000000..174eb00 --- /dev/null +++ b/part_1/ex3/db/ex3.map.ammdb diff --git a/part_1/ex3/db/ex3.map.bpm b/part_1/ex3/db/ex3.map.bpm Binary files differnew file mode 100644 index 0000000..7627580 --- /dev/null +++ b/part_1/ex3/db/ex3.map.bpm diff --git a/part_1/ex3/db/ex3.map.cdb b/part_1/ex3/db/ex3.map.cdb Binary files differnew file mode 100644 index 0000000..057057b --- /dev/null +++ b/part_1/ex3/db/ex3.map.cdb diff --git a/part_1/ex3/db/ex3.map.hdb b/part_1/ex3/db/ex3.map.hdb Binary files differnew file mode 100644 index 0000000..373bc3e --- /dev/null +++ b/part_1/ex3/db/ex3.map.hdb diff --git a/part_1/ex3/db/ex3.map.kpt b/part_1/ex3/db/ex3.map.kpt Binary files differnew file mode 100644 index 0000000..2647172 --- /dev/null +++ b/part_1/ex3/db/ex3.map.kpt diff --git a/part_1/ex3/db/ex3.map.logdb b/part_1/ex3/db/ex3.map.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex3/db/ex3.map.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex3/db/ex3.map.qmsg b/part_1/ex3/db/ex3.map.qmsg new file mode 100644 index 0000000..b884819 --- /dev/null +++ b/part_1/ex3/db/ex3.map.qmsg @@ -0,0 +1,15 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479207444454 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479207444456 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 10:57:24 2016 " "Processing started: Tue Nov 15 10:57:24 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479207444456 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479207444456 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex3 -c ex3 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex3 -c ex3" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479207444456 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479207444969 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479207444969 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/VERI/part_1/ex3/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479207453487 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479207453487 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex3.v 1 1 " "Found 1 design units, including 1 entities, in source file ex3.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex3 " "Found entity 1: ex3" { } { { "ex3.v" "" { Text "H:/VERI/part_1/ex3/ex3.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479207453493 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479207453493 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex3 " "Elaborating entity \"ex3\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479207453548 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "ex3.v" "SEG0" { Text "H:/VERI/part_1/ex3/ex3.v" 9 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479207453574 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1479207454224 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" { } { { "ex3.v" "" { Text "H:/VERI/part_1/ex3/ex3.v" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479207454264 "|ex3|HEX2[1]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1479207454264 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479207454344 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479207454964 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479207454964 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "48 " "Implemented 48 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479207455387 ""} { "Info" "ICUT_CUT_TM_OPINS" "21 " "Implemented 21 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479207455387 ""} { "Info" "ICUT_CUT_TM_LCELLS" "17 " "Implemented 17 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479207455387 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479207455387 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "881 " "Peak virtual memory: 881 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479207455501 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:57:35 2016 " "Processing ended: Tue Nov 15 10:57:35 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479207455501 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479207455501 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479207455501 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479207455501 ""}
diff --git a/part_1/ex3/db/ex3.map.rdb b/part_1/ex3/db/ex3.map.rdb Binary files differnew file mode 100644 index 0000000..c4a4cfa --- /dev/null +++ b/part_1/ex3/db/ex3.map.rdb diff --git a/part_1/ex3/db/ex3.map_bb.cdb b/part_1/ex3/db/ex3.map_bb.cdb Binary files differnew file mode 100644 index 0000000..efa5223 --- /dev/null +++ b/part_1/ex3/db/ex3.map_bb.cdb diff --git a/part_1/ex3/db/ex3.map_bb.hdb b/part_1/ex3/db/ex3.map_bb.hdb Binary files differnew file mode 100644 index 0000000..0104472 --- /dev/null +++ b/part_1/ex3/db/ex3.map_bb.hdb diff --git a/part_1/ex3/db/ex3.map_bb.logdb b/part_1/ex3/db/ex3.map_bb.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex3/db/ex3.map_bb.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex3/db/ex3.pre_map.cdb b/part_1/ex3/db/ex3.pre_map.cdb Binary files differnew file mode 100644 index 0000000..e3efa93 --- /dev/null +++ b/part_1/ex3/db/ex3.pre_map.cdb diff --git a/part_1/ex3/db/ex3.pre_map.hdb b/part_1/ex3/db/ex3.pre_map.hdb Binary files differnew file mode 100644 index 0000000..9c4d52a --- /dev/null +++ b/part_1/ex3/db/ex3.pre_map.hdb diff --git a/part_1/ex3/db/ex3.root_partition.map.reg_db.cdb b/part_1/ex3/db/ex3.root_partition.map.reg_db.cdb Binary files differnew file mode 100644 index 0000000..0fc3b02 --- /dev/null +++ b/part_1/ex3/db/ex3.root_partition.map.reg_db.cdb diff --git a/part_1/ex3/db/ex3.routing.rdb b/part_1/ex3/db/ex3.routing.rdb Binary files differnew file mode 100644 index 0000000..96573d9 --- /dev/null +++ b/part_1/ex3/db/ex3.routing.rdb diff --git a/part_1/ex3/db/ex3.rtlv.hdb b/part_1/ex3/db/ex3.rtlv.hdb Binary files differnew file mode 100644 index 0000000..1693929 --- /dev/null +++ b/part_1/ex3/db/ex3.rtlv.hdb diff --git a/part_1/ex3/db/ex3.rtlv_sg.cdb b/part_1/ex3/db/ex3.rtlv_sg.cdb Binary files differnew file mode 100644 index 0000000..6f81d8a --- /dev/null +++ b/part_1/ex3/db/ex3.rtlv_sg.cdb diff --git a/part_1/ex3/db/ex3.rtlv_sg_swap.cdb b/part_1/ex3/db/ex3.rtlv_sg_swap.cdb Binary files differnew file mode 100644 index 0000000..7b481c7 --- /dev/null +++ b/part_1/ex3/db/ex3.rtlv_sg_swap.cdb diff --git a/part_1/ex3/db/ex3.sld_design_entry.sci b/part_1/ex3/db/ex3.sld_design_entry.sci Binary files differnew file mode 100644 index 0000000..92c1102 --- /dev/null +++ b/part_1/ex3/db/ex3.sld_design_entry.sci diff --git a/part_1/ex3/db/ex3.sld_design_entry_dsc.sci b/part_1/ex3/db/ex3.sld_design_entry_dsc.sci Binary files differnew file mode 100644 index 0000000..92c1102 --- /dev/null +++ b/part_1/ex3/db/ex3.sld_design_entry_dsc.sci diff --git a/part_1/ex3/db/ex3.smart_action.txt b/part_1/ex3/db/ex3.smart_action.txt new file mode 100644 index 0000000..437a63e --- /dev/null +++ b/part_1/ex3/db/ex3.smart_action.txt @@ -0,0 +1 @@ +DONE
diff --git a/part_1/ex3/db/ex3.sta.qmsg b/part_1/ex3/db/ex3.sta.qmsg new file mode 100644 index 0000000..255dfc1 --- /dev/null +++ b/part_1/ex3/db/ex3.sta.qmsg @@ -0,0 +1,61 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479207505013 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479207505015 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 10:58:24 2016 " "Processing started: Tue Nov 15 10:58:24 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479207505015 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207505015 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex3 -c ex3 " "Command: quartus_sta ex3 -c ex3" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207505016 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479207505140 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207505745 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207505745 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207505792 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207505792 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex3.sdc " "Synopsys Design Constraints File file not found: 'ex3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506462 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506464 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506465 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506466 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506467 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506471 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479207506474 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506526 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479207506550 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506551 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506630 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506655 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506683 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506712 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506739 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479207506772 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207506828 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207507386 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207507498 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207507499 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207507499 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207507499 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207507500 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207507550 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207507583 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207507612 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207507639 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207507662 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479207507691 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207508061 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207508504 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207508617 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207508617 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207508617 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207508617 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207508637 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207508886 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207508912 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207508937 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207508959 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479207508986 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207509378 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207509378 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207509379 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207509380 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207509402 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207509421 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207509445 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207509468 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207509490 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207512115 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207512117 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1175 " "Peak virtual memory: 1175 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479207512751 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:58:32 2016 " "Processing ended: Tue Nov 15 10:58:32 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479207512751 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479207512751 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479207512751 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479207512751 ""}
diff --git a/part_1/ex3/db/ex3.sta.rdb b/part_1/ex3/db/ex3.sta.rdb Binary files differnew file mode 100644 index 0000000..9895bbb --- /dev/null +++ b/part_1/ex3/db/ex3.sta.rdb diff --git a/part_1/ex3/db/ex3.sta_cmp.6_slow_1100mv_85c.tdb b/part_1/ex3/db/ex3.sta_cmp.6_slow_1100mv_85c.tdb Binary files differnew file mode 100644 index 0000000..b1e8111 --- /dev/null +++ b/part_1/ex3/db/ex3.sta_cmp.6_slow_1100mv_85c.tdb diff --git a/part_1/ex3/db/ex3.tis_db_list.ddb b/part_1/ex3/db/ex3.tis_db_list.ddb Binary files differnew file mode 100644 index 0000000..88225e8 --- /dev/null +++ b/part_1/ex3/db/ex3.tis_db_list.ddb diff --git a/part_1/ex3/db/ex3.tiscmp.fast_1100mv_0c.ddb b/part_1/ex3/db/ex3.tiscmp.fast_1100mv_0c.ddb Binary files differnew file mode 100644 index 0000000..2469bd3 --- /dev/null +++ b/part_1/ex3/db/ex3.tiscmp.fast_1100mv_0c.ddb diff --git a/part_1/ex3/db/ex3.tiscmp.fast_1100mv_85c.ddb b/part_1/ex3/db/ex3.tiscmp.fast_1100mv_85c.ddb Binary files differnew file mode 100644 index 0000000..a59681f --- /dev/null +++ b/part_1/ex3/db/ex3.tiscmp.fast_1100mv_85c.ddb diff --git a/part_1/ex3/db/ex3.tiscmp.slow_1100mv_0c.ddb b/part_1/ex3/db/ex3.tiscmp.slow_1100mv_0c.ddb Binary files differnew file mode 100644 index 0000000..8d8d10a --- /dev/null +++ b/part_1/ex3/db/ex3.tiscmp.slow_1100mv_0c.ddb diff --git a/part_1/ex3/db/ex3.tiscmp.slow_1100mv_85c.ddb b/part_1/ex3/db/ex3.tiscmp.slow_1100mv_85c.ddb Binary files differnew file mode 100644 index 0000000..3420858 --- /dev/null +++ b/part_1/ex3/db/ex3.tiscmp.slow_1100mv_85c.ddb diff --git a/part_1/ex3/db/ex3.vpr.ammdb b/part_1/ex3/db/ex3.vpr.ammdb Binary files differnew file mode 100644 index 0000000..990d148 --- /dev/null +++ b/part_1/ex3/db/ex3.vpr.ammdb diff --git a/part_1/ex3/db/ex3_partition_pins.json b/part_1/ex3/db/ex3_partition_pins.json new file mode 100644 index 0000000..6a62ba7 --- /dev/null +++ b/part_1/ex3/db/ex3_partition_pins.json @@ -0,0 +1,129 @@ +{
+ "partitions" : [
+ {
+ "name" : "Top",
+ "pins" : [
+ {
+ "name" : "HEX0[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[6]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[0]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[1]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[2]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[3]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[4]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[5]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[6]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[7]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[8]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[9]",
+ "strict" : false
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file diff --git a/part_1/ex3/db/prev_cmp_ex3.qmsg b/part_1/ex3/db/prev_cmp_ex3.qmsg new file mode 100644 index 0000000..044dc9d --- /dev/null +++ b/part_1/ex3/db/prev_cmp_ex3.qmsg @@ -0,0 +1,11 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479207426219 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Elaboration Quartus Prime " "Running Quartus Prime Analysis & Elaboration" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479207426221 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 10:57:05 2016 " "Processing started: Tue Nov 15 10:57:05 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479207426221 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479207426221 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex3 -c ex3 --analysis_and_elaboration " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex3 -c ex3 --analysis_and_elaboration" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479207426222 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479207426800 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479207426800 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/VERI/part_1/ex3/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479207435301 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1479207435301 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex3.v 1 1 " "Found 1 design units, including 1 entities, in source file ex3.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex3 " "Found entity 1: ex3" { } { { "ex3.v" "" { Text "H:/VERI/part_1/ex3/ex3.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479207435306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1479207435306 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex3 " "Elaborating entity \"ex3\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Design Software" 0 -1 1479207435337 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "ex3.v" "SEG0" { Text "H:/VERI/part_1/ex3/ex3.v" 9 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Design Software" 0 -1 1479207435386 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Design Software" 0 -1 1479207435668 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Elaboration 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Elaboration was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "833 " "Peak virtual memory: 833 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479207435793 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 10:57:15 2016 " "Processing ended: Tue Nov 15 10:57:15 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479207435793 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479207435793 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479207435793 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479207435793 ""}
diff --git a/part_1/ex3/ex3.qpf b/part_1/ex3/ex3.qpf new file mode 100644 index 0000000..25856d8 --- /dev/null +++ b/part_1/ex3/ex3.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 10:48:26 November 15, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.0"
+DATE = "10:48:26 November 15, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ex3"
diff --git a/part_1/ex3/ex3.qsf b/part_1/ex3/ex3.qsf new file mode 100644 index 0000000..a2b75a0 --- /dev/null +++ b/part_1/ex3/ex3.qsf @@ -0,0 +1,267 @@ +#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 10:48:27 November 15, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# ex3_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex3
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:48:27 NOVEMBER 15, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE ex3.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/part_1/ex3/ex3.qsf.bak b/part_1/ex3/ex3.qsf.bak new file mode 100644 index 0000000..b79cf74 --- /dev/null +++ b/part_1/ex3/ex3.qsf.bak @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 10:48:27 November 15, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# ex3_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex3
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:48:27 NOVEMBER 15, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE ex3.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/part_1/ex3/ex3.qws b/part_1/ex3/ex3.qws Binary files differnew file mode 100644 index 0000000..43e7acf --- /dev/null +++ b/part_1/ex3/ex3.qws diff --git a/part_1/ex3/ex3.v b/part_1/ex3/ex3.v new file mode 100644 index 0000000..abe7623 --- /dev/null +++ b/part_1/ex3/ex3.v @@ -0,0 +1,14 @@ +module ex3(SW,
+ HEX0, HEX1, HEX2);
+
+ input [9:0] SW;
+ output [6:0] HEX0;
+ output [6:0] HEX1;
+ output [6:0] HEX2;
+
+ hex_to_7seg SEG0 (HEX0, SW[3:0]);
+ hex_to_7seg SEG1 (HEX1, SW[7:4]);
+ hex_to_7seg SEG2 (HEX2, SW[9:8]);
+
+endmodule
+
\ No newline at end of file diff --git a/part_1/ex3/ex3.v.bak b/part_1/ex3/ex3.v.bak new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/part_1/ex3/ex3.v.bak diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.db_info b/part_1/ex3/incremental_db/compiled_partitions/ex3.db_info new file mode 100644 index 0000000..f16f208 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 15 10:55:52 2016
diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.ammdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.ammdb Binary files differnew file mode 100644 index 0000000..87d96f8 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.ammdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.cdb Binary files differnew file mode 100644 index 0000000..6575aa7 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.dfp b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.dfp Binary files differnew file mode 100644 index 0000000..b1c67d6 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.dfp diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hbdb.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hbdb.cdb Binary files differnew file mode 100644 index 0000000..99ad1bd --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hbdb.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hbdb.hdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hbdb.hdb Binary files differnew file mode 100644 index 0000000..1833a86 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hbdb.hdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hbdb.sig b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hdb Binary files differnew file mode 100644 index 0000000..acfbc4c --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.hdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.logdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.rcfdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.rcfdb Binary files differnew file mode 100644 index 0000000..b0ddde4 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.cmp.rcfdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.cdb Binary files differnew file mode 100644 index 0000000..9c468f6 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.dpi b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.dpi Binary files differnew file mode 100644 index 0000000..d372fed --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.dpi diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.cdb Binary files differnew file mode 100644 index 0000000..144a076 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.hb_info b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.hb_info Binary files differnew file mode 100644 index 0000000..8210c55 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.hb_info diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.hdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.hdb Binary files differnew file mode 100644 index 0000000..a0b0bbb --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.hdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.sig b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hdb Binary files differnew file mode 100644 index 0000000..626556d --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.hdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.kpt b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.kpt Binary files differnew file mode 100644 index 0000000..02f94f9 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.kpt diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.olf.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.olf.cdb Binary files differnew file mode 100644 index 0000000..2bb7f2b --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.olf.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.olm.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.olm.cdb Binary files differnew file mode 100644 index 0000000..2d85e41 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.olm.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.oln.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.oln.cdb Binary files differnew file mode 100644 index 0000000..0d7eb28 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.oln.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.opi b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.opi new file mode 100644 index 0000000..56a6051 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.opi @@ -0,0 +1 @@ +1
\ No newline at end of file diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.orf.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.orf.cdb Binary files differnew file mode 100644 index 0000000..2bb7f2b --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.orf.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.orm.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.orm.cdb Binary files differnew file mode 100644 index 0000000..4dcf4f0 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.orm.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.orn.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.orn.cdb Binary files differnew file mode 100644 index 0000000..314dfd7 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.map.orn.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.cdb Binary files differnew file mode 100644 index 0000000..9c468f6 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.hbdb.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.hbdb.cdb Binary files differnew file mode 100644 index 0000000..144a076 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.hbdb.cdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.hbdb.hdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.hbdb.hdb Binary files differnew file mode 100644 index 0000000..a0b0bbb --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.hbdb.hdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.hdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.hdb Binary files differnew file mode 100644 index 0000000..626556d --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.hdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.kpt b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.kpt Binary files differnew file mode 100644 index 0000000..02f94f9 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.root_partition.rrp.kpt diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.rrp.hdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.rrp.hdb Binary files differnew file mode 100644 index 0000000..5ffe117 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.rrp.hdb diff --git a/part_1/ex3/incremental_db/compiled_partitions/ex3.rrs.cdb b/part_1/ex3/incremental_db/compiled_partitions/ex3.rrs.cdb Binary files differnew file mode 100644 index 0000000..deb9e08 --- /dev/null +++ b/part_1/ex3/incremental_db/compiled_partitions/ex3.rrs.cdb diff --git a/part_1/ex3/output_files/ex3.asm.rpt b/part_1/ex3/output_files/ex3.asm.rpt new file mode 100644 index 0000000..6a0ba77 --- /dev/null +++ b/part_1/ex3/output_files/ex3.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for ex3
+Tue Nov 15 10:58:23 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: H:/VERI/part_1/ex3/output_files/ex3.sof
+ 6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Tue Nov 15 10:58:23 2016 ;
+; Revision Name ; ex3 ;
+; Top-level Entity Name ; ex3 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++-----------------------------------------+
+; Assembler Generated Files ;
++-----------------------------------------+
+; File Name ;
++-----------------------------------------+
+; H:/VERI/part_1/ex3/output_files/ex3.sof ;
++-----------------------------------------+
+
+
++-------------------------------------------------------------------+
+; Assembler Device Options: H:/VERI/part_1/ex3/output_files/ex3.sof ;
++----------------+--------------------------------------------------+
+; Option ; Setting ;
++----------------+--------------------------------------------------+
+; Device ; 5CSEMA5F31C6 ;
+; JTAG usercode ; 0x00AFC372 ;
+; Checksum ; 0x00AFC372 ;
++----------------+--------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 10:58:12 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex3 -c ex3
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 893 megabytes
+ Info: Processing ended: Tue Nov 15 10:58:23 2016
+ Info: Elapsed time: 00:00:11
+ Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_1/ex3/output_files/ex3.done b/part_1/ex3/output_files/ex3.done new file mode 100644 index 0000000..79269a0 --- /dev/null +++ b/part_1/ex3/output_files/ex3.done @@ -0,0 +1 @@ +Tue Nov 15 10:58:34 2016
diff --git a/part_1/ex3/output_files/ex3.fit.rpt b/part_1/ex3/output_files/ex3.fit.rpt new file mode 100644 index 0000000..0928c30 --- /dev/null +++ b/part_1/ex3/output_files/ex3.fit.rpt @@ -0,0 +1,1958 @@ +Fitter report for ex3
+Tue Nov 15 10:58:05 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. I/O Assignment Warnings
+ 6. Ignored Assignments
+ 7. Incremental Compilation Preservation Summary
+ 8. Incremental Compilation Partition Settings
+ 9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Routing Usage Summary
+ 21. I/O Rules Summary
+ 22. I/O Rules Details
+ 23. I/O Rules Matrix
+ 24. Fitter Device Options
+ 25. Operating Settings and Conditions
+ 26. Fitter Messages
+ 27. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status ; Successful - Tue Nov 15 10:58:05 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex3 ;
+; Top-level Entity Name ; ex3 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 9 / 32,070 ( < 1 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 31 / 457 ( 7 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total RAM Blocks ; 0 / 397 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
+; Optimize Hold Timing ; All Paths ; All Paths ;
+; Optimize Multi-Corner Timing ; On ; On ;
+; Auto RAM to MLAB Conversion ; On ; On ;
+; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
+; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
+; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
+; SSN Optimization ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
+; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification ; Auto ; Auto ;
+; Enable Beneficial Skew Optimization ; On ; On ;
+; Optimize Design for Metastability ; On ; On ;
+; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+; Clamping Diode ; Off ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
+; Advanced Physical Optimization ; On ; On ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.1% ;
+; Processor 3 ; 0.1% ;
+; Processor 4 ; 0.1% ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings ;
++----------+--------------------------------------+
+; Pin Name ; Reason ;
++----------+--------------------------------------+
+; HEX0[0] ; Missing drive strength and slew rate ;
+; HEX0[1] ; Missing drive strength and slew rate ;
+; HEX0[2] ; Missing drive strength and slew rate ;
+; HEX0[3] ; Missing drive strength and slew rate ;
+; HEX0[4] ; Missing drive strength and slew rate ;
+; HEX0[5] ; Missing drive strength and slew rate ;
+; HEX0[6] ; Missing drive strength and slew rate ;
+; HEX1[0] ; Missing drive strength and slew rate ;
+; HEX1[1] ; Missing drive strength and slew rate ;
+; HEX1[2] ; Missing drive strength and slew rate ;
+; HEX1[3] ; Missing drive strength and slew rate ;
+; HEX1[4] ; Missing drive strength and slew rate ;
+; HEX1[5] ; Missing drive strength and slew rate ;
+; HEX1[6] ; Missing drive strength and slew rate ;
+; HEX2[0] ; Missing drive strength and slew rate ;
+; HEX2[1] ; Missing drive strength and slew rate ;
+; HEX2[2] ; Missing drive strength and slew rate ;
+; HEX2[3] ; Missing drive strength and slew rate ;
+; HEX2[4] ; Missing drive strength and slew rate ;
+; HEX2[5] ; Missing drive strength and slew rate ;
+; HEX2[6] ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location ; ; ; ADC_CS ; PIN_AG20 ; QSF Assignment ;
+; Location ; ; ; ADC_SCK ; PIN_AF21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDI ; PIN_AG21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDO ; PIN_AJ21 ; QSF Assignment ;
+; Location ; ; ; CLOCK_50 ; PIN_AF14 ; QSF Assignment ;
+; Location ; ; ; DAC_CS ; PIN_AD20 ; QSF Assignment ;
+; Location ; ; ; DAC_LD ; PIN_AK21 ; QSF Assignment ;
+; Location ; ; ; DAC_SCK ; PIN_AF20 ; QSF Assignment ;
+; Location ; ; ; DAC_SDI ; PIN_AG18 ; QSF Assignment ;
+; Location ; ; ; HEX3[0] ; PIN_AD26 ; QSF Assignment ;
+; Location ; ; ; HEX3[1] ; PIN_AC27 ; QSF Assignment ;
+; Location ; ; ; HEX3[2] ; PIN_AD25 ; QSF Assignment ;
+; Location ; ; ; HEX3[3] ; PIN_AC25 ; QSF Assignment ;
+; Location ; ; ; HEX3[4] ; PIN_AB28 ; QSF Assignment ;
+; Location ; ; ; HEX3[5] ; PIN_AB25 ; QSF Assignment ;
+; Location ; ; ; HEX3[6] ; PIN_AB22 ; QSF Assignment ;
+; Location ; ; ; HEX4[0] ; PIN_AA24 ; QSF Assignment ;
+; Location ; ; ; HEX4[1] ; PIN_Y23 ; QSF Assignment ;
+; Location ; ; ; HEX4[2] ; PIN_Y24 ; QSF Assignment ;
+; Location ; ; ; HEX4[3] ; PIN_W22 ; QSF Assignment ;
+; Location ; ; ; HEX4[4] ; PIN_W24 ; QSF Assignment ;
+; Location ; ; ; HEX4[5] ; PIN_V23 ; QSF Assignment ;
+; Location ; ; ; HEX4[6] ; PIN_W25 ; QSF Assignment ;
+; Location ; ; ; HEX5[0] ; PIN_V25 ; QSF Assignment ;
+; Location ; ; ; HEX5[1] ; PIN_AA28 ; QSF Assignment ;
+; Location ; ; ; HEX5[2] ; PIN_Y27 ; QSF Assignment ;
+; Location ; ; ; HEX5[3] ; PIN_AB27 ; QSF Assignment ;
+; Location ; ; ; HEX5[4] ; PIN_AB26 ; QSF Assignment ;
+; Location ; ; ; HEX5[5] ; PIN_AA26 ; QSF Assignment ;
+; Location ; ; ; HEX5[6] ; PIN_AA25 ; QSF Assignment ;
+; Location ; ; ; KEY[0] ; PIN_AA14 ; QSF Assignment ;
+; Location ; ; ; KEY[1] ; PIN_AA15 ; QSF Assignment ;
+; Location ; ; ; KEY[2] ; PIN_W15 ; QSF Assignment ;
+; Location ; ; ; KEY[3] ; PIN_Y16 ; QSF Assignment ;
+; Location ; ; ; LEDR[0] ; PIN_V16 ; QSF Assignment ;
+; Location ; ; ; LEDR[1] ; PIN_W16 ; QSF Assignment ;
+; Location ; ; ; LEDR[2] ; PIN_V17 ; QSF Assignment ;
+; Location ; ; ; LEDR[3] ; PIN_V18 ; QSF Assignment ;
+; Location ; ; ; LEDR[4] ; PIN_W17 ; QSF Assignment ;
+; Location ; ; ; LEDR[5] ; PIN_W19 ; QSF Assignment ;
+; Location ; ; ; LEDR[6] ; PIN_Y19 ; QSF Assignment ;
+; Location ; ; ; LEDR[7] ; PIN_W20 ; QSF Assignment ;
+; Location ; ; ; LEDR[8] ; PIN_W21 ; QSF Assignment ;
+; Location ; ; ; LEDR[9] ; PIN_Y21 ; QSF Assignment ;
+; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ;
+; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ;
+; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ;
+; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ;
+; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ;
+; Location ; ; ; PWM_OUT ; PIN_AJ20 ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; ADC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; ADC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; ADC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; ADC_SDO ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; CLOCK_50 ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; DAC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; DAC_LD ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; DAC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; DAC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX3[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX3[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX3[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX3[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX3[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX3[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX3[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX4[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX4[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX4[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX4[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX4[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX4[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX4[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; KEY[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; KEY[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; KEY[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; KEY[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; LEDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; LEDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; LEDR[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; LEDR[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; LEDR[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; LEDR[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; LEDR[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; LEDR[7] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; LEDR[8] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; LEDR[9] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex3 ; ; PWM_OUT ; 3.3-V LVTTL ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Placement (by node) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 80 ) ; 0.00 % ( 0 / 80 ) ; 0.00 % ( 0 / 80 ) ;
+; -- Achieved ; 0.00 % ( 0 / 80 ) ; 0.00 % ( 0 / 80 ) ; 0.00 % ( 0 / 80 ) ;
+; ; ; ; ;
+; Routing (by net) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
+; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
++---------------------+-------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top ; 0.00 % ( 0 / 80 ) ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in H:/VERI/part_1/ex3/output_files/ex3.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource ; Usage ; % ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 9 / 32,070 ; < 1 % ;
+; ALMs needed [=A-B+C] ; 9 ; ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 9 / 32,070 ; < 1 % ;
+; [a] ALMs used for LUT logic and registers ; 0 ; ;
+; [b] ALMs used for LUT logic ; 9 ; ;
+; [c] ALMs used for registers ; 0 ; ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
+; [B] Estimate of ALMs recoverable by dense packing ; 0 / 32,070 ; 0 % ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ;
+; [a] Due to location constrained logic ; 0 ; ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; ;
+; [c] Due to LAB input limits ; 0 ; ;
+; [d] Due to virtual I/Os ; 0 ; ;
+; ; ; ;
+; Difficulty packing design ; Low ; ;
+; ; ; ;
+; Total LABs: partially or completely used ; 3 / 3,207 ; < 1 % ;
+; -- Logic LABs ; 3 ; ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 18 ; ;
+; -- 7 input functions ; 0 ; ;
+; -- 6 input functions ; 0 ; ;
+; -- 5 input functions ; 0 ; ;
+; -- 4 input functions ; 14 ; ;
+; -- <=3 input functions ; 4 ; ;
+; Combinational ALUT usage for route-throughs ; 0 ; ;
+; Dedicated logic registers ; 0 ; ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 0 / 64,140 ; 0 % ;
+; -- Secondary logic registers ; 0 / 64,140 ; 0 % ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 0 ; ;
+; -- Routing optimization registers ; 0 ; ;
+; ; ; ;
+; Virtual pins ; 0 ; ;
+; I/O pins ; 31 / 457 ; 7 % ;
+; -- Clock pins ; 0 / 8 ; 0 % ;
+; -- Dedicated input pins ; 0 / 21 ; 0 % ;
+; ; ; ;
+; Hard processor system peripheral utilization ; ; ;
+; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
+; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
+; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
+; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
+; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
+; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
+; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
+; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
+; -- JTAG ; 0 / 1 ( 0 % ) ; ;
+; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
+; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
+; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
+; -- STM event ; 0 / 1 ( 0 % ) ; ;
+; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
+; -- DMA ; 0 / 1 ( 0 % ) ; ;
+; -- CAN ; 0 / 2 ( 0 % ) ; ;
+; -- EMAC ; 0 / 2 ( 0 % ) ; ;
+; -- I2C ; 0 / 4 ( 0 % ) ; ;
+; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
+; -- QSPI ; 0 / 1 ( 0 % ) ; ;
+; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
+; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
+; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
+; -- UART ; 0 / 2 ( 0 % ) ; ;
+; -- USB ; 0 / 2 ( 0 % ) ; ;
+; ; ; ;
+; Global signals ; 0 ; ;
+; M10K blocks ; 0 / 397 ; 0 % ;
+; Total MLAB memory bits ; 0 ; ;
+; Total block memory bits ; 0 / 4,065,280 ; 0 % ;
+; Total block memory implementation bits ; 0 / 4,065,280 ; 0 % ;
+; ; ; ;
+; Total DSP Blocks ; 0 / 87 ; 0 % ;
+; ; ; ;
+; Fractional PLLs ; 0 / 6 ; 0 % ;
+; Global clocks ; 0 / 16 ; 0 % ;
+; Quadrant clocks ; 0 / 66 ; 0 % ;
+; Horizontal periphery clocks ; 0 / 18 ; 0 % ;
+; SERDES Transmitters ; 0 / 100 ; 0 % ;
+; SERDES Receivers ; 0 / 100 ; 0 % ;
+; JTAGs ; 0 / 1 ; 0 % ;
+; ASMI blocks ; 0 / 1 ; 0 % ;
+; CRC blocks ; 0 / 1 ; 0 % ;
+; Remote update blocks ; 0 / 1 ; 0 % ;
+; Oscillator blocks ; 0 / 1 ; 0 % ;
+; Impedance control blocks ; 0 / 4 ; 0 % ;
+; Hard Memory Controllers ; 0 / 2 ; 0 % ;
+; Average interconnect usage (total/H/V) ; 0.0% / 0.1% / 0.0% ; ;
+; Peak interconnect usage (total/H/V) ; 0.4% / 0.3% / 0.7% ; ;
+; Maximum fan-out ; 7 ; ;
+; Highest non-global fan-out ; 7 ; ;
+; Total fan-out ; 113 ; ;
+; Average fan-out ; 1.41 ; ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+; Statistic ; Top ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 9 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; ALMs needed [=A-B+C] ; 9 ; 0 ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 9 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] ALMs used for LUT logic and registers ; 0 ; 0 ;
+; [b] ALMs used for LUT logic ; 9 ; 0 ;
+; [c] ALMs used for registers ; 0 ; 0 ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
+; [B] Estimate of ALMs recoverable by dense packing ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] Due to location constrained logic ; 0 ; 0 ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
+; [c] Due to LAB input limits ; 0 ; 0 ;
+; [d] Due to virtual I/Os ; 0 ; 0 ;
+; ; ; ;
+; Difficulty packing design ; Low ; Low ;
+; ; ; ;
+; Total LABs: partially or completely used ; 3 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ;
+; -- Logic LABs ; 3 ; 0 ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 18 ; 0 ;
+; -- 7 input functions ; 0 ; 0 ;
+; -- 6 input functions ; 0 ; 0 ;
+; -- 5 input functions ; 0 ; 0 ;
+; -- 4 input functions ; 14 ; 0 ;
+; -- <=3 input functions ; 4 ; 0 ;
+; Combinational ALUT usage for route-throughs ; 0 ; 0 ;
+; Memory ALUT usage ; 0 ; 0 ;
+; -- 64-address deep ; 0 ; 0 ;
+; -- 32-address deep ; 0 ; 0 ;
+; ; ; ;
+; Dedicated logic registers ; 0 ; 0 ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 0 / 64140 ( 0 % ) ; 0 / 64140 ( 0 % ) ;
+; -- Secondary logic registers ; 0 / 64140 ( 0 % ) ; 0 / 64140 ( 0 % ) ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 0 ; 0 ;
+; -- Routing optimization registers ; 0 ; 0 ;
+; ; ; ;
+; ; ; ;
+; Virtual pins ; 0 ; 0 ;
+; I/O pins ; 31 ; 0 ;
+; I/O registers ; 0 ; 0 ;
+; Total block memory bits ; 0 ; 0 ;
+; Total block memory implementation bits ; 0 ; 0 ;
+; ; ; ;
+; Connections ; ; ;
+; -- Input Connections ; 0 ; 0 ;
+; -- Registered Input Connections ; 0 ; 0 ;
+; -- Output Connections ; 0 ; 0 ;
+; -- Registered Output Connections ; 0 ; 0 ;
+; ; ; ;
+; Internal Connections ; ; ;
+; -- Total Connections ; 113 ; 0 ;
+; -- Registered Connections ; 0 ; 0 ;
+; ; ; ;
+; External Connections ; ; ;
+; -- Top ; 0 ; 0 ;
+; -- hard_block:auto_generated_inst ; 0 ; 0 ;
+; ; ; ;
+; Partition Interface ; ; ;
+; -- Input Ports ; 10 ; 0 ;
+; -- Output Ports ; 21 ; 0 ;
+; -- Bidir Ports ; 0 ; 0 ;
+; ; ; ;
+; Registered Ports ; ; ;
+; -- Registered Input Ports ; 0 ; 0 ;
+; -- Registered Output Ports ; 0 ; 0 ;
+; ; ; ;
+; Port Connectivity ; ; ;
+; -- Input Ports driven by GND ; 0 ; 0 ;
+; -- Output Ports driven by GND ; 0 ; 0 ;
+; -- Input Ports driven by VCC ; 0 ; 0 ;
+; -- Output Ports driven by VCC ; 0 ; 0 ;
+; -- Input Ports with no Source ; 0 ; 0 ;
+; -- Output Ports with no Source ; 0 ; 0 ;
+; -- Input Ports with no Fanout ; 0 ; 0 ;
+; -- Output Ports with no Fanout ; 0 ; 0 ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; SW[0] ; AB12 ; 3A ; 12 ; 0 ; 17 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[1] ; AC12 ; 3A ; 16 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[2] ; AF9 ; 3A ; 8 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[3] ; AF10 ; 3A ; 4 ; 0 ; 51 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[4] ; AD11 ; 3A ; 2 ; 0 ; 40 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[5] ; AD12 ; 3A ; 16 ; 0 ; 17 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[6] ; AE11 ; 3A ; 4 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[7] ; AC9 ; 3A ; 4 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[8] ; AD10 ; 3A ; 4 ; 0 ; 17 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[9] ; AE12 ; 3A ; 2 ; 0 ; 57 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[0] ; AJ29 ; 5A ; 89 ; 6 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[1] ; AH29 ; 5A ; 89 ; 6 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[2] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[3] ; AG30 ; 5A ; 89 ; 16 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[4] ; AF29 ; 5A ; 89 ; 15 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[5] ; AF30 ; 5A ; 89 ; 15 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[6] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[0] ; AB23 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[1] ; AE29 ; 5B ; 89 ; 23 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[2] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[3] ; AC28 ; 5B ; 89 ; 20 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[4] ; AD30 ; 5B ; 89 ; 25 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[5] ; AC29 ; 5B ; 89 ; 20 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[6] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; 3A ; 10 / 32 ( 31 % ) ; 3.3V ; -- ; 3.3V ;
+; 3B ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 5A ; 15 / 32 ( 47 % ) ; 3.3V ; -- ; 3.3V ;
+; 5B ; 6 / 16 ( 38 % ) ; 3.3V ; -- ; 3.3V ;
+; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
+; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
+; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA14 ; 122 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA15 ; 120 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA27 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB12 ; 72 ; 3A ; SW[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB14 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB22 ; 225 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB23 ; 227 ; 5A ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB25 ; 230 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB28 ; 249 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC9 ; 58 ; 3A ; SW[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AC10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC11 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC12 ; 82 ; 3A ; SW[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC21 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AC25 ; 215 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC27 ; 242 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC28 ; 245 ; 5B ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC29 ; 247 ; 5B ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC30 ; 259 ; 5B ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD8 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD10 ; 56 ; 3A ; SW[8] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AD11 ; 54 ; 3A ; SW[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AD12 ; 80 ; 3A ; SW[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AD13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD25 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD26 ; 240 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD27 ; 222 ; 5A ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD29 ; 255 ; 5B ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD30 ; 257 ; 5B ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE11 ; 59 ; 3A ; SW[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AE12 ; 52 ; 3A ; SW[9] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE15 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE25 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE29 ; 253 ; 5B ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE30 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF7 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF9 ; 67 ; 3A ; SW[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AF10 ; 57 ; 3A ; SW[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF14 ; 114 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AF29 ; 237 ; 5A ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AF30 ; 239 ; 5A ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG4 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG30 ; 243 ; 5A ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH26 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH29 ; 218 ; 5A ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH30 ; 241 ; 5A ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ29 ; 216 ; 5A ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
+; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
+; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
+; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
+; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
+; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
+; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
+; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
+; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
+; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
+; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
+; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
+; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
+; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
+; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
+; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U23 ; ; 5B ; VCCPD5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V16 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V18 ; 194 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W15 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W16 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W17 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W19 ; 192 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W20 ; 217 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W21 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y16 ; 128 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y19 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y21 ; 219 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; Y23 ; 232 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------+-------------+--------------+
+; |ex3 ; 9.0 (0.5) ; 9.0 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 18 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 31 ; 0 ; |ex3 ; ex3 ; work ;
+; |hex_to_7seg:SEG0| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex3|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG1| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex3|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG2| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex3|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; SW[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[6] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[7] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[8] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[9] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++------------------------------------+-------------------+---------+
+; SW[0] ; ; ;
+; - hex_to_7seg:SEG0|WideOr6~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr5~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr4~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr3~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr2~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr1~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr0~0 ; 0 ; 0 ;
+; SW[1] ; ; ;
+; - hex_to_7seg:SEG0|WideOr6~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr5~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr4~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr3~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr2~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr1~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr0~0 ; 0 ; 0 ;
+; SW[2] ; ; ;
+; - hex_to_7seg:SEG0|WideOr6~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr5~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr4~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr3~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr2~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr1~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr0~0 ; 0 ; 0 ;
+; SW[3] ; ; ;
+; - hex_to_7seg:SEG0|WideOr6~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr5~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr4~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr3~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr2~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr1~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG0|WideOr0~0 ; 1 ; 0 ;
+; SW[4] ; ; ;
+; - hex_to_7seg:SEG1|WideOr6~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr5~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr4~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr3~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr2~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr1~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr0~0 ; 1 ; 0 ;
+; SW[5] ; ; ;
+; - hex_to_7seg:SEG1|WideOr6~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr5~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr4~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr3~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr2~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr1~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr0~0 ; 1 ; 0 ;
+; SW[6] ; ; ;
+; - hex_to_7seg:SEG1|WideOr6~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr5~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr4~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr3~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr2~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr1~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr0~0 ; 1 ; 0 ;
+; SW[7] ; ; ;
+; - hex_to_7seg:SEG1|WideOr6~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr5~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr4~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr3~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr2~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr1~0 ; 0 ; 0 ;
+; - hex_to_7seg:SEG1|WideOr0~0 ; 0 ; 0 ;
+; SW[8] ; ; ;
+; - hex_to_7seg:SEG2|Decoder0~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG2|Decoder0~1 ; 1 ; 0 ;
+; - hex_to_7seg:SEG2|Decoder0~2 ; 1 ; 0 ;
+; - HEX2[4]~output ; 1 ; 0 ;
+; SW[9] ; ; ;
+; - hex_to_7seg:SEG2|Decoder0~0 ; 1 ; 0 ;
+; - hex_to_7seg:SEG2|Decoder0~1 ; 1 ; 0 ;
+; - hex_to_7seg:SEG2|Decoder0~2 ; 1 ; 0 ;
+; - HEX2[6]~output ; 1 ; 0 ;
++------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------+
+; Routing Usage Summary ;
++---------------------------------------------+------------------------+
+; Routing Resource Type ; Usage ;
++---------------------------------------------+------------------------+
+; Block interconnects ; 31 / 289,320 ( < 1 % ) ;
+; C12 interconnects ; 13 / 13,420 ( < 1 % ) ;
+; C2 interconnects ; 15 / 119,108 ( < 1 % ) ;
+; C4 interconnects ; 29 / 56,300 ( < 1 % ) ;
+; DQS bus muxes ; 0 / 25 ( 0 % ) ;
+; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
+; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
+; Direct links ; 0 / 289,320 ( 0 % ) ;
+; Global clocks ; 0 / 16 ( 0 % ) ;
+; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
+; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
+; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
+; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
+; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
+; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
+; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
+; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
+; Local interconnects ; 0 / 84,580 ( 0 % ) ;
+; Quadrant clocks ; 0 / 66 ( 0 % ) ;
+; R14 interconnects ; 57 / 12,676 ( < 1 % ) ;
+; R14/C12 interconnect drivers ; 60 / 20,720 ( < 1 % ) ;
+; R3 interconnects ; 15 / 130,992 ( < 1 % ) ;
+; R6 interconnects ; 18 / 266,960 ( < 1 % ) ;
+; Spine clocks ; 0 / 360 ( 0 % ) ;
+; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
++---------------------------------------------+------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary ;
++----------------------------------+-------+
+; I/O Rules Statistic ; Total ;
++----------------------------------+-------+
+; Total I/O Rules ; 28 ;
+; Number of I/O Rules Passed ; 6 ;
+; Number of I/O Rules Failed ; 0 ;
+; Number of I/O Rules Unchecked ; 0 ;
+; Number of I/O Rules Inapplicable ; 22 ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
+; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
+; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
+; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass ; 31 ; 0 ; 31 ; 0 ; 0 ; 31 ; 31 ; 0 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Inapplicable ; 0 ; 31 ; 0 ; 31 ; 31 ; 0 ; 0 ; 31 ; 0 ; 0 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ; 31 ;
+; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options ;
++------------------------------------------------------------------+-----------------------------+
+; Option ; Setting ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Passive Serial ;
+; Enable Error Detection CRC_ERROR pin ; Off ;
+; Enable CvP_CONFDONE pin ; Off ;
+; Enable open drain on CRC_ERROR pin ; On ;
+; Enable open drain on CvP_CONFDONE pin ; On ;
+; Enable open drain on INIT_DONE pin ; On ;
+; Enable open drain on Partial Reconfiguration pins ; Off ;
+; Enable open drain on nCEO pin ; On ;
+; Enable Partial Reconfiguration pins ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ;
+; Enable internal scrubbing ; Off ;
+; Active Serial clock source ; 100 MHz Internal Oscillator ;
+; Device initialization clock source ; Internal Oscillator ;
+; Configuration via Protocol ; Off ;
+; Configuration Voltage Level ; Auto ;
+; Force Configuration Voltage Level ; Off ;
+; Enable nCEO output ; Off ;
+; Data[15..8] ; Unreserved ;
+; Data[7..5] ; Unreserved ;
+; Base pin-out file on sameframe device ; Off ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.10 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex3"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (184020): Starting Fitter periphery placement operations
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+ Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+ Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
+Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info (170201): Optimizations that may affect the design's routability were skipped
+ Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (11888): Total time spent on timing analysis during the Fitter is 0.07 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file H:/VERI/part_1/ex3/output_files/ex3.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 56 warnings
+ Info: Peak virtual memory: 2537 megabytes
+ Info: Processing ended: Tue Nov 15 10:58:08 2016
+ Info: Elapsed time: 00:00:31
+ Info: Total CPU time (on all processors): 00:00:48
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in H:/VERI/part_1/ex3/output_files/ex3.fit.smsg.
+
+
diff --git a/part_1/ex3/output_files/ex3.fit.smsg b/part_1/ex3/output_files/ex3.fit.smsg new file mode 100644 index 0000000..43eead5 --- /dev/null +++ b/part_1/ex3/output_files/ex3.fit.smsg @@ -0,0 +1,6 @@ +Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_1/ex3/output_files/ex3.fit.summary b/part_1/ex3/output_files/ex3.fit.summary new file mode 100644 index 0000000..5ba8f31 --- /dev/null +++ b/part_1/ex3/output_files/ex3.fit.summary @@ -0,0 +1,20 @@ +Fitter Status : Successful - Tue Nov 15 10:58:05 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex3
+Top-level Entity Name : ex3
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 9 / 32,070 ( < 1 % )
+Total registers : 0
+Total pins : 31 / 457 ( 7 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_1/ex3/output_files/ex3.flow.rpt b/part_1/ex3/output_files/ex3.flow.rpt new file mode 100644 index 0000000..499e607 --- /dev/null +++ b/part_1/ex3/output_files/ex3.flow.rpt @@ -0,0 +1,128 @@ +Flow report for ex3
+Tue Nov 15 10:58:32 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+ 8. Flow Messages
+ 9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary ;
++---------------------------------+-------------------------------------------------+
+; Flow Status ; Successful - Tue Nov 15 10:58:23 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex3 ;
+; Top-level Entity Name ; ex3 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 9 / 32,070 ( < 1 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 31 / 457 ( 7 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 11/15/2016 10:57:24 ;
+; Main task ; Compilation ;
+; Revision Name ; ex3 ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 260248564170200.147920744408188 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
+; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 881 MB ; 00:00:22 ;
+; Fitter ; 00:00:28 ; 1.0 ; 2537 MB ; 00:00:47 ;
+; Assembler ; 00:00:11 ; 1.0 ; 892 MB ; 00:00:06 ;
+; TimeQuest Timing Analyzer ; 00:00:08 ; 1.0 ; 1175 MB ; 00:00:05 ;
+; Total ; 00:00:57 ; -- ; -- ; 00:01:20 ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; Fitter ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; Assembler ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; TimeQuest Timing Analyzer ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex3 -c ex3
+quartus_fit --read_settings_files=off --write_settings_files=off ex3 -c ex3
+quartus_asm --read_settings_files=off --write_settings_files=off ex3 -c ex3
+quartus_sta ex3 -c ex3
+
+
+
diff --git a/part_1/ex3/output_files/ex3.jdi b/part_1/ex3/output_files/ex3.jdi new file mode 100644 index 0000000..a471153 --- /dev/null +++ b/part_1/ex3/output_files/ex3.jdi @@ -0,0 +1,8 @@ +<sld_project_info>
+ <project>
+ <hash md5_digest_80b="f57abd042c86ee6b5942"/>
+ </project>
+ <file_info>
+ <file device="5CSEMA5F31C6" path="ex3.sof" usercode="0xFFFFFFFF"/>
+ </file_info>
+</sld_project_info>
diff --git a/part_1/ex3/output_files/ex3.map.rpt b/part_1/ex3/output_files/ex3.map.rpt new file mode 100644 index 0000000..56fed6f --- /dev/null +++ b/part_1/ex3/output_files/ex3.map.rpt @@ -0,0 +1,304 @@ +Analysis & Synthesis report for ex3
+Tue Nov 15 10:57:35 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Source Files Read
+ 6. Analysis & Synthesis Resource Usage Summary
+ 7. Analysis & Synthesis Resource Utilization by Entity
+ 8. General Register Statistics
+ 9. Port Connectivity Checks: "hex_to_7seg:SEG2"
+ 10. Post-Synthesis Netlist Statistics for Top Partition
+ 11. Elapsed Time Per Partition
+ 12. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Tue Nov 15 10:57:35 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex3 ;
+; Top-level Entity Name ; ex3 ;
+; Family ; Cyclone V ;
+; Logic utilization (in ALMs) ; N/A ;
+; Total registers ; 0 ;
+; Total pins ; 31 ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 ;
+; Total DSP Blocks ; 0 ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Top-level entity name ; ex3 ; ex3 ;
+; Family name ; Cyclone V ; Cyclone V ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Infer RAMs from Raw Logic ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; On ; On ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 3 ; 3 ;
+; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
+; Synthesis Seed ; 1 ; 1 ;
+; Automatic Parallel Synthesis ; On ; On ;
+; Partial Reconfiguration Bitstream ID ; Off ; Off ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 1 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------+------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------+------------------------------------------------+---------+
+; verilog_files/hex_to_7seg.v ; yes ; User Verilog HDL File ; H:/VERI/part_1/ex3/verilog_files/hex_to_7seg.v ; ;
+; ex3.v ; yes ; User Verilog HDL File ; H:/VERI/part_1/ex3/ex3.v ; ;
++----------------------------------+-----------------+------------------------+------------------------------------------------+---------+
+
+
++-----------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+-------------+
+; Resource ; Usage ;
++---------------------------------------------+-------------+
+; Estimate of Logic utilization (ALMs needed) ; 9 ;
+; ; ;
+; Combinational ALUT usage for logic ; 17 ;
+; -- 7 input functions ; 0 ;
+; -- 6 input functions ; 0 ;
+; -- 5 input functions ; 0 ;
+; -- 4 input functions ; 14 ;
+; -- <=3 input functions ; 3 ;
+; ; ;
+; Dedicated logic registers ; 0 ;
+; ; ;
+; I/O pins ; 31 ;
+; ; ;
+; Total DSP Blocks ; 0 ;
+; ; ;
+; Maximum fan-out node ; SW[0]~input ;
+; Maximum fan-out ; 7 ;
+; Total fan-out ; 113 ;
+; Average fan-out ; 1.43 ;
++---------------------------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------+-------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------+-------------+--------------+
+; |ex3 ; 17 (0) ; 0 (0) ; 0 ; 0 ; 31 ; 0 ; |ex3 ; ex3 ; work ;
+; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex3|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex3|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG2| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex3|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 0 ;
+; Number of registers using Synchronous Clear ; 0 ;
+; Number of registers using Synchronous Load ; 0 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 0 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "hex_to_7seg:SEG2" ;
++------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------+
+; in ; Input ; Warning ; Input port expression (2 bits) is smaller than the input port (4 bits) it drives. Extra input bit(s) "in[3..2]" will be connected to GND. ;
++------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type ; Count ;
++-----------------------+-----------------------------+
+; arriav_lcell_comb ; 21 ;
+; normal ; 21 ;
+; 0 data inputs ; 1 ;
+; 1 data inputs ; 3 ;
+; 2 data inputs ; 3 ;
+; 4 data inputs ; 14 ;
+; boundary_port ; 31 ;
+; ; ;
+; Max LUT depth ; 2.00 ;
+; Average LUT depth ; 1.35 ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top ; 00:00:00 ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 10:57:24 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex3 -c ex3
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+ Info (12023): Found entity 1: hex_to_7seg File: H:/VERI/part_1/ex3/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file ex3.v
+ Info (12023): Found entity 1: ex3 File: H:/VERI/part_1/ex3/ex3.v Line: 1
+Info (12127): Elaborating entity "ex3" for the top level hierarchy
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/VERI/part_1/ex3/ex3.v Line: 9
+Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+ Warning (13410): Pin "HEX2[1]" is stuck at GND File: H:/VERI/part_1/ex3/ex3.v Line: 7
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+ Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 48 device resources after synthesis - the final resource count might be different
+ Info (21058): Implemented 10 input pins
+ Info (21059): Implemented 21 output pins
+ Info (21061): Implemented 17 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings
+ Info: Peak virtual memory: 881 megabytes
+ Info: Processing ended: Tue Nov 15 10:57:35 2016
+ Info: Elapsed time: 00:00:11
+ Info: Total CPU time (on all processors): 00:00:22
+
+
diff --git a/part_1/ex3/output_files/ex3.map.summary b/part_1/ex3/output_files/ex3.map.summary new file mode 100644 index 0000000..c91ca92 --- /dev/null +++ b/part_1/ex3/output_files/ex3.map.summary @@ -0,0 +1,17 @@ +Analysis & Synthesis Status : Successful - Tue Nov 15 10:57:35 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex3
+Top-level Entity Name : ex3
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 0
+Total pins : 31
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_1/ex3/output_files/ex3.pin b/part_1/ex3/output_files/ex3.pin new file mode 100644 index 0000000..38600b9 --- /dev/null +++ b/part_1/ex3/output_files/ex3.pin @@ -0,0 +1,976 @@ + -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other
+ -- applicable license agreement, including, without limitation,
+ -- that your use is for the sole purpose of programming logic
+ -- devices manufactured by Altera and sold by Altera or its
+ -- authorized distributors. Please refer to the applicable
+ -- agreement for further details.
+ --
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 3A: 3.3V
+ -- Bank 3B: 2.5V
+ -- Bank 4A: 2.5V
+ -- Bank 5A: 3.3V
+ -- Bank 5B: 3.3V
+ -- Bank 6B: 2.5V
+ -- Bank 6A: 2.5V
+ -- Bank 7A: 2.5V
+ -- Bank 7B: 2.5V
+ -- Bank 7C: 2.5V
+ -- Bank 7D: 2.5V
+ -- Bank 8A: 2.5V
+ -- RREF : External reference resistor for the quad, MUST be connected to
+ -- GND via a 2k Ohm resistor.
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
+ -- must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP "ex3" ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A :
+VCCIO8A : A7 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A :
+GND : A12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C :
+GND : A17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B :
+GND : A22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A :
+GND : A26 : : : : 7A :
+GND : A27 : gnd : : : :
+HPS_TRST : A28 : : : : 7A :
+HPS_TMS : A29 : : : : 7A :
+GND : AA1 : gnd : : : :
+GND : AA2 : gnd : : : :
+GND : AA3 : gnd : : : :
+GND : AA4 : gnd : : : :
+VCC : AA5 : power : : 1.1V : :
+GND : AA6 : gnd : : : :
+DNU : AA7 : : : : :
+VCCA_FPLL : AA8 : power : : 2.5V : :
+GND : AA9 : gnd : : : :
+VCCPD3A : AA10 : power : : 3.3V : 3A :
+GND : AA11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
+VCCIO4A : AA17 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
+GND : AA22 : gnd : : : :
+VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
+VCCIO5B : AA27 : power : : 3.3V : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 5B :
+VREFB5BN0 : AA29 : power : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B :
+GND : AB1 : gnd : : : :
+GND : AB2 : gnd : : : :
+DNU : AB3 : : : : :
+DNU : AB4 : : : : :
+GND : AB5 : gnd : : : :
+VCCA_FPLL : AB6 : power : : 2.5V : :
+GND : AB7 : gnd : : : :
+nCSO, DATA4 : AB8 : : : : 3A :
+TDO : AB9 : output : : : 3A :
+VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX : AB11 : power : : 2.5V : :
+SW[0] : AB12 : input : 3.3-V LVTTL : : 3A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B :
+VCCIO3B : AB14 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B :
+VCC_AUX : AB16 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
+VCCPD3B4A : AB18 : power : : 2.5V : 3B, 4A :
+GND : AB19 : gnd : : : :
+VCCPD3B4A : AB20 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 5A :
+HEX2[0] : AB23 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AB24 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28 : : : : 5B :
+GND : AB29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B :
+GND : AC1 : gnd : : : :
+GND : AC2 : gnd : : : :
+GND : AC3 : gnd : : : :
+GND : AC4 : gnd : : : :
+TCK : AC5 : input : : : 3A :
+GND : AC6 : gnd : : : :
+AS_DATA3, DATA3 : AC7 : : : : 3A :
+GND : AC8 : gnd : : : :
+SW[7] : AC9 : input : 3.3-V LVTTL : : 3A : Y
+VCCPD3A : AC10 : power : : 3.3V : 3A :
+VCCIO3A : AC11 : power : : 3.3V : 3A :
+SW[1] : AC12 : input : 3.3-V LVTTL : : 3A : Y
+VCCPD3B4A : AC13 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3B :
+VCCPD3B4A : AC15 : power : : 2.5V : 3B, 4A :
+GND : AC16 : gnd : : : :
+VCCPD3B4A : AC17 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
+VCCPD3B4A : AC19 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
+VCCIO4A : AC21 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
+VREFB5AN0 : AC24 : power : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5A :
+GND : AC26 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5A :
+HEX2[3] : AC28 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[5] : AC29 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[6] : AC30 : output : 3.3-V LVTTL : : 5B : Y
+GND : AD1 : gnd : : : :
+GND : AD2 : gnd : : : :
+DNU : AD3 : : : : :
+DNU : AD4 : : : : :
+GND : AD5 : gnd : : : :
+VREFB3AN0 : AD6 : power : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
+VCCIO3A : AD8 : power : : 3.3V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A :
+SW[8] : AD10 : input : 3.3-V LVTTL : : 3A : Y
+SW[4] : AD11 : input : 3.3-V LVTTL : : 3A : Y
+SW[5] : AD12 : input : 3.3-V LVTTL : : 3A : Y
+VCCIO3B : AD13 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B :
+DNU : AD15 : : : : :
+VCCPD3B4A : AD16 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
+VCCIO4A : AD18 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
+VCC_AUX : AD22 : power : : 2.5V : :
+GND : AD23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5A :
+HEX1[6] : AD27 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AD28 : power : : 3.3V : 5A :
+HEX2[2] : AD29 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[4] : AD30 : output : 3.3-V LVTTL : : 5B : Y
+GND : AE1 : gnd : : : :
+GND : AE2 : gnd : : : :
+GND : AE3 : gnd : : : :
+GND : AE4 : gnd : : : :
+AS_DATA1, DATA1 : AE5 : : : : 3A :
+AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3A :
+AS_DATA2, DATA2 : AE8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3A :
+GND : AE10 : gnd : : : :
+SW[6] : AE11 : input : 3.3-V LVTTL : : 3A : Y
+SW[9] : AE12 : input : 3.3-V LVTTL : : 3A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B :
+VCCIO3B : AE15 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
+GND : AE20 : gnd : : : :
+VCCPD3B4A : AE21 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
+VCCIO4A : AE25 : power : : 2.5V : 4A :
+HEX0[0] : AE26 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[1] : AE27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[2] : AE28 : output : 3.3-V LVTTL : : 5A : Y
+HEX2[1] : AE29 : output : 3.3-V LVTTL : : 5B : Y
+VCCIO5B : AE30 : power : : 3.3V : 5B :
+GND : AF1 : gnd : : : :
+GND : AF2 : gnd : : : :
+GND : AF3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A :
+VCCIO3A : AF7 : power : : 3.3V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A :
+SW[2] : AF9 : input : 3.3-V LVTTL : : 3A : Y
+SW[3] : AF10 : input : 3.3-V LVTTL : : 3A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
+GND : AF12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
+GND : AF17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
+VCCIO4A : AF22 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A :
+GND : AF27 : gnd : : : :
+HEX0[4] : AF28 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[4] : AF29 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[5] : AF30 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A :
+VCCIO3A : AG4 : power : : 3.3V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3A :
+GND : AG9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B :
+GND : AG14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
+VCCIO4A : AG19 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
+GND : AG24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
+HEX0[3] : AG27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[5] : AG28 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AG29 : power : : 3.3V : 5A :
+HEX1[3] : AG30 : output : 3.3-V LVTTL : : 5A : Y
+GND : AH1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A :
+GND : AH6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3B :
+GND : AH11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15 : : : : 3B :
+VCCIO4A : AH16 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A :
+GND : AH21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4A :
+VCCIO4A : AH26 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
+HEX0[6] : AH28 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[1] : AH29 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[2] : AH30 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2 : : : : 3A :
+GND : AJ3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B :
+VCCIO3B : AJ8 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B :
+VCCIO3B : AJ13 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B :
+VREFB3BN0 : AJ15 : power : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A :
+GND : AJ18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 4A :
+VCCIO4A : AJ23 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A :
+GND : AJ28 : gnd : : : :
+HEX1[0] : AJ29 : output : 3.3-V LVTTL : : 5A : Y
+GND : AJ30 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4 : : : : 3B :
+GND : AK5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B :
+VCCIO3B : AK10 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B :
+GND : AK15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A :
+VREFB4AN0 : AK17 : power : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A :
+VCCIO4A : AK20 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A :
+GND : AK25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A :
+VCCIO8A : B4 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A :
+GND : B9 : gnd : : : :
+VREFB8AN0 : B10 : power : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A :
+GND : B14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B :
+GND : B19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A :
+GND : B24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A :
+HPS_TDI : B27 : : : : 7A :
+HPS_TDO : B28 : : : : 7A :
+GND : B29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A :
+GND : C1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A :
+GND : C6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A :
+VCCIO8A : C11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D :
+GND : C16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B :
+GND : C21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A :
+GND : C26 : gnd : : : :
+HPS_nRST : C27 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A :
+GND : D3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
+VCCIO8A : D8 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
+GND : D13 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C :
+VCCIO7C_HPS : D18 : power : : 2.5V : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A :
+GND : D23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A :
+HPS_CLK1 : D25 : : : : 7A :
+GND : D26 : : : : 7A :
+HPS_RZQ_0 : D27 : : : : 6A :
+VCCIO6A_HPS : D28 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A :
+VCCIO8A : E5 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
+GND : E10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D :
+VCCIO7D_HPS : E15 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B :
+VCCIO7B_HPS : E20 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B :
+VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A :
+GND : E25 : gnd : : : :
+DNU : E26 : : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A :
+GND : E30 : gnd : : : :
+DNU : F1 : : : : :
+GND : F2 : gnd : : : :
+CONF_DONE : F3 : : : : 9A :
+nSTATUS : F4 : : : : 9A :
+GND : F5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
+GND : F7 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A :
+VCCIO8A : F12 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D :
+GND : F17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B :
+VCCIO7A_HPS : F22 : power : : 2.5V : 7A :
+HPS_nPOR : F23 : : : : 7A :
+HPS_PORSEL : F24 : : : : 7A :
+HPS_CLK2 : F25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
+GND : F27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A :
+GND : G1 : : : : :
+DNU : G2 : : : : :
+GND : G3 : gnd : : : :
+GND : G4 : gnd : : : :
+nCE : G5 : : : : 9A :
+MSEL2 : G6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8A :
+VCCIO8A : G9 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A :
+VCCIO8A : G14 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C :
+VCCIO7B_HPS : G19 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A :
+VCCRSTCLK_HPS : G23 : : : : 7A :
+GND : G24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
+VCCIO6A_HPS : G29 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A :
+GND : H1 : gnd : : : :
+GND : H2 : gnd : : : :
+DNU : H3 : : : : :
+DNU : H4 : : : : :
+GND : H5 : gnd : : : :
+VCCIO8A : H6 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
+VCCBAT : H9 : power : : 1.2V : :
+VCC_AUX : H10 : power : : 2.5V : :
+GND : H11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A :
+VCCIO7D_HPS : H16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A :
+VCCIO7A_HPS : H21 : power : : 2.5V : 7A :
+HPS_TCK : H22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
+VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A :
+GND : J1 : gnd : : : :
+GND : J2 : gnd : : : :
+GND : J3 : gnd : : : :
+GND : J4 : gnd : : : :
+nCONFIG : J5 : : : : 9A :
+GND : J6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
+GND : J8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
+VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A :
+VCCIO8A : J13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8A :
+DNU : J15 : : : : :
+VCC_AUX : J16 : power : : 2.5V : :
+VCCPD7C_HPS : J17 : power : : 2.5V : 7C :
+GND : J18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B :
+VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX_SHARED : J21 : power : : 2.5V : :
+GND : J22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
+GND : J28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A :
+GND : K1 : gnd : : : :
+GND : K2 : gnd : : : :
+DNU : K3 : : : : :
+DNU : K4 : : : : :
+GND : K5 : gnd : : : :
+MSEL1 : K6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
+VCCA_FPLL : K9 : power : : 2.5V : :
+GND : K10 : gnd : : : :
+VCCPD8A : K11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 8A :
+VCCPD8A : K13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A :
+GND : K15 : gnd : : : :
+VCCPD7D_HPS : K16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B :
+VCCPD7B_HPS : K18 : power : : 2.5V : 7B :
+VCCPD7A_HPS : K19 : power : : 2.5V : 7A :
+GND : K20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
+VCCIO6A_HPS : K24 : power : : 2.5V : 6A :
+GND : K25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A :
+VCCIO6A_HPS : K30 : power : : 2.5V : 6A :
+GND : L1 : gnd : : : :
+GND : L2 : gnd : : : :
+GND : L3 : gnd : : : :
+GND : L4 : gnd : : : :
+VCC : L5 : power : : 1.1V : :
+GND : L6 : gnd : : : :
+MSEL3 : L7 : : : : 9A :
+MSEL0 : L8 : : : : 9A :
+MSEL4 : L9 : : : : 9A :
+VCCPD8A : L10 : power : : 2.5V : 8A :
+GND : L11 : gnd : : : :
+VCCPD8A : L12 : power : : 2.5V : 8A :
+GND : L13 : gnd : : : :
+VCCPD8A : L14 : power : : 2.5V : 8A :
+GND : L15 : gnd : : : :
+VCC_HPS : L16 : power : : 1.1V : :
+GND : L17 : gnd : : : :
+VCC_HPS : L18 : power : : 1.1V : :
+GND : L19 : gnd : : : :
+VCC_HPS : L20 : power : : 1.1V : :
+VCCPLL_HPS : L21 : power : : 2.5V : :
+GND : L22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A :
+VCCIO6A_HPS : L27 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A :
+GND : M1 : gnd : : : :
+GND : M2 : gnd : : : :
+DNU : M3 : : : : :
+DNU : M4 : : : : :
+GND : M5 : gnd : : : :
+VCC : M6 : power : : 1.1V : :
+GND : M7 : gnd : : : :
+GND : M8 : gnd : : : :
+VCC : M9 : power : : 1.1V : :
+GND : M10 : gnd : : : :
+VCC : M11 : power : : 1.1V : :
+GND : M12 : gnd : : : :
+VCC : M13 : power : : 1.1V : :
+GND : M14 : gnd : : : :
+VCC_HPS : M15 : power : : 1.1V : :
+GND : M16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D :
+GND : M18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A :
+GND : M20 : gnd : : : :
+VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A :
+VCCIO6A_HPS : M24 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
+GND : M29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A :
+GND : N1 : gnd : : : :
+GND : N2 : gnd : : : :
+GND : N3 : gnd : : : :
+GND : N4 : gnd : : : :
+VCC : N5 : power : : 1.1V : :
+GND : N6 : gnd : : : :
+VCCA_FPLL : N7 : power : : 2.5V : :
+GND : N8 : gnd : : : :
+GND : N9 : gnd : : : :
+VCC : N10 : power : : 1.1V : :
+GND : N11 : gnd : : : :
+VCC : N12 : power : : 1.1V : :
+GND : N13 : gnd : : : :
+VCC : N14 : power : : 1.1V : :
+GND : N15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D :
+GND : N17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A :
+GND : N19 : gnd : : : :
+VCC_HPS : N20 : power : : 1.1V : :
+VCCIO6A_HPS : N21 : power : : 2.5V : 6A :
+VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A :
+GND : N26 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B :
+GND : P1 : gnd : : : :
+GND : P2 : gnd : : : :
+DNU : P3 : : : : :
+DNU : P4 : : : : :
+GND : P5 : gnd : : : :
+VCCA_FPLL : P6 : power : : 2.5V : :
+GND : P7 : gnd : : : :
+GND : P8 : gnd : : : :
+GND : P9 : gnd : : : :
+GND : P10 : gnd : : : :
+VCC : P11 : power : : 1.1V : :
+GND : P12 : gnd : : : :
+VCC : P13 : power : : 1.1V : :
+GND : P14 : gnd : : : :
+VCC_HPS : P15 : power : : 1.1V : :
+GND : P16 : gnd : : : :
+VCC_HPS : P17 : power : : 1.1V : :
+GND : P18 : gnd : : : :
+VCC_HPS : P19 : power : : 1.1V : :
+GND : P20 : gnd : : : :
+VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B :
+VCCIO6B_HPS : P23 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B :
+VCCIO6B_HPS : P28 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B :
+GND : R1 : gnd : : : :
+GND : R2 : gnd : : : :
+GND : R3 : gnd : : : :
+GND : R4 : gnd : : : :
+VCC : R5 : power : : 1.1V : :
+GND : R6 : gnd : : : :
+VCCA_FPLL : R7 : power : : 2.5V : :
+GND : R8 : gnd : : : :
+GND : R9 : gnd : : : :
+VCC : R10 : power : : 1.1V : :
+GND : R11 : gnd : : : :
+VCC : R12 : power : : 1.1V : :
+GND : R13 : gnd : : : :
+VCC : R14 : power : : 1.1V : :
+GND : R15 : gnd : : : :
+VCC_HPS : R16 : power : : 1.1V : :
+GND : R17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B :
+VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B :
+VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
+VCCIO6B_HPS : R25 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B :
+GND : R30 : gnd : : : :
+GND : T1 : gnd : : : :
+GND : T2 : gnd : : : :
+DNU : T3 : : : : :
+DNU : T4 : : : : :
+GND : T5 : gnd : : : :
+VCC : T6 : power : : 1.1V : :
+GND : T7 : gnd : : : :
+GND : T8 : gnd : : : :
+GND : T9 : gnd : : : :
+GND : T10 : gnd : : : :
+VCC : T11 : power : : 1.1V : :
+GND : T12 : gnd : : : :
+VCC : T13 : power : : 1.1V : :
+GND : T14 : gnd : : : :
+GND : T15 : gnd : : : :
+GND : T16 : gnd : : : :
+VCC_HPS : T17 : power : : 1.1V : :
+GND : T18 : gnd : : : :
+VCC_HPS : T19 : power : : 1.1V : :
+GND : T20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B :
+VCCIO6B_HPS : T22 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
+GND : T27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B :
+GND : U1 : gnd : : : :
+GND : U2 : gnd : : : :
+GND : U3 : gnd : : : :
+GND : U4 : gnd : : : :
+VCC : U5 : power : : 1.1V : :
+GND : U6 : gnd : : : :
+DCLK : U7 : : : : 3A :
+TDI : U8 : input : : : 3A :
+GND : U9 : gnd : : : :
+VCC : U10 : power : : 1.1V : :
+GND : U11 : gnd : : : :
+VCC : U12 : power : : 1.1V : :
+GND : U13 : gnd : : : :
+VCC : U14 : power : : 1.1V : :
+GND : U15 : gnd : : : :
+VCC_HPS : U16 : power : : 1.1V : :
+GND : U17 : gnd : : : :
+VCC_HPS : U18 : power : : 1.1V : :
+VCCIO6B_HPS : U19 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B :
+VCC : U21 : power : : 1.1V : :
+GND : U22 : gnd : : : :
+VCCPD5B : U23 : power : : 3.3V : 5B :
+GND : U24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
+GND : U29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B :
+GND : V1 : gnd : : : :
+GND : V2 : gnd : : : :
+DNU : V3 : : : : :
+DNU : V4 : : : : :
+GND : V5 : gnd : : : :
+VCCA_FPLL : V6 : power : : 2.5V : :
+GND : V7 : gnd : : : :
+VCCA_FPLL : V8 : power : : 2.5V : :
+TMS : V9 : input : : : 3A :
+GND : V10 : gnd : : : :
+VCC : V11 : power : : 1.1V : :
+GND : V12 : gnd : : : :
+VCC : V13 : power : : 1.1V : :
+GND : V14 : gnd : : : :
+VCC : V15 : power : : 1.1V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
+GND : V19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
+GND : V21 : gnd : : : :
+VCCPD5A : V22 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5A :
+VCCPD5A : V24 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
+VCCIO6B_HPS : V26 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B :
+GND : W1 : gnd : : : :
+GND : W2 : gnd : : : :
+GND : W3 : gnd : : : :
+GND : W4 : gnd : : : :
+VCC : W5 : power : : 1.1V : :
+GND : W6 : gnd : : : :
+GND : W7 : gnd : : : :
+GND : W8 : gnd : : : :
+GND : W9 : gnd : : : :
+VCC : W10 : power : : 1.1V : :
+GND : W11 : gnd : : : :
+VCC : W12 : power : : 1.1V : :
+GND : W13 : gnd : : : :
+VCC : W14 : power : : 1.1V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
+GND : W18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5A :
+VCCIO5A : W23 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W24 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B :
+GND : W28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B :
+GND : Y1 : gnd : : : :
+GND : Y2 : gnd : : : :
+DNU : Y3 : : : : :
+DNU : Y4 : : : : :
+GND : Y5 : gnd : : : :
+VCC : Y6 : power : : 1.1V : :
+GND : Y7 : gnd : : : :
+GND : Y8 : gnd : : : :
+VCC : Y9 : power : : 1.1V : :
+GND : Y10 : gnd : : : :
+VCC : Y11 : power : : 1.1V : :
+GND : Y12 : gnd : : : :
+VCC : Y13 : power : : 1.1V : :
+GND : Y14 : gnd : : : :
+GND : Y15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
+GND : Y20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5A :
+VCCA_FPLL : Y22 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A :
+GND : Y25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B :
+GND : Y30 : gnd : : : :
diff --git a/part_1/ex3/output_files/ex3.sld b/part_1/ex3/output_files/ex3.sld new file mode 100644 index 0000000..41a6030 --- /dev/null +++ b/part_1/ex3/output_files/ex3.sld @@ -0,0 +1 @@ +<sld_project_info/>
diff --git a/part_1/ex3/output_files/ex3.sof b/part_1/ex3/output_files/ex3.sof Binary files differnew file mode 100644 index 0000000..3be9b57 --- /dev/null +++ b/part_1/ex3/output_files/ex3.sof diff --git a/part_1/ex3/output_files/ex3.sta.rpt b/part_1/ex3/output_files/ex3.sta.rpt new file mode 100644 index 0000000..9bd1ddf --- /dev/null +++ b/part_1/ex3/output_files/ex3.sta.rpt @@ -0,0 +1,648 @@ +TimeQuest Timing Analyzer report for ex3
+Tue Nov 15 10:58:32 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. TimeQuest Timing Analyzer Summary
+ 3. Parallel Compilation
+ 4. Clocks
+ 5. Slow 1100mV 85C Model Fmax Summary
+ 6. Timing Closure Recommendations
+ 7. Slow 1100mV 85C Model Setup Summary
+ 8. Slow 1100mV 85C Model Hold Summary
+ 9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Clock Transfers
+ 40. Report TCCS
+ 41. Report RSKM
+ 42. Unconstrained Paths Summary
+ 43. Unconstrained Input Ports
+ 44. Unconstrained Output Ports
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer ; TimeQuest ;
+; Revision Name ; ex3 ;
+; Device Family ; Cyclone V ;
+; Device Name ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Delay Model ; Combined ;
+; Rise/Fall Delays ; Enabled ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.02 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.9% ;
+; Processor 3 ; 0.9% ;
+; Processor 4 ; 0.3% ;
++----------------------------+-------------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+---------------------------------------
+; Fast 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Fast 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
+; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------+
+; Input Transition Times ;
++-------+--------------+-----------------+-----------------+
+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------+--------------+-----------------+-----------------+
+; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
++-------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary ;
++---------------------------------+-------+------+
+; Property ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks ; 0 ; 0 ;
+; Unconstrained Clocks ; 0 ; 0 ;
+; Unconstrained Input Ports ; 10 ; 10 ;
+; Unconstrained Input Port Paths ; 66 ; 66 ;
+; Unconstrained Output Ports ; 20 ; 20 ;
+; Unconstrained Output Port Paths ; 66 ; 66 ;
++---------------------------------+-------+------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 10:58:24 2016
+Info: Command: quartus_sta ex3 -c ex3
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex3.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1100mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
+ Info: Peak virtual memory: 1175 megabytes
+ Info: Processing ended: Tue Nov 15 10:58:32 2016
+ Info: Elapsed time: 00:00:08
+ Info: Total CPU time (on all processors): 00:00:05
+
+
diff --git a/part_1/ex3/output_files/ex3.sta.summary b/part_1/ex3/output_files/ex3.sta.summary new file mode 100644 index 0000000..6640100 --- /dev/null +++ b/part_1/ex3/output_files/ex3.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/part_1/ex3/verilog_files/hex_to_7seg.v b/part_1/ex3/verilog_files/hex_to_7seg.v new file mode 100644 index 0000000..82aa9a5 --- /dev/null +++ b/part_1/ex3/verilog_files/hex_to_7seg.v @@ -0,0 +1,27 @@ +module hex_to_7seg (out, in);
+
+ output [6:0] out;
+ input [3:0] in;
+
+ reg [6:0] out;
+
+ always @ (*)
+ case(in)
+ 4'h0: out = 7'b1000000;
+ 4'h1: out = 7'b1111001;
+ 4'h2: out = 7'b0100100;
+ 4'h3: out = 7'b0110000;
+ 4'h4: out = 7'b0011001;
+ 4'h5: out = 7'b0010010;
+ 4'h6: out = 7'b0000010;
+ 4'h7: out = 7'b1111000;
+ 4'h8: out = 7'b0000000;
+ 4'h9: out = 7'b0011000;
+ 4'ha: out = 7'b0001000;
+ 4'hb: out = 7'b0000011;
+ 4'hc: out = 7'b1000110;
+ 4'hd: out = 7'b0100001;
+ 4'he: out = 7'b0000110;
+ 4'hf: out = 7'b0001110;
+ endcase
+endmodule
diff --git a/part_1/ex3/verilog_files/hex_to_7seg.v.bak b/part_1/ex3/verilog_files/hex_to_7seg.v.bak new file mode 100644 index 0000000..82aa9a5 --- /dev/null +++ b/part_1/ex3/verilog_files/hex_to_7seg.v.bak @@ -0,0 +1,27 @@ +module hex_to_7seg (out, in);
+
+ output [6:0] out;
+ input [3:0] in;
+
+ reg [6:0] out;
+
+ always @ (*)
+ case(in)
+ 4'h0: out = 7'b1000000;
+ 4'h1: out = 7'b1111001;
+ 4'h2: out = 7'b0100100;
+ 4'h3: out = 7'b0110000;
+ 4'h4: out = 7'b0011001;
+ 4'h5: out = 7'b0010010;
+ 4'h6: out = 7'b0000010;
+ 4'h7: out = 7'b1111000;
+ 4'h8: out = 7'b0000000;
+ 4'h9: out = 7'b0011000;
+ 4'ha: out = 7'b0001000;
+ 4'hb: out = 7'b0000011;
+ 4'hc: out = 7'b1000110;
+ 4'hd: out = 7'b0100001;
+ 4'he: out = 7'b0000110;
+ 4'hf: out = 7'b0001110;
+ endcase
+endmodule
diff --git a/part_1/ex4/c5_pin_model_dump.txt b/part_1/ex4/c5_pin_model_dump.txt new file mode 100644 index 0000000..a895a64 --- /dev/null +++ b/part_1/ex4/c5_pin_model_dump.txt @@ -0,0 +1,118 @@ +io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_1/ex4/db/_cmp.kpt b/part_1/ex4/db/_cmp.kpt Binary files differnew file mode 100644 index 0000000..580e170 --- /dev/null +++ b/part_1/ex4/db/_cmp.kpt diff --git a/part_1/ex4/db/ex4.(0).cnf.cdb b/part_1/ex4/db/ex4.(0).cnf.cdb Binary files differnew file mode 100644 index 0000000..898bf01 --- /dev/null +++ b/part_1/ex4/db/ex4.(0).cnf.cdb diff --git a/part_1/ex4/db/ex4.(0).cnf.hdb b/part_1/ex4/db/ex4.(0).cnf.hdb Binary files differnew file mode 100644 index 0000000..cc357aa --- /dev/null +++ b/part_1/ex4/db/ex4.(0).cnf.hdb diff --git a/part_1/ex4/db/ex4.(1).cnf.cdb b/part_1/ex4/db/ex4.(1).cnf.cdb Binary files differnew file mode 100644 index 0000000..34e627d --- /dev/null +++ b/part_1/ex4/db/ex4.(1).cnf.cdb diff --git a/part_1/ex4/db/ex4.(1).cnf.hdb b/part_1/ex4/db/ex4.(1).cnf.hdb Binary files differnew file mode 100644 index 0000000..fe13cf6 --- /dev/null +++ b/part_1/ex4/db/ex4.(1).cnf.hdb diff --git a/part_1/ex4/db/ex4.(2).cnf.cdb b/part_1/ex4/db/ex4.(2).cnf.cdb Binary files differnew file mode 100644 index 0000000..6e30e47 --- /dev/null +++ b/part_1/ex4/db/ex4.(2).cnf.cdb diff --git a/part_1/ex4/db/ex4.(2).cnf.hdb b/part_1/ex4/db/ex4.(2).cnf.hdb Binary files differnew file mode 100644 index 0000000..93ba6b6 --- /dev/null +++ b/part_1/ex4/db/ex4.(2).cnf.hdb diff --git a/part_1/ex4/db/ex4.(3).cnf.cdb b/part_1/ex4/db/ex4.(3).cnf.cdb Binary files differnew file mode 100644 index 0000000..2b70296 --- /dev/null +++ b/part_1/ex4/db/ex4.(3).cnf.cdb diff --git a/part_1/ex4/db/ex4.(3).cnf.hdb b/part_1/ex4/db/ex4.(3).cnf.hdb Binary files differnew file mode 100644 index 0000000..34b5383 --- /dev/null +++ b/part_1/ex4/db/ex4.(3).cnf.hdb diff --git a/part_1/ex4/db/ex4.(4).cnf.cdb b/part_1/ex4/db/ex4.(4).cnf.cdb Binary files differnew file mode 100644 index 0000000..d0981a4 --- /dev/null +++ b/part_1/ex4/db/ex4.(4).cnf.cdb diff --git a/part_1/ex4/db/ex4.(4).cnf.hdb b/part_1/ex4/db/ex4.(4).cnf.hdb Binary files differnew file mode 100644 index 0000000..1b983ff --- /dev/null +++ b/part_1/ex4/db/ex4.(4).cnf.hdb diff --git a/part_1/ex4/db/ex4.ae.hdb b/part_1/ex4/db/ex4.ae.hdb Binary files differnew file mode 100644 index 0000000..afbd7d6 --- /dev/null +++ b/part_1/ex4/db/ex4.ae.hdb diff --git a/part_1/ex4/db/ex4.analyze_file.qmsg b/part_1/ex4/db/ex4.analyze_file.qmsg new file mode 100644 index 0000000..a056ef3 --- /dev/null +++ b/part_1/ex4/db/ex4.analyze_file.qmsg @@ -0,0 +1,9 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479209419389 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479209419391 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 11:30:19 2016 " "Processing started: Tue Nov 15 11:30:19 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479209419391 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479209419391 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex4 -c ex4 --analyze_file=H:/VERI/part_1/ex4/verilog_files/add3_ge5.v " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex4 -c ex4 --analyze_file=H:/VERI/part_1/ex4/verilog_files/add3_ge5.v" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479209419391 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479209419876 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479209419876 ""}
+{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"input\"; expecting \";\" add3_ge5.v(3) " "Verilog HDL syntax error at add3_ge5.v(3) near text: \"input\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "verilog_files/add3_ge5.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/add3_ge5.v" 3 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Design Software" 0 -1 1479209428595 ""}
+{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"always\"; expecting \";\" add3_ge5.v(5) " "Verilog HDL syntax error at add3_ge5.v(5) near text: \"always\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "verilog_files/add3_ge5.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/add3_ge5.v" 5 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Design Software" 0 -1 1479209428595 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "add3_ge5 add3_ge5.v(1) " "Ignored design unit \"add3_ge5\" at add3_ge5.v(1) due to previous errors" { } { { "verilog_files/add3_ge5.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/add3_ge5.v" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Design Software" 0 -1 1479209428601 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analyze Current File 3 s 1 Quartus Prime " "Quartus Prime Analyze Current File was unsuccessful. 3 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "831 " "Peak virtual memory: 831 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479209428607 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Nov 15 11:30:28 2016 " "Processing ended: Tue Nov 15 11:30:28 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479209428607 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479209428607 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479209428607 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479209428607 ""}
diff --git a/part_1/ex4/db/ex4.asm.qmsg b/part_1/ex4/db/ex4.asm.qmsg new file mode 100644 index 0000000..8836e3f --- /dev/null +++ b/part_1/ex4/db/ex4.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479210573826 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479210573831 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 11:49:33 2016 " "Processing started: Tue Nov 15 11:49:33 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479210573831 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479210573831 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex4 -c ex4 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex4 -c ex4" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479210573831 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479210574817 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479210579556 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "892 " "Peak virtual memory: 892 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479210582702 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 11:49:42 2016 " "Processing ended: Tue Nov 15 11:49:42 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479210582702 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479210582702 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479210582702 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479210582702 ""}
diff --git a/part_1/ex4/db/ex4.asm.rdb b/part_1/ex4/db/ex4.asm.rdb Binary files differnew file mode 100644 index 0000000..2125961 --- /dev/null +++ b/part_1/ex4/db/ex4.asm.rdb diff --git a/part_1/ex4/db/ex4.cbx.xml b/part_1/ex4/db/ex4.cbx.xml new file mode 100644 index 0000000..3d091b0 --- /dev/null +++ b/part_1/ex4/db/ex4.cbx.xml @@ -0,0 +1,5 @@ +<?xml version="1.0" ?>
+<LOG_ROOT>
+ <PROJECT NAME="ex4">
+ </PROJECT>
+</LOG_ROOT>
diff --git a/part_1/ex4/db/ex4.cmp.ammdb b/part_1/ex4/db/ex4.cmp.ammdb Binary files differnew file mode 100644 index 0000000..afc7e0a --- /dev/null +++ b/part_1/ex4/db/ex4.cmp.ammdb diff --git a/part_1/ex4/db/ex4.cmp.bpm b/part_1/ex4/db/ex4.cmp.bpm Binary files differnew file mode 100644 index 0000000..7c2021e --- /dev/null +++ b/part_1/ex4/db/ex4.cmp.bpm diff --git a/part_1/ex4/db/ex4.cmp.cdb b/part_1/ex4/db/ex4.cmp.cdb Binary files differnew file mode 100644 index 0000000..7d9edf7 --- /dev/null +++ b/part_1/ex4/db/ex4.cmp.cdb diff --git a/part_1/ex4/db/ex4.cmp.hdb b/part_1/ex4/db/ex4.cmp.hdb Binary files differnew file mode 100644 index 0000000..80bcd34 --- /dev/null +++ b/part_1/ex4/db/ex4.cmp.hdb diff --git a/part_1/ex4/db/ex4.cmp.idb b/part_1/ex4/db/ex4.cmp.idb Binary files differnew file mode 100644 index 0000000..a293fe9 --- /dev/null +++ b/part_1/ex4/db/ex4.cmp.idb diff --git a/part_1/ex4/db/ex4.cmp.logdb b/part_1/ex4/db/ex4.cmp.logdb new file mode 100644 index 0000000..73f6bdb --- /dev/null +++ b/part_1/ex4/db/ex4.cmp.logdb @@ -0,0 +1,77 @@ +v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,38;0;38;0;0;38;38;0;38;38;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;38;0;38;38;0;0;38;0;0;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_1/ex4/db/ex4.cmp.rdb b/part_1/ex4/db/ex4.cmp.rdb Binary files differnew file mode 100644 index 0000000..21b830b --- /dev/null +++ b/part_1/ex4/db/ex4.cmp.rdb diff --git a/part_1/ex4/db/ex4.cmp_merge.kpt b/part_1/ex4/db/ex4.cmp_merge.kpt Binary files differnew file mode 100644 index 0000000..a058c0f --- /dev/null +++ b/part_1/ex4/db/ex4.cmp_merge.kpt diff --git a/part_1/ex4/db/ex4.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_1/ex4/db/ex4.cyclonev_io_sim_cache.ff_0c_fast.hsd Binary files differnew file mode 100644 index 0000000..5b115d6 --- /dev/null +++ b/part_1/ex4/db/ex4.cyclonev_io_sim_cache.ff_0c_fast.hsd diff --git a/part_1/ex4/db/ex4.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_1/ex4/db/ex4.cyclonev_io_sim_cache.ff_85c_fast.hsd Binary files differnew file mode 100644 index 0000000..3a7a497 --- /dev/null +++ b/part_1/ex4/db/ex4.cyclonev_io_sim_cache.ff_85c_fast.hsd diff --git a/part_1/ex4/db/ex4.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_1/ex4/db/ex4.cyclonev_io_sim_cache.tt_0c_slow.hsd Binary files differnew file mode 100644 index 0000000..aa473fa --- /dev/null +++ b/part_1/ex4/db/ex4.cyclonev_io_sim_cache.tt_0c_slow.hsd diff --git a/part_1/ex4/db/ex4.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_1/ex4/db/ex4.cyclonev_io_sim_cache.tt_85c_slow.hsd Binary files differnew file mode 100644 index 0000000..dce4f6b --- /dev/null +++ b/part_1/ex4/db/ex4.cyclonev_io_sim_cache.tt_85c_slow.hsd diff --git a/part_1/ex4/db/ex4.db_info b/part_1/ex4/db/ex4.db_info new file mode 100644 index 0000000..00de183 --- /dev/null +++ b/part_1/ex4/db/ex4.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 15 11:03:25 2016
diff --git a/part_1/ex4/db/ex4.fit.qmsg b/part_1/ex4/db/ex4.fit.qmsg new file mode 100644 index 0000000..4c1c77a --- /dev/null +++ b/part_1/ex4/db/ex4.fit.qmsg @@ -0,0 +1,45 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479210538622 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479210538623 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex4 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex4\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479210538889 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479210538957 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479210538957 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479210539357 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479210539519 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479210549571 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210549605 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479210549607 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479210549608 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479210549608 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479210549608 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479210549609 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479210549609 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479210549609 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479210549610 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479210549610 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210549640 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479210549640 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210549646 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex4.sdc " "Synopsys Design Constraints File file not found: 'ex4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1479210555249 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1479210555250 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1479210555251 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1479210555252 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479210555253 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1479210555253 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1479210555253 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479210555256 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479210555330 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210555784 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479210556203 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479210556458 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210556458 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479210557624 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" { } { { "loc" "" { Generic "H:/VERI/part_1/ex4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479210561915 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479210561915 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479210562185 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479210562185 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479210562185 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210562190 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479210563485 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479210563521 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479210563910 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479210563910 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479210564299 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210566523 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479210566759 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/VERI/part_1/ex4/output_files/ex4.fit.smsg " "Generated suppressed messages file H:/VERI/part_1/ex4/output_files/ex4.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479210566888 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 49 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 49 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2581 " "Peak virtual memory: 2581 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479210568819 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 11:49:28 2016 " "Processing ended: Tue Nov 15 11:49:28 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479210568819 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Elapsed time: 00:00:31" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479210568819 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:49 " "Total CPU time (on all processors): 00:00:49" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479210568819 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479210568819 ""}
diff --git a/part_1/ex4/db/ex4.hier_info b/part_1/ex4/db/ex4.hier_info new file mode 100644 index 0000000..418ec9b --- /dev/null +++ b/part_1/ex4/db/ex4.hier_info @@ -0,0 +1,258 @@ +|ex4
+SW[0] => SW[0].IN1
+SW[1] => SW[1].IN1
+SW[2] => SW[2].IN1
+SW[3] => SW[3].IN1
+SW[4] => SW[4].IN1
+SW[5] => SW[5].IN1
+SW[6] => SW[6].IN1
+SW[7] => SW[7].IN1
+SW[8] => SW[8].IN1
+SW[9] => SW[9].IN1
+HEX0[0] <= hex_to_7seg:comb_4.port0
+HEX0[1] <= hex_to_7seg:comb_4.port0
+HEX0[2] <= hex_to_7seg:comb_4.port0
+HEX0[3] <= hex_to_7seg:comb_4.port0
+HEX0[4] <= hex_to_7seg:comb_4.port0
+HEX0[5] <= hex_to_7seg:comb_4.port0
+HEX0[6] <= hex_to_7seg:comb_4.port0
+HEX1[0] <= hex_to_7seg:comb_5.port0
+HEX1[1] <= hex_to_7seg:comb_5.port0
+HEX1[2] <= hex_to_7seg:comb_5.port0
+HEX1[3] <= hex_to_7seg:comb_5.port0
+HEX1[4] <= hex_to_7seg:comb_5.port0
+HEX1[5] <= hex_to_7seg:comb_5.port0
+HEX1[6] <= hex_to_7seg:comb_5.port0
+HEX2[0] <= hex_to_7seg:comb_6.port0
+HEX2[1] <= hex_to_7seg:comb_6.port0
+HEX2[2] <= hex_to_7seg:comb_6.port0
+HEX2[3] <= hex_to_7seg:comb_6.port0
+HEX2[4] <= hex_to_7seg:comb_6.port0
+HEX2[5] <= hex_to_7seg:comb_6.port0
+HEX2[6] <= hex_to_7seg:comb_6.port0
+HEX3[0] <= hex_to_7seg:comb_7.port0
+HEX3[1] <= hex_to_7seg:comb_7.port0
+HEX3[2] <= hex_to_7seg:comb_7.port0
+HEX3[3] <= hex_to_7seg:comb_7.port0
+HEX3[4] <= hex_to_7seg:comb_7.port0
+HEX3[5] <= hex_to_7seg:comb_7.port0
+HEX3[6] <= hex_to_7seg:comb_7.port0
+
+
+|ex4|bin2bcd_10:comb_3
+B[0] => BCD_0[0].DATAIN
+B[1] => w12[0].IN1
+B[2] => w9[0].IN1
+B[3] => w7[0].IN1
+B[4] => w5[0].IN1
+B[5] => w3[0].IN1
+B[6] => w2[0].IN1
+B[7] => w1[0].IN1
+B[8] => w1[1].IN1
+B[9] => w1[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A12.port1
+BCD_0[2] <= add3_ge5:A12.port1
+BCD_0[3] <= add3_ge5:A12.port1
+BCD_1[0] <= add3_ge5:A12.port1
+BCD_1[1] <= add3_ge5:A11.port1
+BCD_1[2] <= add3_ge5:A11.port1
+BCD_1[3] <= add3_ge5:A11.port1
+BCD_2[0] <= add3_ge5:A11.port1
+BCD_2[1] <= add3_ge5:A10.port1
+BCD_2[2] <= add3_ge5:A10.port1
+BCD_2[3] <= add3_ge5:A10.port1
+BCD_3[0] <= add3_ge5:A10.port1
+BCD_3[1] <= <GND>
+BCD_3[2] <= <GND>
+BCD_3[3] <= <GND>
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A1
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A2
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A3
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A4
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A5
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A6
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A7
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A8
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A9
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A10
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A11
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|bin2bcd_10:comb_3|add3_ge5:A12
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex4|hex_to_7seg:comb_4
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex4|hex_to_7seg:comb_5
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex4|hex_to_7seg:comb_6
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex4|hex_to_7seg:comb_7
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_1/ex4/db/ex4.hif b/part_1/ex4/db/ex4.hif Binary files differnew file mode 100644 index 0000000..88b7589 --- /dev/null +++ b/part_1/ex4/db/ex4.hif diff --git a/part_1/ex4/db/ex4.lpc.html b/part_1/ex4/db/ex4.lpc.html new file mode 100644 index 0000000..bd64001 --- /dev/null +++ b/part_1/ex4/db/ex4.lpc.html @@ -0,0 +1,290 @@ +<TABLE>
+<TR bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >comb_7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A12</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A11</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A10</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A9</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A4</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3|A1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >comb_3</TD>
+<TD >10</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >16</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_1/ex4/db/ex4.lpc.rdb b/part_1/ex4/db/ex4.lpc.rdb Binary files differnew file mode 100644 index 0000000..a5dc5db --- /dev/null +++ b/part_1/ex4/db/ex4.lpc.rdb diff --git a/part_1/ex4/db/ex4.lpc.txt b/part_1/ex4/db/ex4.lpc.txt new file mode 100644 index 0000000..9dbe288 --- /dev/null +++ b/part_1/ex4/db/ex4.lpc.txt @@ -0,0 +1,23 @@ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; comb_7 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_6 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_5 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_4 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A12 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A11 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A10 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A9 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A8 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A7 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A6 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A5 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A4 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A3 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A2 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3|A1 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; comb_3 ; 10 ; 3 ; 0 ; 3 ; 16 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_1/ex4/db/ex4.map.ammdb b/part_1/ex4/db/ex4.map.ammdb Binary files differnew file mode 100644 index 0000000..174eb00 --- /dev/null +++ b/part_1/ex4/db/ex4.map.ammdb diff --git a/part_1/ex4/db/ex4.map.bpm b/part_1/ex4/db/ex4.map.bpm Binary files differnew file mode 100644 index 0000000..3227fb0 --- /dev/null +++ b/part_1/ex4/db/ex4.map.bpm diff --git a/part_1/ex4/db/ex4.map.cdb b/part_1/ex4/db/ex4.map.cdb Binary files differnew file mode 100644 index 0000000..3f840a8 --- /dev/null +++ b/part_1/ex4/db/ex4.map.cdb diff --git a/part_1/ex4/db/ex4.map.hdb b/part_1/ex4/db/ex4.map.hdb Binary files differnew file mode 100644 index 0000000..713a995 --- /dev/null +++ b/part_1/ex4/db/ex4.map.hdb diff --git a/part_1/ex4/db/ex4.map.kpt b/part_1/ex4/db/ex4.map.kpt Binary files differnew file mode 100644 index 0000000..79cf4a3 --- /dev/null +++ b/part_1/ex4/db/ex4.map.kpt diff --git a/part_1/ex4/db/ex4.map.logdb b/part_1/ex4/db/ex4.map.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex4/db/ex4.map.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex4/db/ex4.map.qmsg b/part_1/ex4/db/ex4.map.qmsg new file mode 100644 index 0000000..5602bc2 --- /dev/null +++ b/part_1/ex4/db/ex4.map.qmsg @@ -0,0 +1,66 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479210522995 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479210522998 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 11:48:42 2016 " "Processing started: Tue Nov 15 11:48:42 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479210522998 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210522998 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex4 -c ex4 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex4 -c ex4" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210522998 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479210523638 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479210523638 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479210532117 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210532117 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532121 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532121 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532122 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532122 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532123 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532123 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532123 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532123 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532123 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532123 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532123 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532123 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532124 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532124 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532124 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532124 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532124 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532124 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532124 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532124 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532125 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532125 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532125 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532125 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532126 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532126 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532126 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532126 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532127 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479210532127 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210532127 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532140 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532140 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532140 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532140 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532140 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532140 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532142 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532142 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532142 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532142 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532142 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210532142 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_10.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_10 " "Found entity 1: bin2bcd_10" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479210532142 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210532142 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex4.v 1 1 " "Found 1 design units, including 1 entities, in source file ex4.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex4 " "Found entity 1: ex4" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479210532154 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210532154 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/add3_ge5.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479210532161 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210532161 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex4.v(8) " "Verilog HDL Instantiation warning at ex4.v(8): instance has no name" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 8 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479210532162 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex4.v(10) " "Verilog HDL Instantiation warning at ex4.v(10): instance has no name" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 10 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479210532162 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex4.v(11) " "Verilog HDL Instantiation warning at ex4.v(11): instance has no name" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 11 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479210532162 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex4.v(12) " "Verilog HDL Instantiation warning at ex4.v(12): instance has no name" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 12 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479210532162 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex4.v(13) " "Verilog HDL Instantiation warning at ex4.v(13): instance has no name" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 13 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479210532162 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex4 " "Elaborating entity \"ex4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479210532219 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_10 bin2bcd_10:comb_3 " "Elaborating entity \"bin2bcd_10\" for hierarchy \"bin2bcd_10:comb_3\"" { } { { "ex4.v" "comb_3" { Text "H:/VERI/part_1/ex4/ex4.v" 8 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479210532262 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_10:comb_3\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_10:comb_3\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_10.v" "A1" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 11 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479210532319 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:comb_4 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:comb_4\"" { } { { "ex4.v" "comb_4" { Text "H:/VERI/part_1/ex4/ex4.v" 10 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479210532339 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[1\] GND " "Pin \"HEX3\[1\]\" is stuck at GND" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210533189 "|ex4|HEX3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[2\] GND " "Pin \"HEX3\[2\]\" is stuck at GND" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210533189 "|ex4|HEX3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[6\] VCC " "Pin \"HEX3\[6\]\" is stuck at VCC" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210533189 "|ex4|HEX3[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1479210533189 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479210533263 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/VERI/part_1/ex4/output_files/ex4.map.smsg " "Generated suppressed messages file H:/VERI/part_1/ex4/output_files/ex4.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210533924 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479210534627 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479210534627 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "104 " "Implemented 104 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479210535469 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479210535469 ""} { "Info" "ICUT_CUT_TM_LCELLS" "66 " "Implemented 66 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479210535469 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479210535469 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "883 " "Peak virtual memory: 883 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479210535655 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 11:48:55 2016 " "Processing ended: Tue Nov 15 11:48:55 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479210535655 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479210535655 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479210535655 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210535655 ""}
diff --git a/part_1/ex4/db/ex4.map.rdb b/part_1/ex4/db/ex4.map.rdb Binary files differnew file mode 100644 index 0000000..77d3f32 --- /dev/null +++ b/part_1/ex4/db/ex4.map.rdb diff --git a/part_1/ex4/db/ex4.map_bb.cdb b/part_1/ex4/db/ex4.map_bb.cdb Binary files differnew file mode 100644 index 0000000..8f64ea1 --- /dev/null +++ b/part_1/ex4/db/ex4.map_bb.cdb diff --git a/part_1/ex4/db/ex4.map_bb.hdb b/part_1/ex4/db/ex4.map_bb.hdb Binary files differnew file mode 100644 index 0000000..4cff9e5 --- /dev/null +++ b/part_1/ex4/db/ex4.map_bb.hdb diff --git a/part_1/ex4/db/ex4.map_bb.logdb b/part_1/ex4/db/ex4.map_bb.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex4/db/ex4.map_bb.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex4/db/ex4.pplq.rdb b/part_1/ex4/db/ex4.pplq.rdb Binary files differnew file mode 100644 index 0000000..d70b3fb --- /dev/null +++ b/part_1/ex4/db/ex4.pplq.rdb diff --git a/part_1/ex4/db/ex4.pre_map.cdb b/part_1/ex4/db/ex4.pre_map.cdb Binary files differnew file mode 100644 index 0000000..950bd62 --- /dev/null +++ b/part_1/ex4/db/ex4.pre_map.cdb diff --git a/part_1/ex4/db/ex4.pre_map.hdb b/part_1/ex4/db/ex4.pre_map.hdb Binary files differnew file mode 100644 index 0000000..479bcac --- /dev/null +++ b/part_1/ex4/db/ex4.pre_map.hdb diff --git a/part_1/ex4/db/ex4.root_partition.map.reg_db.cdb b/part_1/ex4/db/ex4.root_partition.map.reg_db.cdb Binary files differnew file mode 100644 index 0000000..de77fc9 --- /dev/null +++ b/part_1/ex4/db/ex4.root_partition.map.reg_db.cdb diff --git a/part_1/ex4/db/ex4.routing.rdb b/part_1/ex4/db/ex4.routing.rdb Binary files differnew file mode 100644 index 0000000..a89b84d --- /dev/null +++ b/part_1/ex4/db/ex4.routing.rdb diff --git a/part_1/ex4/db/ex4.rtlv.hdb b/part_1/ex4/db/ex4.rtlv.hdb Binary files differnew file mode 100644 index 0000000..18af27e --- /dev/null +++ b/part_1/ex4/db/ex4.rtlv.hdb diff --git a/part_1/ex4/db/ex4.rtlv_sg.cdb b/part_1/ex4/db/ex4.rtlv_sg.cdb Binary files differnew file mode 100644 index 0000000..944d292 --- /dev/null +++ b/part_1/ex4/db/ex4.rtlv_sg.cdb diff --git a/part_1/ex4/db/ex4.rtlv_sg_swap.cdb b/part_1/ex4/db/ex4.rtlv_sg_swap.cdb Binary files differnew file mode 100644 index 0000000..9cf0c70 --- /dev/null +++ b/part_1/ex4/db/ex4.rtlv_sg_swap.cdb diff --git a/part_1/ex4/db/ex4.sld_design_entry.sci b/part_1/ex4/db/ex4.sld_design_entry.sci Binary files differnew file mode 100644 index 0000000..92c1102 --- /dev/null +++ b/part_1/ex4/db/ex4.sld_design_entry.sci diff --git a/part_1/ex4/db/ex4.sld_design_entry_dsc.sci b/part_1/ex4/db/ex4.sld_design_entry_dsc.sci Binary files differnew file mode 100644 index 0000000..92c1102 --- /dev/null +++ b/part_1/ex4/db/ex4.sld_design_entry_dsc.sci diff --git a/part_1/ex4/db/ex4.smart_action.txt b/part_1/ex4/db/ex4.smart_action.txt new file mode 100644 index 0000000..437a63e --- /dev/null +++ b/part_1/ex4/db/ex4.smart_action.txt @@ -0,0 +1 @@ +DONE
diff --git a/part_1/ex4/db/ex4.sta.qmsg b/part_1/ex4/db/ex4.sta.qmsg new file mode 100644 index 0000000..c3ae2f9 --- /dev/null +++ b/part_1/ex4/db/ex4.sta.qmsg @@ -0,0 +1,61 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479210584520 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479210584522 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 11:49:43 2016 " "Processing started: Tue Nov 15 11:49:43 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479210584522 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210584522 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex4 -c ex4 " "Command: quartus_sta ex4 -c ex4" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210584522 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479210584647 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210585268 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210585268 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210585315 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210585315 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex4.sdc " "Synopsys Design Constraints File file not found: 'ex4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586189 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586190 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586191 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586193 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586194 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586198 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479210586201 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586276 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479210586301 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586305 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586354 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586377 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586404 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586428 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586451 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479210586477 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210586561 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587407 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587514 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587514 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587514 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587514 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587515 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587547 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587566 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587588 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587610 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587629 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479210587650 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210587979 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210588732 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210588834 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210588834 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210588834 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210588834 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210588851 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210588869 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210588890 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210588917 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210588935 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479210588957 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210589333 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210589333 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210589333 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210589335 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210589356 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210589374 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210589393 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210589410 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210589428 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210591681 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210591685 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1202 " "Peak virtual memory: 1202 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479210592027 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 11:49:52 2016 " "Processing ended: Tue Nov 15 11:49:52 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479210592027 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479210592027 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479210592027 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479210592027 ""}
diff --git a/part_1/ex4/db/ex4.sta.rdb b/part_1/ex4/db/ex4.sta.rdb Binary files differnew file mode 100644 index 0000000..d436459 --- /dev/null +++ b/part_1/ex4/db/ex4.sta.rdb diff --git a/part_1/ex4/db/ex4.sta_cmp.6_slow_1100mv_85c.tdb b/part_1/ex4/db/ex4.sta_cmp.6_slow_1100mv_85c.tdb Binary files differnew file mode 100644 index 0000000..6689e0e --- /dev/null +++ b/part_1/ex4/db/ex4.sta_cmp.6_slow_1100mv_85c.tdb diff --git a/part_1/ex4/db/ex4.tis_db_list.ddb b/part_1/ex4/db/ex4.tis_db_list.ddb Binary files differnew file mode 100644 index 0000000..88225e8 --- /dev/null +++ b/part_1/ex4/db/ex4.tis_db_list.ddb diff --git a/part_1/ex4/db/ex4.tiscmp.fast_1100mv_0c.ddb b/part_1/ex4/db/ex4.tiscmp.fast_1100mv_0c.ddb Binary files differnew file mode 100644 index 0000000..c030390 --- /dev/null +++ b/part_1/ex4/db/ex4.tiscmp.fast_1100mv_0c.ddb diff --git a/part_1/ex4/db/ex4.tiscmp.fast_1100mv_85c.ddb b/part_1/ex4/db/ex4.tiscmp.fast_1100mv_85c.ddb Binary files differnew file mode 100644 index 0000000..100d471 --- /dev/null +++ b/part_1/ex4/db/ex4.tiscmp.fast_1100mv_85c.ddb diff --git a/part_1/ex4/db/ex4.tiscmp.slow_1100mv_0c.ddb b/part_1/ex4/db/ex4.tiscmp.slow_1100mv_0c.ddb Binary files differnew file mode 100644 index 0000000..d430ebc --- /dev/null +++ b/part_1/ex4/db/ex4.tiscmp.slow_1100mv_0c.ddb diff --git a/part_1/ex4/db/ex4.tiscmp.slow_1100mv_85c.ddb b/part_1/ex4/db/ex4.tiscmp.slow_1100mv_85c.ddb Binary files differnew file mode 100644 index 0000000..e2ea50c --- /dev/null +++ b/part_1/ex4/db/ex4.tiscmp.slow_1100mv_85c.ddb diff --git a/part_1/ex4/db/ex4.tmw_info b/part_1/ex4/db/ex4.tmw_info new file mode 100644 index 0000000..0dfbde9 --- /dev/null +++ b/part_1/ex4/db/ex4.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:01:12
+start_analysis_synthesis:s:00:00:16-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:36-start_full_compilation
+start_assembler:s:00:00:10-start_full_compilation
+start_timing_analyzer:s:00:00:10-start_full_compilation
diff --git a/part_1/ex4/db/ex4.vpr.ammdb b/part_1/ex4/db/ex4.vpr.ammdb Binary files differnew file mode 100644 index 0000000..24cfc95 --- /dev/null +++ b/part_1/ex4/db/ex4.vpr.ammdb diff --git a/part_1/ex4/db/ex4_partition_pins.json b/part_1/ex4/db/ex4_partition_pins.json new file mode 100644 index 0000000..fdc1023 --- /dev/null +++ b/part_1/ex4/db/ex4_partition_pins.json @@ -0,0 +1,149 @@ +{
+ "partitions" : [
+ {
+ "name" : "Top",
+ "pins" : [
+ {
+ "name" : "HEX0[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[5]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[0]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[1]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[2]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[3]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[4]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[5]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[6]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[7]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[8]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[9]",
+ "strict" : false
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file diff --git a/part_1/ex4/db/prev_cmp_ex4.qmsg b/part_1/ex4/db/prev_cmp_ex4.qmsg new file mode 100644 index 0000000..ea7d27f --- /dev/null +++ b/part_1/ex4/db/prev_cmp_ex4.qmsg @@ -0,0 +1,118 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479210471539 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479210471543 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 11:47:51 2016 " "Processing started: Tue Nov 15 11:47:51 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479210471543 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210471543 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex4 -c ex4 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex4 -c ex4" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210471543 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479210472391 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479210472391 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479210480968 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210480968 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480978 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480978 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480978 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480978 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480981 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480981 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480981 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480981 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480981 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480981 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480981 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480981 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480983 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480983 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480983 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480983 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480983 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480983 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480983 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480983 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480985 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480985 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480985 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480985 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480985 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480985 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480985 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480985 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480989 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479210480989 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210480989 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480997 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480997 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480997 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480997 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480997 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210480997 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210481003 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210481003 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210481003 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210481003 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210481003 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_10.v(7) " "Verilog HDL Declaration information at bin2bcd_10.v(7): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479210481003 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_10.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_10 " "Found entity 1: bin2bcd_10" { } { { "verilog_files/bin2bcd_10.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479210481003 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210481003 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex4.v 1 1 " "Found 1 design units, including 1 entities, in source file ex4.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex4 " "Found entity 1: ex4" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479210481014 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210481014 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/add3_ge5.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479210481023 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210481023 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex4.v(8) " "Verilog HDL Instantiation warning at ex4.v(8): instance has no name" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 8 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479210481024 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex4.v(10) " "Verilog HDL Instantiation warning at ex4.v(10): instance has no name" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 10 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479210481024 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex4.v(11) " "Verilog HDL Instantiation warning at ex4.v(11): instance has no name" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 11 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479210481024 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex4.v(12) " "Verilog HDL Instantiation warning at ex4.v(12): instance has no name" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 12 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479210481024 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex4.v(13) " "Verilog HDL Instantiation warning at ex4.v(13): instance has no name" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 13 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479210481024 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex4 " "Elaborating entity \"ex4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479210481225 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:comb_3 " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:comb_3\"" { } { { "ex4.v" "comb_3" { Text "H:/VERI/part_1/ex4/ex4.v" 8 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479210481356 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:comb_3\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:comb_3\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_16.v" "A1" { Text "H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479210481393 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:comb_4 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:comb_4\"" { } { { "ex4.v" "comb_4" { Text "H:/VERI/part_1/ex4/ex4.v" 10 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479210481427 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1479210482509 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[1\] GND " "Pin \"HEX3\[1\]\" is stuck at GND" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210482578 "|ex4|HEX3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[2\] GND " "Pin \"HEX3\[2\]\" is stuck at GND" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210482578 "|ex4|HEX3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[6\] VCC " "Pin \"HEX3\[6\]\" is stuck at VCC" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210482578 "|ex4|HEX3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[0\] GND " "Pin \"HEX4\[0\]\" is stuck at GND" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210482578 "|ex4|HEX4[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[1\] GND " "Pin \"HEX4\[1\]\" is stuck at GND" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210482578 "|ex4|HEX4[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[2\] GND " "Pin \"HEX4\[2\]\" is stuck at GND" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210482578 "|ex4|HEX4[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[3\] GND " "Pin \"HEX4\[3\]\" is stuck at GND" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210482578 "|ex4|HEX4[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[4\] GND " "Pin \"HEX4\[4\]\" is stuck at GND" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210482578 "|ex4|HEX4[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[5\] VCC " "Pin \"HEX4\[5\]\" is stuck at VCC" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210482578 "|ex4|HEX4[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[6\] GND " "Pin \"HEX4\[6\]\" is stuck at GND" { } { { "ex4.v" "" { Text "H:/VERI/part_1/ex4/ex4.v" 4 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1479210482578 "|ex4|HEX4[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1479210482578 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479210482651 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/VERI/part_1/ex4/output_files/ex4.map.smsg " "Generated suppressed messages file H:/VERI/part_1/ex4/output_files/ex4.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210483109 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479210483482 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479210483482 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "111 " "Implemented 111 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479210483824 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479210483824 ""} { "Info" "ICUT_CUT_TM_LCELLS" "66 " "Implemented 66 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479210483824 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479210483824 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "884 " "Peak virtual memory: 884 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479210483930 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 11:48:03 2016 " "Processing ended: Tue Nov 15 11:48:03 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479210483930 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479210483930 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479210483930 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479210483930 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1479210486317 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479210486319 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 11:48:05 2016 " "Processing started: Tue Nov 15 11:48:05 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479210486319 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1479210486319 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex4 -c ex4 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex4 -c ex4" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1479210486319 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1479210486439 ""}
+{ "Info" "0" "" "Project = ex4" { } { } 0 0 "Project = ex4" 0 0 "Fitter" 0 0 1479210486440 ""}
+{ "Info" "0" "" "Revision = ex4" { } { } 0 0 "Revision = ex4" 0 0 "Fitter" 0 0 1479210486440 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479210486669 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479210486673 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex4 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex4\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479210486955 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479210487004 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479210487004 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479210487411 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479210487578 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479210497685 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210497723 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479210497725 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479210497726 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479210497726 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479210497726 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479210497726 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479210497727 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479210497727 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479210497729 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479210497729 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479210497764 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479210497764 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210497769 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex4.sdc " "Synopsys Design Constraints File file not found: 'ex4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1479210503257 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1479210503258 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1479210503258 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1479210503259 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479210503259 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1479210503260 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1479210503260 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479210503262 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479210503339 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210503805 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479210504222 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479210504473 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210504473 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479210505655 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" { } { { "loc" "" { Generic "H:/VERI/part_1/ex4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479210510039 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479210510039 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479210510322 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479210510322 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479210510322 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210510326 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479210511648 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479210511684 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479210512091 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479210512091 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479210512484 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479210514800 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479210515035 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/VERI/part_1/ex4/output_files/ex4.fit.smsg " "Generated suppressed messages file H:/VERI/part_1/ex4/output_files/ex4.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479210515155 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 42 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 42 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2582 " "Peak virtual memory: 2582 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479210517095 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 11:48:37 2016 " "Processing ended: Tue Nov 15 11:48:37 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479210517095 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Elapsed time: 00:00:32" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479210517095 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:49 " "Total CPU time (on all processors): 00:00:49" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479210517095 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479210517095 ""}
diff --git a/part_1/ex4/ex4.bck b/part_1/ex4/ex4.bck new file mode 100644 index 0000000..38e1c23 --- /dev/null +++ b/part_1/ex4/ex4.bck @@ -0,0 +1,17 @@ +module ex4(SW, HEX0, HEX1, HEX2, HEX3, HEX4);
+
+ input [9:0] SW;
+ output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;
+
+ wire [3:0] w0, w1, w2, w3, w4;
+
+ bin2bcd_16(SW, w0, w1, w2, w3, w4);
+
+ hex_to_7seg(HEX0, w0);
+ hex_to_7seg(HEX1, w1);
+ hex_to_7seg(HEX2, w2);
+ hex_to_7seg(HEX3, w3);
+ assign HEX4 = 6'b100000;
+
+
+endmodule
\ No newline at end of file diff --git a/part_1/ex4/ex4.qpf b/part_1/ex4/ex4.qpf new file mode 100644 index 0000000..68a9374 --- /dev/null +++ b/part_1/ex4/ex4.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 11:03:24 November 15, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.0"
+DATE = "11:03:24 November 15, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ex4"
diff --git a/part_1/ex4/ex4.qsf b/part_1/ex4/ex4.qsf new file mode 100644 index 0000000..9d1bd9c --- /dev/null +++ b/part_1/ex4/ex4.qsf @@ -0,0 +1,271 @@ +#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 11:03:24 November 15, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# ex4_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex4
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:24 NOVEMBER 15, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_10.v
+set_global_assignment -name VERILOG_FILE ex4.v
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
+set_global_assignment -name SOURCE_FILE ex4.bck
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/part_1/ex4/ex4.qsf.bak b/part_1/ex4/ex4.qsf.bak new file mode 100644 index 0000000..11bfcde --- /dev/null +++ b/part_1/ex4/ex4.qsf.bak @@ -0,0 +1,60 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 11:03:24 November 15, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# ex4_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex4
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:24 NOVEMBER 15, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_10.v
+set_global_assignment -name VERILOG_FILE ex4.v
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/part_1/ex4/ex4.qws b/part_1/ex4/ex4.qws Binary files differnew file mode 100644 index 0000000..bda3374 --- /dev/null +++ b/part_1/ex4/ex4.qws diff --git a/part_1/ex4/ex4.v b/part_1/ex4/ex4.v new file mode 100644 index 0000000..e92e969 --- /dev/null +++ b/part_1/ex4/ex4.v @@ -0,0 +1,16 @@ +module ex4(SW, HEX0, HEX1, HEX2, HEX3);
+
+ input [9:0] SW;
+ output [6:0] HEX0, HEX1, HEX2, HEX3;
+
+ wire [3:0] w0, w1, w2, w3;
+
+ bin2bcd_10(SW, w0, w1, w2, w3);
+
+ hex_to_7seg(HEX0, w0);
+ hex_to_7seg(HEX1, w1);
+ hex_to_7seg(HEX2, w2);
+ hex_to_7seg(HEX3, w3);
+
+
+endmodule
\ No newline at end of file diff --git a/part_1/ex4/ex4.v.bak b/part_1/ex4/ex4.v.bak new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/part_1/ex4/ex4.v.bak diff --git a/part_1/ex4/incremental_db/README b/part_1/ex4/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/part_1/ex4/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.db_info b/part_1/ex4/incremental_db/compiled_partitions/ex4.db_info new file mode 100644 index 0000000..232b71c --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 15 11:31:58 2016
diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.ammdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.ammdb Binary files differnew file mode 100644 index 0000000..afc7e0a --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.ammdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.cdb Binary files differnew file mode 100644 index 0000000..da47849 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.dfp b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.dfp Binary files differnew file mode 100644 index 0000000..b1c67d6 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.dfp diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hbdb.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hbdb.cdb Binary files differnew file mode 100644 index 0000000..808498f --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hbdb.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hbdb.hdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hbdb.hdb Binary files differnew file mode 100644 index 0000000..ab06b66 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hbdb.hdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hbdb.sig b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hdb Binary files differnew file mode 100644 index 0000000..f0eaa0a --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.hdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.logdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1
diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.rcfdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.rcfdb Binary files differnew file mode 100644 index 0000000..2f6a2c4 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.cmp.rcfdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.cdb Binary files differnew file mode 100644 index 0000000..dc62d32 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.dpi b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.dpi Binary files differnew file mode 100644 index 0000000..8c9884e --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.dpi diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.cdb Binary files differnew file mode 100644 index 0000000..7b50fb2 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.hb_info b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.hb_info Binary files differnew file mode 100644 index 0000000..8210c55 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.hb_info diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.hdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.hdb Binary files differnew file mode 100644 index 0000000..16ca30c --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.hdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.sig b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hdb Binary files differnew file mode 100644 index 0000000..5847f5b --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.hdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.kpt b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.kpt Binary files differnew file mode 100644 index 0000000..c9ac72c --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.kpt diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.olf.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.olf.cdb Binary files differnew file mode 100644 index 0000000..2b47b8d --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.olf.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.olm.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.olm.cdb Binary files differnew file mode 100644 index 0000000..38a2960 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.olm.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.oln.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.oln.cdb Binary files differnew file mode 100644 index 0000000..2c84090 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.oln.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.opi b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.opi new file mode 100644 index 0000000..56a6051 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.opi @@ -0,0 +1 @@ +1
\ No newline at end of file diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.orf.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.orf.cdb Binary files differnew file mode 100644 index 0000000..2b47b8d --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.orf.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.orm.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.orm.cdb Binary files differnew file mode 100644 index 0000000..289ca7e --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.orm.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.orn.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.orn.cdb Binary files differnew file mode 100644 index 0000000..120d1e3 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.map.orn.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.cdb Binary files differnew file mode 100644 index 0000000..dc62d32 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.hbdb.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.hbdb.cdb Binary files differnew file mode 100644 index 0000000..7b50fb2 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.hbdb.cdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.hbdb.hdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.hbdb.hdb Binary files differnew file mode 100644 index 0000000..16ca30c --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.hbdb.hdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.hdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.hdb Binary files differnew file mode 100644 index 0000000..5847f5b --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.hdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.kpt b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.kpt Binary files differnew file mode 100644 index 0000000..c9ac72c --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.root_partition.rrp.kpt diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.rrp.hdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.rrp.hdb Binary files differnew file mode 100644 index 0000000..99dfc60 --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.rrp.hdb diff --git a/part_1/ex4/incremental_db/compiled_partitions/ex4.rrs.cdb b/part_1/ex4/incremental_db/compiled_partitions/ex4.rrs.cdb Binary files differnew file mode 100644 index 0000000..0ac032e --- /dev/null +++ b/part_1/ex4/incremental_db/compiled_partitions/ex4.rrs.cdb diff --git a/part_1/ex4/output_files/ex4.asm.rpt b/part_1/ex4/output_files/ex4.asm.rpt new file mode 100644 index 0000000..57ea9f1 --- /dev/null +++ b/part_1/ex4/output_files/ex4.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for ex4
+Tue Nov 15 11:49:42 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: H:/VERI/part_1/ex4/output_files/ex4.sof
+ 6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Tue Nov 15 11:49:42 2016 ;
+; Revision Name ; ex4 ;
+; Top-level Entity Name ; ex4 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++-----------------------------------------+
+; Assembler Generated Files ;
++-----------------------------------------+
+; File Name ;
++-----------------------------------------+
+; H:/VERI/part_1/ex4/output_files/ex4.sof ;
++-----------------------------------------+
+
+
++-------------------------------------------------------------------+
+; Assembler Device Options: H:/VERI/part_1/ex4/output_files/ex4.sof ;
++----------------+--------------------------------------------------+
+; Option ; Setting ;
++----------------+--------------------------------------------------+
+; Device ; 5CSEMA5F31C6 ;
+; JTAG usercode ; 0x00B0A39D ;
+; Checksum ; 0x00B0A39D ;
++----------------+--------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 11:49:33 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex4 -c ex4
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 892 megabytes
+ Info: Processing ended: Tue Nov 15 11:49:42 2016
+ Info: Elapsed time: 00:00:09
+ Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_1/ex4/output_files/ex4.done b/part_1/ex4/output_files/ex4.done new file mode 100644 index 0000000..8f64e13 --- /dev/null +++ b/part_1/ex4/output_files/ex4.done @@ -0,0 +1 @@ +Tue Nov 15 11:49:53 2016
diff --git a/part_1/ex4/output_files/ex4.fit.rpt b/part_1/ex4/output_files/ex4.fit.rpt new file mode 100644 index 0000000..8f0c5d7 --- /dev/null +++ b/part_1/ex4/output_files/ex4.fit.rpt @@ -0,0 +1,1984 @@ +Fitter report for ex4
+Tue Nov 15 11:49:26 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. I/O Assignment Warnings
+ 6. Ignored Assignments
+ 7. Incremental Compilation Preservation Summary
+ 8. Incremental Compilation Partition Settings
+ 9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Routing Usage Summary
+ 21. I/O Rules Summary
+ 22. I/O Rules Details
+ 23. I/O Rules Matrix
+ 24. Fitter Device Options
+ 25. Operating Settings and Conditions
+ 26. Fitter Messages
+ 27. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status ; Successful - Tue Nov 15 11:49:26 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex4 ;
+; Top-level Entity Name ; ex4 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 37 / 32,070 ( < 1 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 38 / 457 ( 8 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total RAM Blocks ; 0 / 397 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
+; Optimize Hold Timing ; All Paths ; All Paths ;
+; Optimize Multi-Corner Timing ; On ; On ;
+; Auto RAM to MLAB Conversion ; On ; On ;
+; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
+; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
+; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
+; SSN Optimization ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
+; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification ; Auto ; Auto ;
+; Enable Beneficial Skew Optimization ; On ; On ;
+; Optimize Design for Metastability ; On ; On ;
+; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+; Clamping Diode ; Off ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
+; Advanced Physical Optimization ; On ; On ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.01 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.2% ;
+; Processor 3 ; 0.2% ;
+; Processor 4 ; 0.2% ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings ;
++----------+--------------------------------------+
+; Pin Name ; Reason ;
++----------+--------------------------------------+
+; HEX0[0] ; Missing drive strength and slew rate ;
+; HEX0[1] ; Missing drive strength and slew rate ;
+; HEX0[2] ; Missing drive strength and slew rate ;
+; HEX0[3] ; Missing drive strength and slew rate ;
+; HEX0[4] ; Missing drive strength and slew rate ;
+; HEX0[5] ; Missing drive strength and slew rate ;
+; HEX0[6] ; Missing drive strength and slew rate ;
+; HEX1[0] ; Missing drive strength and slew rate ;
+; HEX1[1] ; Missing drive strength and slew rate ;
+; HEX1[2] ; Missing drive strength and slew rate ;
+; HEX1[3] ; Missing drive strength and slew rate ;
+; HEX1[4] ; Missing drive strength and slew rate ;
+; HEX1[5] ; Missing drive strength and slew rate ;
+; HEX1[6] ; Missing drive strength and slew rate ;
+; HEX2[0] ; Missing drive strength and slew rate ;
+; HEX2[1] ; Missing drive strength and slew rate ;
+; HEX2[2] ; Missing drive strength and slew rate ;
+; HEX2[3] ; Missing drive strength and slew rate ;
+; HEX2[4] ; Missing drive strength and slew rate ;
+; HEX2[5] ; Missing drive strength and slew rate ;
+; HEX2[6] ; Missing drive strength and slew rate ;
+; HEX3[0] ; Missing drive strength and slew rate ;
+; HEX3[1] ; Missing drive strength and slew rate ;
+; HEX3[2] ; Missing drive strength and slew rate ;
+; HEX3[3] ; Missing drive strength and slew rate ;
+; HEX3[4] ; Missing drive strength and slew rate ;
+; HEX3[5] ; Missing drive strength and slew rate ;
+; HEX3[6] ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location ; ; ; ADC_CS ; PIN_AG20 ; QSF Assignment ;
+; Location ; ; ; ADC_SCK ; PIN_AF21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDI ; PIN_AG21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDO ; PIN_AJ21 ; QSF Assignment ;
+; Location ; ; ; CLOCK_50 ; PIN_AF14 ; QSF Assignment ;
+; Location ; ; ; DAC_CS ; PIN_AD20 ; QSF Assignment ;
+; Location ; ; ; DAC_LD ; PIN_AK21 ; QSF Assignment ;
+; Location ; ; ; DAC_SCK ; PIN_AF20 ; QSF Assignment ;
+; Location ; ; ; DAC_SDI ; PIN_AG18 ; QSF Assignment ;
+; Location ; ; ; HEX4[0] ; PIN_AA24 ; QSF Assignment ;
+; Location ; ; ; HEX4[1] ; PIN_Y23 ; QSF Assignment ;
+; Location ; ; ; HEX4[2] ; PIN_Y24 ; QSF Assignment ;
+; Location ; ; ; HEX4[3] ; PIN_W22 ; QSF Assignment ;
+; Location ; ; ; HEX4[4] ; PIN_W24 ; QSF Assignment ;
+; Location ; ; ; HEX4[5] ; PIN_V23 ; QSF Assignment ;
+; Location ; ; ; HEX4[6] ; PIN_W25 ; QSF Assignment ;
+; Location ; ; ; HEX5[0] ; PIN_V25 ; QSF Assignment ;
+; Location ; ; ; HEX5[1] ; PIN_AA28 ; QSF Assignment ;
+; Location ; ; ; HEX5[2] ; PIN_Y27 ; QSF Assignment ;
+; Location ; ; ; HEX5[3] ; PIN_AB27 ; QSF Assignment ;
+; Location ; ; ; HEX5[4] ; PIN_AB26 ; QSF Assignment ;
+; Location ; ; ; HEX5[5] ; PIN_AA26 ; QSF Assignment ;
+; Location ; ; ; HEX5[6] ; PIN_AA25 ; QSF Assignment ;
+; Location ; ; ; KEY[0] ; PIN_AA14 ; QSF Assignment ;
+; Location ; ; ; KEY[1] ; PIN_AA15 ; QSF Assignment ;
+; Location ; ; ; KEY[2] ; PIN_W15 ; QSF Assignment ;
+; Location ; ; ; KEY[3] ; PIN_Y16 ; QSF Assignment ;
+; Location ; ; ; LEDR[0] ; PIN_V16 ; QSF Assignment ;
+; Location ; ; ; LEDR[1] ; PIN_W16 ; QSF Assignment ;
+; Location ; ; ; LEDR[2] ; PIN_V17 ; QSF Assignment ;
+; Location ; ; ; LEDR[3] ; PIN_V18 ; QSF Assignment ;
+; Location ; ; ; LEDR[4] ; PIN_W17 ; QSF Assignment ;
+; Location ; ; ; LEDR[5] ; PIN_W19 ; QSF Assignment ;
+; Location ; ; ; LEDR[6] ; PIN_Y19 ; QSF Assignment ;
+; Location ; ; ; LEDR[7] ; PIN_W20 ; QSF Assignment ;
+; Location ; ; ; LEDR[8] ; PIN_W21 ; QSF Assignment ;
+; Location ; ; ; LEDR[9] ; PIN_Y21 ; QSF Assignment ;
+; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ;
+; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ;
+; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ;
+; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ;
+; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ;
+; Location ; ; ; PWM_OUT ; PIN_AJ20 ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; ADC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; ADC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; ADC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; ADC_SDO ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; CLOCK_50 ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; DAC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; DAC_LD ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; DAC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; DAC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX4[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX4[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX4[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX4[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX4[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX4[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX4[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; KEY[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; KEY[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; KEY[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; KEY[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; LEDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; LEDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; LEDR[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; LEDR[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; LEDR[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; LEDR[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; LEDR[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; LEDR[7] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; LEDR[8] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; LEDR[9] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex4 ; ; PWM_OUT ; 3.3-V LVTTL ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 143 ) ; 0.00 % ( 0 / 143 ) ; 0.00 % ( 0 / 143 ) ;
+; -- Achieved ; 0.00 % ( 0 / 143 ) ; 0.00 % ( 0 / 143 ) ; 0.00 % ( 0 / 143 ) ;
+; ; ; ; ;
+; Routing (by net) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
+; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top ; 0.00 % ( 0 / 143 ) ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in H:/VERI/part_1/ex4/output_files/ex4.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource ; Usage ; % ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 37 / 32,070 ; < 1 % ;
+; ALMs needed [=A-B+C] ; 37 ; ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 37 / 32,070 ; < 1 % ;
+; [a] ALMs used for LUT logic and registers ; 0 ; ;
+; [b] ALMs used for LUT logic ; 37 ; ;
+; [c] ALMs used for registers ; 0 ; ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
+; [B] Estimate of ALMs recoverable by dense packing ; 0 / 32,070 ; 0 % ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ;
+; [a] Due to location constrained logic ; 0 ; ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; ;
+; [c] Due to LAB input limits ; 0 ; ;
+; [d] Due to virtual I/Os ; 0 ; ;
+; ; ; ;
+; Difficulty packing design ; Low ; ;
+; ; ; ;
+; Total LABs: partially or completely used ; 7 / 3,207 ; < 1 % ;
+; -- Logic LABs ; 7 ; ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 67 ; ;
+; -- 7 input functions ; 0 ; ;
+; -- 6 input functions ; 6 ; ;
+; -- 5 input functions ; 1 ; ;
+; -- 4 input functions ; 55 ; ;
+; -- <=3 input functions ; 5 ; ;
+; Combinational ALUT usage for route-throughs ; 0 ; ;
+; Dedicated logic registers ; 0 ; ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 0 / 64,140 ; 0 % ;
+; -- Secondary logic registers ; 0 / 64,140 ; 0 % ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 0 ; ;
+; -- Routing optimization registers ; 0 ; ;
+; ; ; ;
+; Virtual pins ; 0 ; ;
+; I/O pins ; 38 / 457 ; 8 % ;
+; -- Clock pins ; 0 / 8 ; 0 % ;
+; -- Dedicated input pins ; 0 / 21 ; 0 % ;
+; ; ; ;
+; Hard processor system peripheral utilization ; ; ;
+; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
+; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
+; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
+; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
+; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
+; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
+; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
+; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
+; -- JTAG ; 0 / 1 ( 0 % ) ; ;
+; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
+; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
+; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
+; -- STM event ; 0 / 1 ( 0 % ) ; ;
+; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
+; -- DMA ; 0 / 1 ( 0 % ) ; ;
+; -- CAN ; 0 / 2 ( 0 % ) ; ;
+; -- EMAC ; 0 / 2 ( 0 % ) ; ;
+; -- I2C ; 0 / 4 ( 0 % ) ; ;
+; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
+; -- QSPI ; 0 / 1 ( 0 % ) ; ;
+; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
+; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
+; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
+; -- UART ; 0 / 2 ( 0 % ) ; ;
+; -- USB ; 0 / 2 ( 0 % ) ; ;
+; ; ; ;
+; Global signals ; 0 ; ;
+; M10K blocks ; 0 / 397 ; 0 % ;
+; Total MLAB memory bits ; 0 ; ;
+; Total block memory bits ; 0 / 4,065,280 ; 0 % ;
+; Total block memory implementation bits ; 0 / 4,065,280 ; 0 % ;
+; ; ; ;
+; Total DSP Blocks ; 0 / 87 ; 0 % ;
+; ; ; ;
+; Fractional PLLs ; 0 / 6 ; 0 % ;
+; Global clocks ; 0 / 16 ; 0 % ;
+; Quadrant clocks ; 0 / 66 ; 0 % ;
+; Horizontal periphery clocks ; 0 / 18 ; 0 % ;
+; SERDES Transmitters ; 0 / 100 ; 0 % ;
+; SERDES Receivers ; 0 / 100 ; 0 % ;
+; JTAGs ; 0 / 1 ; 0 % ;
+; ASMI blocks ; 0 / 1 ; 0 % ;
+; CRC blocks ; 0 / 1 ; 0 % ;
+; Remote update blocks ; 0 / 1 ; 0 % ;
+; Oscillator blocks ; 0 / 1 ; 0 % ;
+; Impedance control blocks ; 0 / 4 ; 0 % ;
+; Hard Memory Controllers ; 0 / 2 ; 0 % ;
+; Average interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; ;
+; Peak interconnect usage (total/H/V) ; 0.6% / 0.5% / 1.0% ; ;
+; Maximum fan-out ; 9 ; ;
+; Highest non-global fan-out ; 9 ; ;
+; Total fan-out ; 335 ; ;
+; Average fan-out ; 2.34 ; ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+; Statistic ; Top ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 37 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; ALMs needed [=A-B+C] ; 37 ; 0 ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 37 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] ALMs used for LUT logic and registers ; 0 ; 0 ;
+; [b] ALMs used for LUT logic ; 37 ; 0 ;
+; [c] ALMs used for registers ; 0 ; 0 ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
+; [B] Estimate of ALMs recoverable by dense packing ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] Due to location constrained logic ; 0 ; 0 ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
+; [c] Due to LAB input limits ; 0 ; 0 ;
+; [d] Due to virtual I/Os ; 0 ; 0 ;
+; ; ; ;
+; Difficulty packing design ; Low ; Low ;
+; ; ; ;
+; Total LABs: partially or completely used ; 7 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ;
+; -- Logic LABs ; 7 ; 0 ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 67 ; 0 ;
+; -- 7 input functions ; 0 ; 0 ;
+; -- 6 input functions ; 6 ; 0 ;
+; -- 5 input functions ; 1 ; 0 ;
+; -- 4 input functions ; 55 ; 0 ;
+; -- <=3 input functions ; 5 ; 0 ;
+; Combinational ALUT usage for route-throughs ; 0 ; 0 ;
+; Memory ALUT usage ; 0 ; 0 ;
+; -- 64-address deep ; 0 ; 0 ;
+; -- 32-address deep ; 0 ; 0 ;
+; ; ; ;
+; Dedicated logic registers ; 0 ; 0 ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 0 / 64140 ( 0 % ) ; 0 / 64140 ( 0 % ) ;
+; -- Secondary logic registers ; 0 / 64140 ( 0 % ) ; 0 / 64140 ( 0 % ) ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 0 ; 0 ;
+; -- Routing optimization registers ; 0 ; 0 ;
+; ; ; ;
+; ; ; ;
+; Virtual pins ; 0 ; 0 ;
+; I/O pins ; 38 ; 0 ;
+; I/O registers ; 0 ; 0 ;
+; Total block memory bits ; 0 ; 0 ;
+; Total block memory implementation bits ; 0 ; 0 ;
+; ; ; ;
+; Connections ; ; ;
+; -- Input Connections ; 0 ; 0 ;
+; -- Registered Input Connections ; 0 ; 0 ;
+; -- Output Connections ; 0 ; 0 ;
+; -- Registered Output Connections ; 0 ; 0 ;
+; ; ; ;
+; Internal Connections ; ; ;
+; -- Total Connections ; 335 ; 0 ;
+; -- Registered Connections ; 0 ; 0 ;
+; ; ; ;
+; External Connections ; ; ;
+; -- Top ; 0 ; 0 ;
+; -- hard_block:auto_generated_inst ; 0 ; 0 ;
+; ; ; ;
+; Partition Interface ; ; ;
+; -- Input Ports ; 10 ; 0 ;
+; -- Output Ports ; 28 ; 0 ;
+; -- Bidir Ports ; 0 ; 0 ;
+; ; ; ;
+; Registered Ports ; ; ;
+; -- Registered Input Ports ; 0 ; 0 ;
+; -- Registered Output Ports ; 0 ; 0 ;
+; ; ; ;
+; Port Connectivity ; ; ;
+; -- Input Ports driven by GND ; 0 ; 0 ;
+; -- Output Ports driven by GND ; 0 ; 0 ;
+; -- Input Ports driven by VCC ; 0 ; 0 ;
+; -- Output Ports driven by VCC ; 0 ; 0 ;
+; -- Input Ports with no Source ; 0 ; 0 ;
+; -- Output Ports with no Source ; 0 ; 0 ;
+; -- Input Ports with no Fanout ; 0 ; 0 ;
+; -- Output Ports with no Fanout ; 0 ; 0 ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; SW[0] ; AB12 ; 3A ; 12 ; 0 ; 17 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[1] ; AC12 ; 3A ; 16 ; 0 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[2] ; AF9 ; 3A ; 8 ; 0 ; 34 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[3] ; AF10 ; 3A ; 4 ; 0 ; 51 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[4] ; AD11 ; 3A ; 2 ; 0 ; 40 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[5] ; AD12 ; 3A ; 16 ; 0 ; 17 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[6] ; AE11 ; 3A ; 4 ; 0 ; 34 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[7] ; AC9 ; 3A ; 4 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[8] ; AD10 ; 3A ; 4 ; 0 ; 17 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; SW[9] ; AE12 ; 3A ; 2 ; 0 ; 57 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[0] ; AJ29 ; 5A ; 89 ; 6 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[1] ; AH29 ; 5A ; 89 ; 6 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[2] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[3] ; AG30 ; 5A ; 89 ; 16 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[4] ; AF29 ; 5A ; 89 ; 15 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[5] ; AF30 ; 5A ; 89 ; 15 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[6] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[0] ; AB23 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[1] ; AE29 ; 5B ; 89 ; 23 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[2] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[3] ; AC28 ; 5B ; 89 ; 20 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[4] ; AD30 ; 5B ; 89 ; 25 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[5] ; AC29 ; 5B ; 89 ; 20 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[6] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[0] ; AD26 ; 5A ; 89 ; 16 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[1] ; AC27 ; 5A ; 89 ; 16 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[2] ; AD25 ; 5A ; 89 ; 4 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[3] ; AC25 ; 5A ; 89 ; 4 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[4] ; AB28 ; 5B ; 89 ; 21 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[5] ; AB25 ; 5A ; 89 ; 11 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[6] ; AB22 ; 5A ; 89 ; 9 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; 3A ; 10 / 32 ( 31 % ) ; 3.3V ; -- ; 3.3V ;
+; 3B ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 5A ; 21 / 32 ( 66 % ) ; 3.3V ; -- ; 3.3V ;
+; 5B ; 7 / 16 ( 44 % ) ; 3.3V ; -- ; 3.3V ;
+; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
+; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
+; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA14 ; 122 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA15 ; 120 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA27 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB12 ; 72 ; 3A ; SW[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB14 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB22 ; 225 ; 5A ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB23 ; 227 ; 5A ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB25 ; 230 ; 5A ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB28 ; 249 ; 5B ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC9 ; 58 ; 3A ; SW[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AC10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC11 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC12 ; 82 ; 3A ; SW[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC21 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AC25 ; 215 ; 5A ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC27 ; 242 ; 5A ; HEX3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC28 ; 245 ; 5B ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC29 ; 247 ; 5B ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC30 ; 259 ; 5B ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD8 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD10 ; 56 ; 3A ; SW[8] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AD11 ; 54 ; 3A ; SW[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AD12 ; 80 ; 3A ; SW[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AD13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD25 ; 213 ; 5A ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD26 ; 240 ; 5A ; HEX3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD27 ; 222 ; 5A ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD29 ; 255 ; 5B ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD30 ; 257 ; 5B ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE11 ; 59 ; 3A ; SW[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AE12 ; 52 ; 3A ; SW[9] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE15 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE25 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE29 ; 253 ; 5B ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE30 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF7 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF9 ; 67 ; 3A ; SW[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AF10 ; 57 ; 3A ; SW[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF14 ; 114 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AF29 ; 237 ; 5A ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AF30 ; 239 ; 5A ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG4 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG30 ; 243 ; 5A ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH26 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH29 ; 218 ; 5A ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH30 ; 241 ; 5A ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ29 ; 216 ; 5A ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
+; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
+; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
+; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
+; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
+; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
+; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
+; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
+; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
+; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
+; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
+; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
+; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
+; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
+; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
+; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U23 ; ; 5B ; VCCPD5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V16 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V18 ; 194 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W15 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W16 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W17 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W19 ; 192 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W20 ; 217 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W21 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y16 ; 128 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y19 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y21 ; 219 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; Y23 ; 232 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------------------+-------------+--------------+
+; |ex4 ; 36.5 (0.5) ; 37.0 (0.5) ; 0.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 38 ; 0 ; |ex4 ; ex4 ; work ;
+; |bin2bcd_10:comb_3| ; 21.5 (0.0) ; 21.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 39 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3 ; bin2bcd_10 ; work ;
+; |add3_ge5:A1| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A1 ; add3_ge5 ; work ;
+; |add3_ge5:A10| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A10 ; add3_ge5 ; work ;
+; |add3_ge5:A11| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A11 ; add3_ge5 ; work ;
+; |add3_ge5:A12| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A12 ; add3_ge5 ; work ;
+; |add3_ge5:A2| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A2 ; add3_ge5 ; work ;
+; |add3_ge5:A3| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A3 ; add3_ge5 ; work ;
+; |add3_ge5:A4| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A4 ; add3_ge5 ; work ;
+; |add3_ge5:A5| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A5 ; add3_ge5 ; work ;
+; |add3_ge5:A6| ; 4.0 (4.0) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A6 ; add3_ge5 ; work ;
+; |add3_ge5:A7| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A7 ; add3_ge5 ; work ;
+; |add3_ge5:A8| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A8 ; add3_ge5 ; work ;
+; |add3_ge5:A9| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A9 ; add3_ge5 ; work ;
+; |hex_to_7seg:comb_4| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|hex_to_7seg:comb_4 ; hex_to_7seg ; work ;
+; |hex_to_7seg:comb_5| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|hex_to_7seg:comb_5 ; hex_to_7seg ; work ;
+; |hex_to_7seg:comb_6| ; 7.5 (7.5) ; 8.0 (8.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex4|hex_to_7seg:comb_6 ; hex_to_7seg ; work ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; SW[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[6] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[7] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[8] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[9] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++-------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++-------------------------------------------------+-------------------+---------+
+; SW[0] ; ; ;
+; - hex_to_7seg:comb_4|WideOr6~0 ; 0 ; 0 ;
+; - hex_to_7seg:comb_4|WideOr5~0 ; 0 ; 0 ;
+; - hex_to_7seg:comb_4|WideOr4~0 ; 0 ; 0 ;
+; - hex_to_7seg:comb_4|WideOr3~0 ; 0 ; 0 ;
+; - hex_to_7seg:comb_4|WideOr2~0 ; 0 ; 0 ;
+; - hex_to_7seg:comb_4|WideOr1~0 ; 0 ; 0 ;
+; - hex_to_7seg:comb_4|WideOr0~0 ; 0 ; 0 ;
+; SW[1] ; ; ;
+; - bin2bcd_10:comb_3|add3_ge5:A12|WideOr3~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A12|WideOr2~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A12|WideOr1~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A12|WideOr0~0 ; 0 ; 0 ;
+; SW[2] ; ; ;
+; - bin2bcd_10:comb_3|add3_ge5:A9|WideOr3~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A9|WideOr2~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A9|WideOr1~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A9|WideOr0~0 ; 0 ; 0 ;
+; SW[3] ; ; ;
+; - bin2bcd_10:comb_3|add3_ge5:A7|WideOr3~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A7|WideOr2~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A7|WideOr1~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A7|WideOr0~0 ; 1 ; 0 ;
+; SW[4] ; ; ;
+; - bin2bcd_10:comb_3|add3_ge5:A5|WideOr3~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A5|WideOr2~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A5|WideOr1~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A5|WideOr0~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr0~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr1~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr2~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr3~0 ; 1 ; 0 ;
+; SW[5] ; ; ;
+; - bin2bcd_10:comb_3|add3_ge5:A3|WideOr3~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A3|WideOr2~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A3|WideOr1~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A3|WideOr0~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr0~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr1~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr2~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr3~0 ; 1 ; 0 ;
+; SW[6] ; ; ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr0~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr1~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr2~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr3~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr0~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr1~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr2~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr3~0 ; 1 ; 0 ;
+; SW[7] ; ; ;
+; - bin2bcd_10:comb_3|add3_ge5:A1|WideOr0~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr0~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr1~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr2~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr3~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr0~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr1~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr2~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr3~0 ; 0 ; 0 ;
+; SW[8] ; ; ;
+; - bin2bcd_10:comb_3|add3_ge5:A1|WideOr0~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr0~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr1~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr2~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr3~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr0~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr1~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr2~0 ; 1 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr3~0 ; 1 ; 0 ;
+; SW[9] ; ; ;
+; - bin2bcd_10:comb_3|add3_ge5:A1|WideOr0~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr0~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr1~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr2~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A6|WideOr3~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr0~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr1~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr2~0 ; 0 ; 0 ;
+; - bin2bcd_10:comb_3|add3_ge5:A2|WideOr3~0 ; 0 ; 0 ;
++-------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------+
+; Routing Usage Summary ;
++---------------------------------------------+------------------------+
+; Routing Resource Type ; Usage ;
++---------------------------------------------+------------------------+
+; Block interconnects ; 68 / 289,320 ( < 1 % ) ;
+; C12 interconnects ; 15 / 13,420 ( < 1 % ) ;
+; C2 interconnects ; 23 / 119,108 ( < 1 % ) ;
+; C4 interconnects ; 42 / 56,300 ( < 1 % ) ;
+; DQS bus muxes ; 0 / 25 ( 0 % ) ;
+; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
+; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
+; Direct links ; 15 / 289,320 ( < 1 % ) ;
+; Global clocks ; 0 / 16 ( 0 % ) ;
+; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
+; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
+; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
+; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
+; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
+; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
+; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
+; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
+; Local interconnects ; 25 / 84,580 ( < 1 % ) ;
+; Quadrant clocks ; 0 / 66 ( 0 % ) ;
+; R14 interconnects ; 54 / 12,676 ( < 1 % ) ;
+; R14/C12 interconnect drivers ; 59 / 20,720 ( < 1 % ) ;
+; R3 interconnects ; 28 / 130,992 ( < 1 % ) ;
+; R6 interconnects ; 33 / 266,960 ( < 1 % ) ;
+; Spine clocks ; 0 / 360 ( 0 % ) ;
+; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
++---------------------------------------------+------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary ;
++----------------------------------+-------+
+; I/O Rules Statistic ; Total ;
++----------------------------------+-------+
+; Total I/O Rules ; 28 ;
+; Number of I/O Rules Passed ; 6 ;
+; Number of I/O Rules Failed ; 0 ;
+; Number of I/O Rules Unchecked ; 0 ;
+; Number of I/O Rules Inapplicable ; 22 ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
+; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
+; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
+; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass ; 38 ; 0 ; 38 ; 0 ; 0 ; 38 ; 38 ; 0 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Inapplicable ; 0 ; 38 ; 0 ; 38 ; 38 ; 0 ; 0 ; 38 ; 0 ; 0 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ;
+; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options ;
++------------------------------------------------------------------+-----------------------------+
+; Option ; Setting ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Passive Serial ;
+; Enable Error Detection CRC_ERROR pin ; Off ;
+; Enable CvP_CONFDONE pin ; Off ;
+; Enable open drain on CRC_ERROR pin ; On ;
+; Enable open drain on CvP_CONFDONE pin ; On ;
+; Enable open drain on INIT_DONE pin ; On ;
+; Enable open drain on Partial Reconfiguration pins ; Off ;
+; Enable open drain on nCEO pin ; On ;
+; Enable Partial Reconfiguration pins ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ;
+; Enable internal scrubbing ; Off ;
+; Active Serial clock source ; 100 MHz Internal Oscillator ;
+; Device initialization clock source ; Internal Oscillator ;
+; Configuration via Protocol ; Off ;
+; Configuration Voltage Level ; Auto ;
+; Force Configuration Voltage Level ; Off ;
+; Enable nCEO output ; Off ;
+; Data[15..8] ; Unreserved ;
+; Data[7..5] ; Unreserved ;
+; Base pin-out file on sameframe device ; Off ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.10 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex4"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (184020): Starting Fitter periphery placement operations
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+ Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+ Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
+Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info (170201): Optimizations that may affect the design's routability were skipped
+ Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.08 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file H:/VERI/part_1/ex4/output_files/ex4.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 49 warnings
+ Info: Peak virtual memory: 2581 megabytes
+ Info: Processing ended: Tue Nov 15 11:49:28 2016
+ Info: Elapsed time: 00:00:31
+ Info: Total CPU time (on all processors): 00:00:49
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in H:/VERI/part_1/ex4/output_files/ex4.fit.smsg.
+
+
diff --git a/part_1/ex4/output_files/ex4.fit.smsg b/part_1/ex4/output_files/ex4.fit.smsg new file mode 100644 index 0000000..43eead5 --- /dev/null +++ b/part_1/ex4/output_files/ex4.fit.smsg @@ -0,0 +1,6 @@ +Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_1/ex4/output_files/ex4.fit.summary b/part_1/ex4/output_files/ex4.fit.summary new file mode 100644 index 0000000..99e1f91 --- /dev/null +++ b/part_1/ex4/output_files/ex4.fit.summary @@ -0,0 +1,20 @@ +Fitter Status : Successful - Tue Nov 15 11:49:26 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex4
+Top-level Entity Name : ex4
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 37 / 32,070 ( < 1 % )
+Total registers : 0
+Total pins : 38 / 457 ( 8 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_1/ex4/output_files/ex4.flow.rpt b/part_1/ex4/output_files/ex4.flow.rpt new file mode 100644 index 0000000..f4af68b --- /dev/null +++ b/part_1/ex4/output_files/ex4.flow.rpt @@ -0,0 +1,128 @@ +Flow report for ex4
+Tue Nov 15 11:49:51 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+ 8. Flow Messages
+ 9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary ;
++---------------------------------+-------------------------------------------------+
+; Flow Status ; Successful - Tue Nov 15 11:49:42 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex4 ;
+; Top-level Entity Name ; ex4 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 37 / 32,070 ( < 1 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 38 / 457 ( 8 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 11/15/2016 11:48:43 ;
+; Main task ; Compilation ;
+; Revision Name ; ex4 ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 260248564170200.147921052310088 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
+; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 883 MB ; 00:00:21 ;
+; Fitter ; 00:00:29 ; 1.0 ; 2581 MB ; 00:00:48 ;
+; Assembler ; 00:00:09 ; 1.0 ; 892 MB ; 00:00:06 ;
+; TimeQuest Timing Analyzer ; 00:00:08 ; 1.0 ; 1202 MB ; 00:00:06 ;
+; Total ; 00:00:57 ; -- ; -- ; 00:01:21 ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; Fitter ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; Assembler ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
+; TimeQuest Timing Analyzer ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex4 -c ex4
+quartus_fit --read_settings_files=off --write_settings_files=off ex4 -c ex4
+quartus_asm --read_settings_files=off --write_settings_files=off ex4 -c ex4
+quartus_sta ex4 -c ex4
+
+
+
diff --git a/part_1/ex4/output_files/ex4.jdi b/part_1/ex4/output_files/ex4.jdi new file mode 100644 index 0000000..f1b7624 --- /dev/null +++ b/part_1/ex4/output_files/ex4.jdi @@ -0,0 +1,8 @@ +<sld_project_info>
+ <project>
+ <hash md5_digest_80b="0e0c9b8e7c1371a24e40"/>
+ </project>
+ <file_info>
+ <file device="5CSEMA5F31C6" path="ex4.sof" usercode="0xFFFFFFFF"/>
+ </file_info>
+</sld_project_info>
diff --git a/part_1/ex4/output_files/ex4.map.rpt b/part_1/ex4/output_files/ex4.map.rpt new file mode 100644 index 0000000..e27ce18 --- /dev/null +++ b/part_1/ex4/output_files/ex4.map.rpt @@ -0,0 +1,364 @@ +Analysis & Synthesis report for ex4
+Tue Nov 15 11:48:55 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Source Files Read
+ 6. Analysis & Synthesis Resource Usage Summary
+ 7. Analysis & Synthesis Resource Utilization by Entity
+ 8. General Register Statistics
+ 9. Port Connectivity Checks: "bin2bcd_10:comb_3|add3_ge5:A10"
+ 10. Port Connectivity Checks: "bin2bcd_10:comb_3|add3_ge5:A4"
+ 11. Port Connectivity Checks: "bin2bcd_10:comb_3|add3_ge5:A1"
+ 12. Post-Synthesis Netlist Statistics for Top Partition
+ 13. Elapsed Time Per Partition
+ 14. Analysis & Synthesis Messages
+ 15. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Tue Nov 15 11:48:55 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex4 ;
+; Top-level Entity Name ; ex4 ;
+; Family ; Cyclone V ;
+; Logic utilization (in ALMs) ; N/A ;
+; Total registers ; 0 ;
+; Total pins ; 38 ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 ;
+; Total DSP Blocks ; 0 ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Top-level entity name ; ex4 ; ex4 ;
+; Family name ; Cyclone V ; Cyclone V ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Infer RAMs from Raw Logic ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; On ; On ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 3 ; 3 ;
+; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
+; Synthesis Seed ; 1 ; 1 ;
+; Automatic Parallel Synthesis ; On ; On ;
+; Partial Reconfiguration Bitstream ID ; Off ; Off ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 1 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------+------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------+------------------------------------------------+---------+
+; verilog_files/hex_to_7seg.v ; yes ; User Verilog HDL File ; H:/VERI/part_1/ex4/verilog_files/hex_to_7seg.v ; ;
+; verilog_files/bin2bcd_10.v ; yes ; User Verilog HDL File ; H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v ; ;
+; ex4.v ; yes ; User Verilog HDL File ; H:/VERI/part_1/ex4/ex4.v ; ;
+; verilog_files/add3_ge5.v ; yes ; User Verilog HDL File ; H:/VERI/part_1/ex4/verilog_files/add3_ge5.v ; ;
++----------------------------------+-----------------+------------------------+------------------------------------------------+---------+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+-----------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+-----------------------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 36 ;
+; ; ;
+; Combinational ALUT usage for logic ; 66 ;
+; -- 7 input functions ; 0 ;
+; -- 6 input functions ; 6 ;
+; -- 5 input functions ; 1 ;
+; -- 4 input functions ; 55 ;
+; -- <=3 input functions ; 4 ;
+; ; ;
+; Dedicated logic registers ; 0 ;
+; ; ;
+; I/O pins ; 38 ;
+; ; ;
+; Total DSP Blocks ; 0 ;
+; ; ;
+; Maximum fan-out node ; bin2bcd_10:comb_3|add3_ge5:A8|WideOr0~0 ;
+; Maximum fan-out ; 9 ;
+; Total fan-out ; 335 ;
+; Average fan-out ; 2.36 ;
++---------------------------------------------+-----------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+-------------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+-------------------------------------+-------------+--------------+
+; |ex4 ; 66 (0) ; 0 (0) ; 0 ; 0 ; 38 ; 0 ; |ex4 ; ex4 ; work ;
+; |bin2bcd_10:comb_3| ; 39 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3 ; bin2bcd_10 ; work ;
+; |add3_ge5:A10| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A10 ; add3_ge5 ; work ;
+; |add3_ge5:A11| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A11 ; add3_ge5 ; work ;
+; |add3_ge5:A12| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A12 ; add3_ge5 ; work ;
+; |add3_ge5:A1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A1 ; add3_ge5 ; work ;
+; |add3_ge5:A2| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A2 ; add3_ge5 ; work ;
+; |add3_ge5:A3| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A3 ; add3_ge5 ; work ;
+; |add3_ge5:A4| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A4 ; add3_ge5 ; work ;
+; |add3_ge5:A5| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A5 ; add3_ge5 ; work ;
+; |add3_ge5:A6| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A6 ; add3_ge5 ; work ;
+; |add3_ge5:A7| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A7 ; add3_ge5 ; work ;
+; |add3_ge5:A8| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A8 ; add3_ge5 ; work ;
+; |add3_ge5:A9| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|bin2bcd_10:comb_3|add3_ge5:A9 ; add3_ge5 ; work ;
+; |hex_to_7seg:comb_4| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|hex_to_7seg:comb_4 ; hex_to_7seg ; work ;
+; |hex_to_7seg:comb_5| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|hex_to_7seg:comb_5 ; hex_to_7seg ; work ;
+; |hex_to_7seg:comb_6| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex4|hex_to_7seg:comb_6 ; hex_to_7seg ; work ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+-------------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 0 ;
+; Number of registers using Synchronous Clear ; 0 ;
+; Number of registers using Synchronous Load ; 0 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 0 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_10:comb_3|add3_ge5:A10" ;
++------+-------+----------+----------------------------------+
+; Port ; Type ; Severity ; Details ;
++------+-------+----------+----------------------------------+
+; w[3] ; Input ; Info ; Stuck at GND ;
++------+-------+----------+----------------------------------+
+
+
++-----------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_10:comb_3|add3_ge5:A4" ;
++------+-------+----------+---------------------------------+
+; Port ; Type ; Severity ; Details ;
++------+-------+----------+---------------------------------+
+; w[3] ; Input ; Info ; Stuck at GND ;
++------+-------+----------+---------------------------------+
+
+
++-----------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_10:comb_3|add3_ge5:A1" ;
++------+-------+----------+---------------------------------+
+; Port ; Type ; Severity ; Details ;
++------+-------+----------+---------------------------------+
+; w[3] ; Input ; Info ; Stuck at GND ;
++------+-------+----------+---------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type ; Count ;
++-----------------------+-----------------------------+
+; arriav_lcell_comb ; 76 ;
+; normal ; 76 ;
+; 0 data inputs ; 2 ;
+; 1 data inputs ; 8 ;
+; 2 data inputs ; 1 ;
+; 3 data inputs ; 3 ;
+; 4 data inputs ; 55 ;
+; 5 data inputs ; 1 ;
+; 6 data inputs ; 6 ;
+; boundary_port ; 38 ;
+; ; ;
+; Max LUT depth ; 9.00 ;
+; Average LUT depth ; 7.52 ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top ; 00:00:00 ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 11:48:42 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex4 -c ex4
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+ Info (12023): Found entity 1: hex_to_7seg File: H:/VERI/part_1/ex4/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+ Info (12023): Found entity 1: bin2bcd_16 File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_10.v
+ Info (12023): Found entity 1: bin2bcd_10 File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file ex4.v
+ Info (12023): Found entity 1: ex4 File: H:/VERI/part_1/ex4/ex4.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+ Info (12023): Found entity 1: add3_ge5 File: H:/VERI/part_1/ex4/verilog_files/add3_ge5.v Line: 1
+Critical Warning (10846): Verilog HDL Instantiation warning at ex4.v(8): instance has no name File: H:/VERI/part_1/ex4/ex4.v Line: 8
+Critical Warning (10846): Verilog HDL Instantiation warning at ex4.v(10): instance has no name File: H:/VERI/part_1/ex4/ex4.v Line: 10
+Critical Warning (10846): Verilog HDL Instantiation warning at ex4.v(11): instance has no name File: H:/VERI/part_1/ex4/ex4.v Line: 11
+Critical Warning (10846): Verilog HDL Instantiation warning at ex4.v(12): instance has no name File: H:/VERI/part_1/ex4/ex4.v Line: 12
+Critical Warning (10846): Verilog HDL Instantiation warning at ex4.v(13): instance has no name File: H:/VERI/part_1/ex4/ex4.v Line: 13
+Info (12127): Elaborating entity "ex4" for the top level hierarchy
+Info (12128): Elaborating entity "bin2bcd_10" for hierarchy "bin2bcd_10:comb_3" File: H:/VERI/part_1/ex4/ex4.v Line: 8
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_10:comb_3|add3_ge5:A1" File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 11
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:comb_4" File: H:/VERI/part_1/ex4/ex4.v Line: 10
+Warning (13024): Output pins are stuck at VCC or GND
+ Warning (13410): Pin "HEX3[1]" is stuck at GND File: H:/VERI/part_1/ex4/ex4.v Line: 4
+ Warning (13410): Pin "HEX3[2]" is stuck at GND File: H:/VERI/part_1/ex4/ex4.v Line: 4
+ Warning (13410): Pin "HEX3[6]" is stuck at VCC File: H:/VERI/part_1/ex4/ex4.v Line: 4
+Info (286030): Timing-Driven Synthesis is running
+Info (144001): Generated suppressed messages file H:/VERI/part_1/ex4/output_files/ex4.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+ Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 104 device resources after synthesis - the final resource count might be different
+ Info (21058): Implemented 10 input pins
+ Info (21059): Implemented 28 output pins
+ Info (21061): Implemented 66 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 10 warnings
+ Info: Peak virtual memory: 883 megabytes
+ Info: Processing ended: Tue Nov 15 11:48:55 2016
+ Info: Elapsed time: 00:00:13
+ Info: Total CPU time (on all processors): 00:00:22
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in H:/VERI/part_1/ex4/output_files/ex4.map.smsg.
+
+
diff --git a/part_1/ex4/output_files/ex4.map.smsg b/part_1/ex4/output_files/ex4.map.smsg new file mode 100644 index 0000000..e8dac42 --- /dev/null +++ b/part_1/ex4/output_files/ex4.map.smsg @@ -0,0 +1,41 @@ +Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a1" differs only in case from object "A1" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a2" differs only in case from object "A2" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a3" differs only in case from object "A3" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a4" differs only in case from object "A4" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a5" differs only in case from object "A5" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a6" differs only in case from object "A6" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a7" differs only in case from object "A7" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a8" differs only in case from object "A8" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a9" differs only in case from object "A9" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a10" differs only in case from object "A10" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a11" differs only in case from object "A11" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_10.v(7): object "a12" differs only in case from object "A12" in the same scope File: H:/VERI/part_1/ex4/verilog_files/bin2bcd_10.v Line: 7
diff --git a/part_1/ex4/output_files/ex4.map.summary b/part_1/ex4/output_files/ex4.map.summary new file mode 100644 index 0000000..2ae37e5 --- /dev/null +++ b/part_1/ex4/output_files/ex4.map.summary @@ -0,0 +1,17 @@ +Analysis & Synthesis Status : Successful - Tue Nov 15 11:48:55 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex4
+Top-level Entity Name : ex4
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 0
+Total pins : 38
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_1/ex4/output_files/ex4.pin b/part_1/ex4/output_files/ex4.pin new file mode 100644 index 0000000..2e84297 --- /dev/null +++ b/part_1/ex4/output_files/ex4.pin @@ -0,0 +1,976 @@ + -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other
+ -- applicable license agreement, including, without limitation,
+ -- that your use is for the sole purpose of programming logic
+ -- devices manufactured by Altera and sold by Altera or its
+ -- authorized distributors. Please refer to the applicable
+ -- agreement for further details.
+ --
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 3A: 3.3V
+ -- Bank 3B: 2.5V
+ -- Bank 4A: 2.5V
+ -- Bank 5A: 3.3V
+ -- Bank 5B: 3.3V
+ -- Bank 6B: 2.5V
+ -- Bank 6A: 2.5V
+ -- Bank 7A: 2.5V
+ -- Bank 7B: 2.5V
+ -- Bank 7C: 2.5V
+ -- Bank 7D: 2.5V
+ -- Bank 8A: 2.5V
+ -- RREF : External reference resistor for the quad, MUST be connected to
+ -- GND via a 2k Ohm resistor.
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
+ -- must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP "ex4" ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A :
+VCCIO8A : A7 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A :
+GND : A12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C :
+GND : A17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B :
+GND : A22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A :
+GND : A26 : : : : 7A :
+GND : A27 : gnd : : : :
+HPS_TRST : A28 : : : : 7A :
+HPS_TMS : A29 : : : : 7A :
+GND : AA1 : gnd : : : :
+GND : AA2 : gnd : : : :
+GND : AA3 : gnd : : : :
+GND : AA4 : gnd : : : :
+VCC : AA5 : power : : 1.1V : :
+GND : AA6 : gnd : : : :
+DNU : AA7 : : : : :
+VCCA_FPLL : AA8 : power : : 2.5V : :
+GND : AA9 : gnd : : : :
+VCCPD3A : AA10 : power : : 3.3V : 3A :
+GND : AA11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
+VCCIO4A : AA17 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
+GND : AA22 : gnd : : : :
+VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
+VCCIO5B : AA27 : power : : 3.3V : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 5B :
+VREFB5BN0 : AA29 : power : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B :
+GND : AB1 : gnd : : : :
+GND : AB2 : gnd : : : :
+DNU : AB3 : : : : :
+DNU : AB4 : : : : :
+GND : AB5 : gnd : : : :
+VCCA_FPLL : AB6 : power : : 2.5V : :
+GND : AB7 : gnd : : : :
+nCSO, DATA4 : AB8 : : : : 3A :
+TDO : AB9 : output : : : 3A :
+VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX : AB11 : power : : 2.5V : :
+SW[0] : AB12 : input : 3.3-V LVTTL : : 3A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B :
+VCCIO3B : AB14 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B :
+VCC_AUX : AB16 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
+VCCPD3B4A : AB18 : power : : 2.5V : 3B, 4A :
+GND : AB19 : gnd : : : :
+VCCPD3B4A : AB20 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A :
+HEX3[6] : AB22 : output : 3.3-V LVTTL : : 5A : Y
+HEX2[0] : AB23 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AB24 : power : : 3.3V : 5A :
+HEX3[5] : AB25 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5B :
+HEX3[4] : AB28 : output : 3.3-V LVTTL : : 5B : Y
+GND : AB29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B :
+GND : AC1 : gnd : : : :
+GND : AC2 : gnd : : : :
+GND : AC3 : gnd : : : :
+GND : AC4 : gnd : : : :
+TCK : AC5 : input : : : 3A :
+GND : AC6 : gnd : : : :
+AS_DATA3, DATA3 : AC7 : : : : 3A :
+GND : AC8 : gnd : : : :
+SW[7] : AC9 : input : 3.3-V LVTTL : : 3A : Y
+VCCPD3A : AC10 : power : : 3.3V : 3A :
+VCCIO3A : AC11 : power : : 3.3V : 3A :
+SW[1] : AC12 : input : 3.3-V LVTTL : : 3A : Y
+VCCPD3B4A : AC13 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3B :
+VCCPD3B4A : AC15 : power : : 2.5V : 3B, 4A :
+GND : AC16 : gnd : : : :
+VCCPD3B4A : AC17 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
+VCCPD3B4A : AC19 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
+VCCIO4A : AC21 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
+VREFB5AN0 : AC24 : power : : : 5A :
+HEX3[3] : AC25 : output : 3.3-V LVTTL : : 5A : Y
+GND : AC26 : gnd : : : :
+HEX3[1] : AC27 : output : 3.3-V LVTTL : : 5A : Y
+HEX2[3] : AC28 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[5] : AC29 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[6] : AC30 : output : 3.3-V LVTTL : : 5B : Y
+GND : AD1 : gnd : : : :
+GND : AD2 : gnd : : : :
+DNU : AD3 : : : : :
+DNU : AD4 : : : : :
+GND : AD5 : gnd : : : :
+VREFB3AN0 : AD6 : power : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
+VCCIO3A : AD8 : power : : 3.3V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A :
+SW[8] : AD10 : input : 3.3-V LVTTL : : 3A : Y
+SW[4] : AD11 : input : 3.3-V LVTTL : : 3A : Y
+SW[5] : AD12 : input : 3.3-V LVTTL : : 3A : Y
+VCCIO3B : AD13 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B :
+DNU : AD15 : : : : :
+VCCPD3B4A : AD16 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
+VCCIO4A : AD18 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
+VCC_AUX : AD22 : power : : 2.5V : :
+GND : AD23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A :
+HEX3[2] : AD25 : output : 3.3-V LVTTL : : 5A : Y
+HEX3[0] : AD26 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[6] : AD27 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AD28 : power : : 3.3V : 5A :
+HEX2[2] : AD29 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[4] : AD30 : output : 3.3-V LVTTL : : 5B : Y
+GND : AE1 : gnd : : : :
+GND : AE2 : gnd : : : :
+GND : AE3 : gnd : : : :
+GND : AE4 : gnd : : : :
+AS_DATA1, DATA1 : AE5 : : : : 3A :
+AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3A :
+AS_DATA2, DATA2 : AE8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3A :
+GND : AE10 : gnd : : : :
+SW[6] : AE11 : input : 3.3-V LVTTL : : 3A : Y
+SW[9] : AE12 : input : 3.3-V LVTTL : : 3A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B :
+VCCIO3B : AE15 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
+GND : AE20 : gnd : : : :
+VCCPD3B4A : AE21 : power : : 2.5V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
+VCCIO4A : AE25 : power : : 2.5V : 4A :
+HEX0[0] : AE26 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[1] : AE27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[2] : AE28 : output : 3.3-V LVTTL : : 5A : Y
+HEX2[1] : AE29 : output : 3.3-V LVTTL : : 5B : Y
+VCCIO5B : AE30 : power : : 3.3V : 5B :
+GND : AF1 : gnd : : : :
+GND : AF2 : gnd : : : :
+GND : AF3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A :
+VCCIO3A : AF7 : power : : 3.3V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A :
+SW[2] : AF9 : input : 3.3-V LVTTL : : 3A : Y
+SW[3] : AF10 : input : 3.3-V LVTTL : : 3A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
+GND : AF12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
+GND : AF17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
+VCCIO4A : AF22 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A :
+GND : AF27 : gnd : : : :
+HEX0[4] : AF28 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[4] : AF29 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[5] : AF30 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A :
+VCCIO3A : AG4 : power : : 3.3V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3A :
+GND : AG9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B :
+GND : AG14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
+VCCIO4A : AG19 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
+GND : AG24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
+HEX0[3] : AG27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[5] : AG28 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AG29 : power : : 3.3V : 5A :
+HEX1[3] : AG30 : output : 3.3-V LVTTL : : 5A : Y
+GND : AH1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A :
+GND : AH6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3B :
+GND : AH11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15 : : : : 3B :
+VCCIO4A : AH16 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A :
+GND : AH21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4A :
+VCCIO4A : AH26 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
+HEX0[6] : AH28 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[1] : AH29 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[2] : AH30 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2 : : : : 3A :
+GND : AJ3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B :
+VCCIO3B : AJ8 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B :
+VCCIO3B : AJ13 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B :
+VREFB3BN0 : AJ15 : power : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A :
+GND : AJ18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 4A :
+VCCIO4A : AJ23 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A :
+GND : AJ28 : gnd : : : :
+HEX1[0] : AJ29 : output : 3.3-V LVTTL : : 5A : Y
+GND : AJ30 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4 : : : : 3B :
+GND : AK5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B :
+VCCIO3B : AK10 : power : : 2.5V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B :
+GND : AK15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A :
+VREFB4AN0 : AK17 : power : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A :
+VCCIO4A : AK20 : power : : 2.5V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A :
+GND : AK25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A :
+VCCIO8A : B4 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A :
+GND : B9 : gnd : : : :
+VREFB8AN0 : B10 : power : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A :
+GND : B14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B :
+GND : B19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A :
+GND : B24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A :
+HPS_TDI : B27 : : : : 7A :
+HPS_TDO : B28 : : : : 7A :
+GND : B29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A :
+GND : C1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A :
+GND : C6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A :
+VCCIO8A : C11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D :
+GND : C16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B :
+GND : C21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A :
+GND : C26 : gnd : : : :
+HPS_nRST : C27 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A :
+GND : D3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
+VCCIO8A : D8 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
+GND : D13 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C :
+VCCIO7C_HPS : D18 : power : : 2.5V : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A :
+GND : D23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A :
+HPS_CLK1 : D25 : : : : 7A :
+GND : D26 : : : : 7A :
+HPS_RZQ_0 : D27 : : : : 6A :
+VCCIO6A_HPS : D28 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A :
+VCCIO8A : E5 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
+GND : E10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D :
+VCCIO7D_HPS : E15 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B :
+VCCIO7B_HPS : E20 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B :
+VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A :
+GND : E25 : gnd : : : :
+DNU : E26 : : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A :
+GND : E30 : gnd : : : :
+DNU : F1 : : : : :
+GND : F2 : gnd : : : :
+CONF_DONE : F3 : : : : 9A :
+nSTATUS : F4 : : : : 9A :
+GND : F5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
+GND : F7 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A :
+VCCIO8A : F12 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D :
+GND : F17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B :
+VCCIO7A_HPS : F22 : power : : 2.5V : 7A :
+HPS_nPOR : F23 : : : : 7A :
+HPS_PORSEL : F24 : : : : 7A :
+HPS_CLK2 : F25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
+GND : F27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A :
+GND : G1 : : : : :
+DNU : G2 : : : : :
+GND : G3 : gnd : : : :
+GND : G4 : gnd : : : :
+nCE : G5 : : : : 9A :
+MSEL2 : G6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8A :
+VCCIO8A : G9 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A :
+VCCIO8A : G14 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C :
+VCCIO7B_HPS : G19 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A :
+VCCRSTCLK_HPS : G23 : : : : 7A :
+GND : G24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
+VCCIO6A_HPS : G29 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A :
+GND : H1 : gnd : : : :
+GND : H2 : gnd : : : :
+DNU : H3 : : : : :
+DNU : H4 : : : : :
+GND : H5 : gnd : : : :
+VCCIO8A : H6 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
+VCCBAT : H9 : power : : 1.2V : :
+VCC_AUX : H10 : power : : 2.5V : :
+GND : H11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A :
+VCCIO7D_HPS : H16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A :
+VCCIO7A_HPS : H21 : power : : 2.5V : 7A :
+HPS_TCK : H22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
+VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A :
+GND : J1 : gnd : : : :
+GND : J2 : gnd : : : :
+GND : J3 : gnd : : : :
+GND : J4 : gnd : : : :
+nCONFIG : J5 : : : : 9A :
+GND : J6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
+GND : J8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
+VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A :
+VCCIO8A : J13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8A :
+DNU : J15 : : : : :
+VCC_AUX : J16 : power : : 2.5V : :
+VCCPD7C_HPS : J17 : power : : 2.5V : 7C :
+GND : J18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B :
+VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX_SHARED : J21 : power : : 2.5V : :
+GND : J22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
+GND : J28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A :
+GND : K1 : gnd : : : :
+GND : K2 : gnd : : : :
+DNU : K3 : : : : :
+DNU : K4 : : : : :
+GND : K5 : gnd : : : :
+MSEL1 : K6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
+VCCA_FPLL : K9 : power : : 2.5V : :
+GND : K10 : gnd : : : :
+VCCPD8A : K11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 8A :
+VCCPD8A : K13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A :
+GND : K15 : gnd : : : :
+VCCPD7D_HPS : K16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B :
+VCCPD7B_HPS : K18 : power : : 2.5V : 7B :
+VCCPD7A_HPS : K19 : power : : 2.5V : 7A :
+GND : K20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
+VCCIO6A_HPS : K24 : power : : 2.5V : 6A :
+GND : K25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A :
+VCCIO6A_HPS : K30 : power : : 2.5V : 6A :
+GND : L1 : gnd : : : :
+GND : L2 : gnd : : : :
+GND : L3 : gnd : : : :
+GND : L4 : gnd : : : :
+VCC : L5 : power : : 1.1V : :
+GND : L6 : gnd : : : :
+MSEL3 : L7 : : : : 9A :
+MSEL0 : L8 : : : : 9A :
+MSEL4 : L9 : : : : 9A :
+VCCPD8A : L10 : power : : 2.5V : 8A :
+GND : L11 : gnd : : : :
+VCCPD8A : L12 : power : : 2.5V : 8A :
+GND : L13 : gnd : : : :
+VCCPD8A : L14 : power : : 2.5V : 8A :
+GND : L15 : gnd : : : :
+VCC_HPS : L16 : power : : 1.1V : :
+GND : L17 : gnd : : : :
+VCC_HPS : L18 : power : : 1.1V : :
+GND : L19 : gnd : : : :
+VCC_HPS : L20 : power : : 1.1V : :
+VCCPLL_HPS : L21 : power : : 2.5V : :
+GND : L22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A :
+VCCIO6A_HPS : L27 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A :
+GND : M1 : gnd : : : :
+GND : M2 : gnd : : : :
+DNU : M3 : : : : :
+DNU : M4 : : : : :
+GND : M5 : gnd : : : :
+VCC : M6 : power : : 1.1V : :
+GND : M7 : gnd : : : :
+GND : M8 : gnd : : : :
+VCC : M9 : power : : 1.1V : :
+GND : M10 : gnd : : : :
+VCC : M11 : power : : 1.1V : :
+GND : M12 : gnd : : : :
+VCC : M13 : power : : 1.1V : :
+GND : M14 : gnd : : : :
+VCC_HPS : M15 : power : : 1.1V : :
+GND : M16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D :
+GND : M18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A :
+GND : M20 : gnd : : : :
+VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A :
+VCCIO6A_HPS : M24 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
+GND : M29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A :
+GND : N1 : gnd : : : :
+GND : N2 : gnd : : : :
+GND : N3 : gnd : : : :
+GND : N4 : gnd : : : :
+VCC : N5 : power : : 1.1V : :
+GND : N6 : gnd : : : :
+VCCA_FPLL : N7 : power : : 2.5V : :
+GND : N8 : gnd : : : :
+GND : N9 : gnd : : : :
+VCC : N10 : power : : 1.1V : :
+GND : N11 : gnd : : : :
+VCC : N12 : power : : 1.1V : :
+GND : N13 : gnd : : : :
+VCC : N14 : power : : 1.1V : :
+GND : N15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D :
+GND : N17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A :
+GND : N19 : gnd : : : :
+VCC_HPS : N20 : power : : 1.1V : :
+VCCIO6A_HPS : N21 : power : : 2.5V : 6A :
+VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A :
+GND : N26 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B :
+GND : P1 : gnd : : : :
+GND : P2 : gnd : : : :
+DNU : P3 : : : : :
+DNU : P4 : : : : :
+GND : P5 : gnd : : : :
+VCCA_FPLL : P6 : power : : 2.5V : :
+GND : P7 : gnd : : : :
+GND : P8 : gnd : : : :
+GND : P9 : gnd : : : :
+GND : P10 : gnd : : : :
+VCC : P11 : power : : 1.1V : :
+GND : P12 : gnd : : : :
+VCC : P13 : power : : 1.1V : :
+GND : P14 : gnd : : : :
+VCC_HPS : P15 : power : : 1.1V : :
+GND : P16 : gnd : : : :
+VCC_HPS : P17 : power : : 1.1V : :
+GND : P18 : gnd : : : :
+VCC_HPS : P19 : power : : 1.1V : :
+GND : P20 : gnd : : : :
+VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B :
+VCCIO6B_HPS : P23 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B :
+VCCIO6B_HPS : P28 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B :
+GND : R1 : gnd : : : :
+GND : R2 : gnd : : : :
+GND : R3 : gnd : : : :
+GND : R4 : gnd : : : :
+VCC : R5 : power : : 1.1V : :
+GND : R6 : gnd : : : :
+VCCA_FPLL : R7 : power : : 2.5V : :
+GND : R8 : gnd : : : :
+GND : R9 : gnd : : : :
+VCC : R10 : power : : 1.1V : :
+GND : R11 : gnd : : : :
+VCC : R12 : power : : 1.1V : :
+GND : R13 : gnd : : : :
+VCC : R14 : power : : 1.1V : :
+GND : R15 : gnd : : : :
+VCC_HPS : R16 : power : : 1.1V : :
+GND : R17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B :
+VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B :
+VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
+VCCIO6B_HPS : R25 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B :
+GND : R30 : gnd : : : :
+GND : T1 : gnd : : : :
+GND : T2 : gnd : : : :
+DNU : T3 : : : : :
+DNU : T4 : : : : :
+GND : T5 : gnd : : : :
+VCC : T6 : power : : 1.1V : :
+GND : T7 : gnd : : : :
+GND : T8 : gnd : : : :
+GND : T9 : gnd : : : :
+GND : T10 : gnd : : : :
+VCC : T11 : power : : 1.1V : :
+GND : T12 : gnd : : : :
+VCC : T13 : power : : 1.1V : :
+GND : T14 : gnd : : : :
+GND : T15 : gnd : : : :
+GND : T16 : gnd : : : :
+VCC_HPS : T17 : power : : 1.1V : :
+GND : T18 : gnd : : : :
+VCC_HPS : T19 : power : : 1.1V : :
+GND : T20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B :
+VCCIO6B_HPS : T22 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
+GND : T27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B :
+GND : U1 : gnd : : : :
+GND : U2 : gnd : : : :
+GND : U3 : gnd : : : :
+GND : U4 : gnd : : : :
+VCC : U5 : power : : 1.1V : :
+GND : U6 : gnd : : : :
+DCLK : U7 : : : : 3A :
+TDI : U8 : input : : : 3A :
+GND : U9 : gnd : : : :
+VCC : U10 : power : : 1.1V : :
+GND : U11 : gnd : : : :
+VCC : U12 : power : : 1.1V : :
+GND : U13 : gnd : : : :
+VCC : U14 : power : : 1.1V : :
+GND : U15 : gnd : : : :
+VCC_HPS : U16 : power : : 1.1V : :
+GND : U17 : gnd : : : :
+VCC_HPS : U18 : power : : 1.1V : :
+VCCIO6B_HPS : U19 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B :
+VCC : U21 : power : : 1.1V : :
+GND : U22 : gnd : : : :
+VCCPD5B : U23 : power : : 3.3V : 5B :
+GND : U24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
+GND : U29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B :
+GND : V1 : gnd : : : :
+GND : V2 : gnd : : : :
+DNU : V3 : : : : :
+DNU : V4 : : : : :
+GND : V5 : gnd : : : :
+VCCA_FPLL : V6 : power : : 2.5V : :
+GND : V7 : gnd : : : :
+VCCA_FPLL : V8 : power : : 2.5V : :
+TMS : V9 : input : : : 3A :
+GND : V10 : gnd : : : :
+VCC : V11 : power : : 1.1V : :
+GND : V12 : gnd : : : :
+VCC : V13 : power : : 1.1V : :
+GND : V14 : gnd : : : :
+VCC : V15 : power : : 1.1V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
+GND : V19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
+GND : V21 : gnd : : : :
+VCCPD5A : V22 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5A :
+VCCPD5A : V24 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
+VCCIO6B_HPS : V26 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B :
+GND : W1 : gnd : : : :
+GND : W2 : gnd : : : :
+GND : W3 : gnd : : : :
+GND : W4 : gnd : : : :
+VCC : W5 : power : : 1.1V : :
+GND : W6 : gnd : : : :
+GND : W7 : gnd : : : :
+GND : W8 : gnd : : : :
+GND : W9 : gnd : : : :
+VCC : W10 : power : : 1.1V : :
+GND : W11 : gnd : : : :
+VCC : W12 : power : : 1.1V : :
+GND : W13 : gnd : : : :
+VCC : W14 : power : : 1.1V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
+GND : W18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5A :
+VCCIO5A : W23 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W24 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B :
+GND : W28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B :
+GND : Y1 : gnd : : : :
+GND : Y2 : gnd : : : :
+DNU : Y3 : : : : :
+DNU : Y4 : : : : :
+GND : Y5 : gnd : : : :
+VCC : Y6 : power : : 1.1V : :
+GND : Y7 : gnd : : : :
+GND : Y8 : gnd : : : :
+VCC : Y9 : power : : 1.1V : :
+GND : Y10 : gnd : : : :
+VCC : Y11 : power : : 1.1V : :
+GND : Y12 : gnd : : : :
+VCC : Y13 : power : : 1.1V : :
+GND : Y14 : gnd : : : :
+GND : Y15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
+GND : Y20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5A :
+VCCA_FPLL : Y22 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A :
+GND : Y25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B :
+GND : Y30 : gnd : : : :
diff --git a/part_1/ex4/output_files/ex4.sld b/part_1/ex4/output_files/ex4.sld new file mode 100644 index 0000000..41a6030 --- /dev/null +++ b/part_1/ex4/output_files/ex4.sld @@ -0,0 +1 @@ +<sld_project_info/>
diff --git a/part_1/ex4/output_files/ex4.sof b/part_1/ex4/output_files/ex4.sof Binary files differnew file mode 100644 index 0000000..f12dfe1 --- /dev/null +++ b/part_1/ex4/output_files/ex4.sof diff --git a/part_1/ex4/output_files/ex4.sta.rpt b/part_1/ex4/output_files/ex4.sta.rpt new file mode 100644 index 0000000..33c4fe5 --- /dev/null +++ b/part_1/ex4/output_files/ex4.sta.rpt @@ -0,0 +1,693 @@ +TimeQuest Timing Analyzer report for ex4
+Tue Nov 15 11:49:52 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. TimeQuest Timing Analyzer Summary
+ 3. Parallel Compilation
+ 4. Clocks
+ 5. Slow 1100mV 85C Model Fmax Summary
+ 6. Timing Closure Recommendations
+ 7. Slow 1100mV 85C Model Setup Summary
+ 8. Slow 1100mV 85C Model Hold Summary
+ 9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Clock Transfers
+ 40. Report TCCS
+ 41. Report RSKM
+ 42. Unconstrained Paths Summary
+ 43. Unconstrained Input Ports
+ 44. Unconstrained Output Ports
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer ; TimeQuest ;
+; Revision Name ; ex4 ;
+; Device Family ; Cyclone V ;
+; Device Name ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Delay Model ; Combined ;
+; Rise/Fall Delays ; Enabled ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.04 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 1.2% ;
+; Processor 3 ; 1.2% ;
+; Processor 4 ; 1.2% ;
++----------------------------+-------------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+---------------------------------------
+; Fast 1100mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Fast 1100mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1100mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1100mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
+; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------+
+; Input Transition Times ;
++-------+--------------+-----------------+-----------------+
+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------+--------------+-----------------+-----------------+
+; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
++-------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary ;
++---------------------------------+-------+------+
+; Property ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks ; 0 ; 0 ;
+; Unconstrained Clocks ; 0 ; 0 ;
+; Unconstrained Input Ports ; 10 ; 10 ;
+; Unconstrained Input Port Paths ; 217 ; 217 ;
+; Unconstrained Output Ports ; 25 ; 25 ;
+; Unconstrained Output Port Paths ; 217 ; 217 ;
++---------------------------------+-------+------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 11:49:43 2016
+Info: Command: quartus_sta ex4 -c ex4
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex4.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1100mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1100mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
+ Info: Peak virtual memory: 1202 megabytes
+ Info: Processing ended: Tue Nov 15 11:49:52 2016
+ Info: Elapsed time: 00:00:09
+ Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_1/ex4/output_files/ex4.sta.summary b/part_1/ex4/output_files/ex4.sta.summary new file mode 100644 index 0000000..6640100 --- /dev/null +++ b/part_1/ex4/output_files/ex4.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/part_1/ex4/verilog_files/add3_ge5.v b/part_1/ex4/verilog_files/add3_ge5.v new file mode 100644 index 0000000..65a561d --- /dev/null +++ b/part_1/ex4/verilog_files/add3_ge5.v @@ -0,0 +1,25 @@ +module add3_ge5(w,a);
+ output [3:0] a;
+ input [3:0] w;
+
+ reg [3:0] a;
+
+ always @ (w)
+ case(w)
+ 4'b0000: a <= 4'b0000;
+ 4'b0001: a <= 4'b0001;
+ 4'b0010: a <= 4'b0010;
+ 4'b0011: a <= 4'b0011;
+ 4'b0100: a <= 4'b0100;
+ 4'b0101: a <= 4'b1000;
+ 4'b0110: a <= 4'b1001;
+ 4'b0111: a <= 4'b1010;
+ 4'b1000: a <= 4'b1011;
+ 4'b1001: a <= 4'b1100;
+ 4'b1010: a <= 4'b1101;
+ 4'b1011: a <= 4'b1110;
+ 4'b1100: a <= 4'b1111;
+
+ default: a <= 4'b0000;
+ endcase
+endmodule
diff --git a/part_1/ex4/verilog_files/add3_ge5.v.bak b/part_1/ex4/verilog_files/add3_ge5.v.bak new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/part_1/ex4/verilog_files/add3_ge5.v.bak diff --git a/part_1/ex4/verilog_files/bin2bcd_10.v b/part_1/ex4/verilog_files/bin2bcd_10.v new file mode 100644 index 0000000..c6f7b6d --- /dev/null +++ b/part_1/ex4/verilog_files/bin2bcd_10.v @@ -0,0 +1,46 @@ +module bin2bcd_10 (B, BCD_0, BCD_1, BCD_2, BCD_3);
+
+ input [9:0] B; // binary input number
+ output [3:0] BCD_0, BCD_1, BCD_2, BCD_3; // BCD digit LSD to MSD
+
+ wire [3:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
+ wire [3:0] a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12;
+
+ // Instantiate a tree of add3-if-greater than or equal to 5 cells
+ // ... input is w_n, and output is a_n
+ add3_ge5 A1 (w1,a1);
+ add3_ge5 A2 (w2,a2);
+ add3_ge5 A3 (w3,a3);
+ add3_ge5 A4 (w4,a4);
+ add3_ge5 A5 (w5,a5);
+ add3_ge5 A6 (w6,a6);
+ add3_ge5 A7 (w7,a7);
+ add3_ge5 A8 (w8,a8);
+ add3_ge5 A9 (w9,a9);
+ add3_ge5 A10 (w10,a10);
+ add3_ge5 A11 (w11,a11);
+ add3_ge5 A12 (w12,a12);
+
+ // wire the tree of add3 modules together
+ assign w1 = {1'b0, B[9:7]}; // wn is the input port to module An
+ assign w2 = {a1[2:0], B[6]};
+ assign w3 = {a2[2:0], B[5]};
+ assign w4 = {1'b0, a1[3], a2[3], a3[3]};
+ assign w5 = {a3[2:0], B[4]};
+ assign w6 = {a4[2:0], a5[3]};
+ assign w7 = {a5[2:0], B[3]};
+ assign w8 = {a6[2:0], a7[3]};
+ assign w9 = {a7[2:0], B[2]};
+ assign w10 = {1'b0, a4[3], a6[3], a8[3]};
+ assign w11 = {a8[2:0], a9[3]};
+ assign w12 = {a9[2:0], B[1]};
+
+ // connect up to four BCD digit outputs
+ assign BCD_0 = {a12[2:0],B[0]};
+ assign BCD_1 = {a11[2:0],a12[3]};
+ assign BCD_2 = {a10[2:0],a11[3]};
+ assign BCD_3 = {3'b000,a10[3]};
+endmodule
+
+
+
diff --git a/part_1/ex4/verilog_files/bin2bcd_10.v.bak b/part_1/ex4/verilog_files/bin2bcd_10.v.bak new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/part_1/ex4/verilog_files/bin2bcd_10.v.bak diff --git a/part_1/ex4/verilog_files/bin2bcd_16.v b/part_1/ex4/verilog_files/bin2bcd_16.v new file mode 100644 index 0000000..fdfb655 --- /dev/null +++ b/part_1/ex4/verilog_files/bin2bcd_16.v @@ -0,0 +1,97 @@ +//------------------------------
+// Module name: bin2bcd_16
+// Function: Converts a 16-bit binary number to 5 digits BCD
+// .... it uses a shift-and-add3 algorithm
+// Creator: Peter Cheung
+// Version: 1.0
+// Date: 18 Sept 2016
+//------------------------------
+// For more explanation of how this work, see
+// ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
+
+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+ input [15:0] B; // binary input number
+ output [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4; // BCD digit LSD to MSD
+
+ wire [3:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
+ wire [3:0] w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;
+ wire [3:0] w26,w27,w28,w29;
+ wire [3:0] a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;
+ wire [3:0] a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;
+ wire [3:0] a26,a27,a28,a29;
+
+ // Instantiate a tree of add3-if-greater than or equal to 5 cells
+ // ... input is w_n, and output is a_n
+ add3_ge5 A1 (w1,a1);
+ add3_ge5 A2 (w2,a2);
+ add3_ge5 A3 (w3,a3);
+ add3_ge5 A4 (w4,a4);
+ add3_ge5 A5 (w5,a5);
+ add3_ge5 A6 (w6,a6);
+ add3_ge5 A7 (w7,a7);
+ add3_ge5 A8 (w8,a8);
+ add3_ge5 A9 (w9,a9);
+ add3_ge5 A10 (w10,a10);
+ add3_ge5 A11 (w11,a11);
+ add3_ge5 A12 (w12,a12);
+ add3_ge5 A13 (w13,a13);
+ add3_ge5 A14 (w14,a14);
+ add3_ge5 A15 (w15,a15);
+ add3_ge5 A16 (w16,a16);
+ add3_ge5 A17 (w17,a17);
+ add3_ge5 A18 (w18,a18);
+ add3_ge5 A19 (w19,a19);
+ add3_ge5 A20 (w20,a20);
+ add3_ge5 A21 (w21,a21);
+ add3_ge5 A22 (w22,a22);
+ add3_ge5 A23 (w23,a23);
+ add3_ge5 A24 (w24,a24);
+ add3_ge5 A25 (w25,a25);
+ add3_ge5 A26 (w26,a26);
+ add3_ge5 A27 (w27,a27);
+ add3_ge5 A28 (w28,a28);
+ add3_ge5 A29 (w29,a29);
+
+ // wire the tree of add3 modules together
+ assign w1 = {B[14:11]}; // wn is the input port to module An
+ assign w2 = {a1[2:0], B[10]};
+ assign w3 = {1'b0, B[15], a1[3], a2[3]};
+ assign w4 = {a2[2:0], B[9]};
+ assign w5 = {a3[2:0], a4[3]};
+ assign w6 = {a4[2:0], B[8]};
+ assign w7 = {a5[2:0], a6[3]};
+ assign w8 = {a6[2:0], B[7]};
+ assign w9 = {1'b0, a3[3], a5[3], a7[3]};
+ assign w10 = {a7[2:0], a8[3]};
+ assign w11 = {a8[2:0], B[6]};
+ assign w12 = {a9[2:0], a10[3]};
+ assign w13 = {a10[2:0], a11[3]};
+ assign w14 = {a11[2:0], B[5]};
+ assign w15 = {a12[2:0], a13[3]};
+ assign w16 = {a13[2:0], a14[3]};
+ assign w17 = {a14[2:0], B[4]};
+ assign w18 = {1'b0, a9[3], a12[3], a15[3]};
+ assign w19 = {a15[2:0], a16[3]};
+ assign w20 = {a16[2:0], a17[3]};
+ assign w21 = {a17[2:0], B[3]};
+ assign w22 = {a18[2:0], a19[3]};
+ assign w23 = {a19[2:0], a20[3]};
+ assign w24 = {a20[2:0], a21[3]};
+ assign w25 = {a21[2:0], B[2]};
+ assign w26 = {a22[2:0], a23[3]};
+ assign w27 = {a23[2:0], a24[3]};
+ assign w28 = {a24[2:0], a25[3]};
+ assign w29 = {a25[2:0], B[1]};
+
+ // connect up to four BCD digit outputs
+ assign BCD_0 = {a29[2:0],B[0]};
+ assign BCD_1 = {a28[2:0],a29[3]};
+ assign BCD_2 = {a27[2:0],a28[3]};
+ assign BCD_3 = {a26[2:0],a27[3]};
+ assign BCD_4 = {1'b0, a18[3], a22[3], a26[3]};
+endmodule
+
+
+
+
diff --git a/part_1/ex4/verilog_files/hex_to_7seg.v b/part_1/ex4/verilog_files/hex_to_7seg.v new file mode 100644 index 0000000..82aa9a5 --- /dev/null +++ b/part_1/ex4/verilog_files/hex_to_7seg.v @@ -0,0 +1,27 @@ +module hex_to_7seg (out, in);
+
+ output [6:0] out;
+ input [3:0] in;
+
+ reg [6:0] out;
+
+ always @ (*)
+ case(in)
+ 4'h0: out = 7'b1000000;
+ 4'h1: out = 7'b1111001;
+ 4'h2: out = 7'b0100100;
+ 4'h3: out = 7'b0110000;
+ 4'h4: out = 7'b0011001;
+ 4'h5: out = 7'b0010010;
+ 4'h6: out = 7'b0000010;
+ 4'h7: out = 7'b1111000;
+ 4'h8: out = 7'b0000000;
+ 4'h9: out = 7'b0011000;
+ 4'ha: out = 7'b0001000;
+ 4'hb: out = 7'b0000011;
+ 4'hc: out = 7'b1000110;
+ 4'hd: out = 7'b0100001;
+ 4'he: out = 7'b0000110;
+ 4'hf: out = 7'b0001110;
+ endcase
+endmodule
diff --git a/pin_assignment.txt b/pin_assignment.txt new file mode 100644 index 0000000..04a3a75 --- /dev/null +++ b/pin_assignment.txt @@ -0,0 +1,211 @@ +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_AF14 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# Add-on Card Interface Pins +#============================================================ +set_location_assignment PIN_AJ20 -to PWM_OUT +set_location_assignment PIN_AK21 -to DAC_LD +set_location_assignment PIN_AD20 -to DAC_CS +set_location_assignment PIN_AF20 -to DAC_SCK +set_location_assignment PIN_AF21 -to ADC_SCK +set_location_assignment PIN_AG21 -to ADC_SDI +set_location_assignment PIN_AG20 -to ADC_CS +set_location_assignment PIN_AG18 -to DAC_SDI +set_location_assignment PIN_AJ21 -to ADC_SDO +set_location_assignment PIN_Y17 -to OLED_CS +set_location_assignment PIN_Y18 -to OLED_RST +set_location_assignment PIN_AK18 -to OLED_DC +set_location_assignment PIN_AJ19 -to OLED_CLK +set_location_assignment PIN_AJ16 -to OLED_DATA + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO + + +#============================================================ +# HEX0 +#============================================================ +set_location_assignment PIN_AE26 -to HEX0[0] +set_location_assignment PIN_AE27 -to HEX0[1] +set_location_assignment PIN_AE28 -to HEX0[2] +set_location_assignment PIN_AG27 -to HEX0[3] +set_location_assignment PIN_AF28 -to HEX0[4] +set_location_assignment PIN_AG28 -to HEX0[5] +set_location_assignment PIN_AH28 -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] + +#============================================================ +# HEX1 +#============================================================ +set_location_assignment PIN_AJ29 -to HEX1[0] +set_location_assignment PIN_AH29 -to HEX1[1] +set_location_assignment PIN_AH30 -to HEX1[2] +set_location_assignment PIN_AG30 -to HEX1[3] +set_location_assignment PIN_AF29 -to HEX1[4] +set_location_assignment PIN_AF30 -to HEX1[5] +set_location_assignment PIN_AD27 -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] + +#============================================================ +# HEX2 +#============================================================ +set_location_assignment PIN_AB23 -to HEX2[0] +set_location_assignment PIN_AE29 -to HEX2[1] +set_location_assignment PIN_AD29 -to HEX2[2] +set_location_assignment PIN_AC28 -to HEX2[3] +set_location_assignment PIN_AD30 -to HEX2[4] +set_location_assignment PIN_AC29 -to HEX2[5] +set_location_assignment PIN_AC30 -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] + +#============================================================ +# HEX3 +#============================================================ +set_location_assignment PIN_AD26 -to HEX3[0] +set_location_assignment PIN_AC27 -to HEX3[1] +set_location_assignment PIN_AD25 -to HEX3[2] +set_location_assignment PIN_AC25 -to HEX3[3] +set_location_assignment PIN_AB28 -to HEX3[4] +set_location_assignment PIN_AB25 -to HEX3[5] +set_location_assignment PIN_AB22 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] + +#============================================================ +# HEX4 +#============================================================ +set_location_assignment PIN_AA24 -to HEX4[0] +set_location_assignment PIN_Y23 -to HEX4[1] +set_location_assignment PIN_Y24 -to HEX4[2] +set_location_assignment PIN_W22 -to HEX4[3] +set_location_assignment PIN_W24 -to HEX4[4] +set_location_assignment PIN_V23 -to HEX4[5] +set_location_assignment PIN_W25 -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] + +#============================================================ +# HEX5 +#============================================================ +set_location_assignment PIN_V25 -to HEX5[0] +set_location_assignment PIN_AA28 -to HEX5[1] +set_location_assignment PIN_Y27 -to HEX5[2] +set_location_assignment PIN_AB27 -to HEX5[3] +set_location_assignment PIN_AB26 -to HEX5[4] +set_location_assignment PIN_AA26 -to HEX5[5] +set_location_assignment PIN_AA25 -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_AA14 -to KEY[0] +set_location_assignment PIN_AA15 -to KEY[1] +set_location_assignment PIN_W15 -to KEY[2] +set_location_assignment PIN_Y16 -to KEY[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] + +#============================================================ +# LEDR +#============================================================ +set_location_assignment PIN_V16 -to LEDR[0] +set_location_assignment PIN_W16 -to LEDR[1] +set_location_assignment PIN_V17 -to LEDR[2] +set_location_assignment PIN_V18 -to LEDR[3] +set_location_assignment PIN_W17 -to LEDR[4] +set_location_assignment PIN_W19 -to LEDR[5] +set_location_assignment PIN_Y19 -to LEDR[6] +set_location_assignment PIN_W20 -to LEDR[7] +set_location_assignment PIN_W21 -to LEDR[8] +set_location_assignment PIN_Y21 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_AB12 -to SW[0] +set_location_assignment PIN_AC12 -to SW[1] +set_location_assignment PIN_AF9 -to SW[2] +set_location_assignment PIN_AF10 -to SW[3] +set_location_assignment PIN_AD11 -to SW[4] +set_location_assignment PIN_AD12 -to SW[5] +set_location_assignment PIN_AE11 -to SW[6] +set_location_assignment PIN_AC9 -to SW[7] +set_location_assignment PIN_AD10 -to SW[8] +set_location_assignment PIN_AE12 -to SW[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] + +#============================================================ +# End of pin and io_standard assignments +#============================================================
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