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authorymherklotz <ymherklotz@gmail.com>2016-12-11 21:35:22 +0000
committerymherklotz <ymherklotz@gmail.com>2016-12-11 21:35:22 +0000
commitc2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (patch)
tree567b3cd21f01fe683f9cdaeb65ea0a20e925ac75
parent47665d0ff2ee13848f4b5b2e3a36d7f4e8b08731 (diff)
downloadVerilogCoursework-c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f.tar.gz
VerilogCoursework-c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f.zip
fixed ex8 and ex9
Diffstat
-rwxr-xr-xpart_2/ex6/c5_pin_model_dump.txt236
-rwxr-xr-xpart_2/ex6/db/.cmp.kptbin376 -> 200 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(0).cnf.cdbbin2561 -> 2565 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(0).cnf.hdbbin1327 -> 1335 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(1).cnf.cdbbin2137 -> 2133 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(1).cnf.hdbbin848 -> 858 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(2).cnf.cdbbin2678 -> 2672 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(2).cnf.hdbbin937 -> 937 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(3).cnf.cdbbin4635 -> 4625 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(3).cnf.hdbbin2225 -> 2300 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(4).cnf.cdbbin1335 -> 1333 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(4).cnf.hdbbin731 -> 731 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(5).cnf.cdbbin1452 -> 1450 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.(5).cnf.hdbbin775 -> 772 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.ae.hdbbin15168 -> 0 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.analyze_file.qmsg6
-rwxr-xr-xpart_2/ex6/db/ex6.asm.qmsg12
-rwxr-xr-xpart_2/ex6/db/ex6.asm.rdbbin790 -> 760 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.cbx.xml10
-rwxr-xr-xpart_2/ex6/db/ex6.cmp.ammdbbin2674 -> 0 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.cmp.bpmbin921 -> 941 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.cmp.cdbbin145288 -> 141957 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.cmp.hdbbin123046 -> 122973 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.cmp.idbbin2552 -> 2547 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.cmp.logdb154
-rwxr-xr-xpart_2/ex6/db/ex6.cmp.rdbbin33913 -> 33956 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.cmp_merge.kptbin206 -> 205 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsdbin1519411 -> 1518175 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsdbin1520839 -> 1520837 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsdbin1518280 -> 1518278 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsdbin1507272 -> 1510682 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.db_info6
-rwxr-xr-xpart_2/ex6/db/ex6.fit.qmsg91
-rwxr-xr-xpart_2/ex6/db/ex6.hier_info1114
-rwxr-xr-xpart_2/ex6/db/ex6.hifbin851 -> 842 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.lpc.html1220
-rwxr-xr-xpart_2/ex6/db/ex6.lpc.rdbbin831 -> 829 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.lpc.txt86
-rwxr-xr-xpart_2/ex6/db/ex6.map.ammdbbin133 -> 129 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.map.bpmbin853 -> 881 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.map.cdbbin9833 -> 10096 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.map.hdbbin17305 -> 18101 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.map.kptbin1121 -> 1106 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.map.logdb2
-rwxr-xr-xpart_2/ex6/db/ex6.map.qmsg101
-rwxr-xr-xpart_2/ex6/db/ex6.map.rdbbin1390 -> 1369 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.map_bb.cdbbin2028 -> 2196 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.map_bb.hdbbin13316 -> 14070 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.map_bb.logdb2
-rwxr-xr-xpart_2/ex6/db/ex6.pre_map.cdbbin10939 -> 0 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.pre_map.hdbbin19143 -> 19667 bytes
-rw-r--r--part_2/ex6/db/ex6.quiproj.2528.rdr.flock0
-rwxr-xr-xpart_2/ex6/db/ex6.root_partition.map.reg_db.cdbbin221 -> 217 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.routing.rdbbin29831 -> 31241 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.rtlv.hdbbin18708 -> 19383 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.rtlv_sg.cdbbin10024 -> 10008 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.rtlv_sg_swap.cdbbin2050 -> 2050 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.sld_design_entry.scibin227 -> 225 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.sld_design_entry_dsc.scibin227 -> 225 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.smart_action.txt2
-rwxr-xr-xpart_2/ex6/db/ex6.sta.qmsg100
-rwxr-xr-xpart_2/ex6/db/ex6.sta.rdbbin10963 -> 10995 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdbbin48128 -> 45398 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.tis_db_list.ddbbin301 -> 297 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddbbin340455 -> 338570 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddbbin332289 -> 330220 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddbbin335550 -> 333324 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddbbin343026 -> 341171 bytes
-rwxr-xr-xpart_2/ex6/db/ex6.tmw_info12
-rwxr-xr-xpart_2/ex6/db/ex6.vpr.ammdbbin486 -> 482 bytes
-rwxr-xr-xpart_2/ex6/db/ex6_partition_pins.json320
-rwxr-xr-xpart_2/ex6/db/prev_cmp_ex6.qmsg320
-rwxr-xr-xpart_2/ex6/ex6.qsf2
-rwxr-xr-xpart_2/ex6/ex6.qwsbin48 -> 0 bytes
-rw-r--r--part_2/ex6/ex6_assignment_defaults.qdf795
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.db_info6
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdbbin2662 -> 539 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdbbin112363 -> 109627 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdbbin1945 -> 2117 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdbbin17320 -> 17419 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdbbin17483 -> 17557 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb2
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdbbin25157 -> 24594 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdbbin9425 -> 9730 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpibin1496 -> 1523 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdbbin1447 -> 1597 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdbbin16593 -> 16971 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdbbin17147 -> 16907 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kptbin1155 -> 1116 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olf.cdbbin491 -> 0 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olm.cdbbin2023 -> 0 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.oln.cdbbin9007 -> 0 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.opi1
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orf.cdbbin491 -> 0 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orm.cdbbin2871 -> 0 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orn.cdbbin10667 -> 0 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.cdbbin9425 -> 0 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.cdbbin1447 -> 0 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.hdbbin16593 -> 0 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hdbbin17147 -> 0 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdbbin18068 -> 18730 bytes
-rwxr-xr-xpart_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdbbin327 -> 273 bytes
-rwxr-xr-xpart_2/ex6/output_files/ex6.asm.rpt184
-rwxr-xr-xpart_2/ex6/output_files/ex6.done2
-rwxr-xr-xpart_2/ex6/output_files/ex6.fit.rpt4068
-rwxr-xr-xpart_2/ex6/output_files/ex6.fit.smsg12
-rwxr-xr-xpart_2/ex6/output_files/ex6.fit.summary40
-rwxr-xr-xpart_2/ex6/output_files/ex6.flow.rpt256
-rwxr-xr-xpart_2/ex6/output_files/ex6.jdi16
-rwxr-xr-xpart_2/ex6/output_files/ex6.map.rpt868
-rwxr-xr-xpart_2/ex6/output_files/ex6.map.summary34
-rwxr-xr-xpart_2/ex6/output_files/ex6.pin1953
-rwxr-xr-xpart_2/ex6/output_files/ex6.sld2
-rwxr-xr-xpart_2/ex6/output_files/ex6.sofbin6690331 -> 6690318 bytes
-rwxr-xr-xpart_2/ex6/output_files/ex6.sta.rpt1678
-rwxr-xr-xpart_2/ex6/output_files/ex6.sta.summary106
-rwxr-xr-xpart_2/ex8/c5_pin_model_dump.txt236
-rwxr-xr-xpart_2/ex8/db/.cmp.kptbin849 -> 686 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(0).cnf.cdbbin2900 -> 2892 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(0).cnf.hdbbin1493 -> 1489 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(1).cnf.cdbbin2091 -> 2088 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(1).cnf.hdbbin847 -> 861 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(2).cnf.cdbbin2135 -> 2128 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(2).cnf.hdbbin837 -> 846 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(3).cnf.cdbbin5504 -> 5213 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(3).cnf.hdbbin2071 -> 2009 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(4).cnf.cdbbin1444 -> 1437 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(4).cnf.hdbbin796 -> 808 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(5).cnf.cdbbin5527 -> 5523 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(5).cnf.hdbbin1481 -> 1495 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(6).cnf.cdbbin5140 -> 5128 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(6).cnf.hdbbin2463 -> 2491 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(7).cnf.cdbbin1335 -> 1332 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(7).cnf.hdbbin736 -> 740 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(8).cnf.cdbbin1452 -> 1449 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.(8).cnf.hdbbin775 -> 776 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.ae.hdbbin17761 -> 0 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.analyze_file.qmsg6
-rwxr-xr-xpart_2/ex8/db/ex8.asm.qmsg12
-rwxr-xr-xpart_2/ex8/db/ex8.asm.rdbbin813 -> 760 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.cbx.xml10
-rwxr-xr-xpart_2/ex8/db/ex8.cmp.ammdbbin6307 -> 0 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.cmp.bpmbin937 -> 933 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.cmp.cdbbin182515 -> 180750 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.cmp.hdbbin125010 -> 124859 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.cmp.idbbin2543 -> 2515 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.cmp.logdb150
-rwxr-xr-xpart_2/ex8/db/ex8.cmp.rdbbin35329 -> 35365 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.cmp_merge.kptbin207 -> 205 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsdbin1519411 -> 1519409 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsdbin1520839 -> 1520837 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsdbin1518280 -> 1518278 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsdbin1507272 -> 1507270 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.db_info6
-rwxr-xr-xpart_2/ex8/db/ex8.fit.qmsg91
-rwxr-xr-xpart_2/ex8/db/ex8.hier_info1361
-rwxr-xr-xpart_2/ex8/db/ex8.hifbin1118 -> 1113 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.lpc.html1444
-rwxr-xr-xpart_2/ex8/db/ex8.lpc.rdbbin958 -> 956 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.lpc.txt100
-rwxr-xr-xpart_2/ex8/db/ex8.map.ammdbbin133 -> 129 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.map.bpmbin908 -> 908 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.map.cdbbin11922 -> 11891 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.map.hdbbin19524 -> 20091 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.map.kptbin2424 -> 2341 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.map.logdb2
-rwxr-xr-xpart_2/ex8/db/ex8.map.qmsg148
-rwxr-xr-xpart_2/ex8/db/ex8.map.rdbbin1392 -> 1371 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.map_bb.cdbbin2030 -> 2193 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.map_bb.hdbbin13904 -> 14674 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.map_bb.logdb2
-rwxr-xr-xpart_2/ex8/db/ex8.pre_map.cdbbin28936 -> 0 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.pre_map.hdbbin22152 -> 22496 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.root_partition.map.reg_db.cdbbin374 -> 370 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.routing.rdbbin28564 -> 30290 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.rtlv.hdbbin21572 -> 21963 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.rtlv_sg.cdbbin20673 -> 20386 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.rtlv_sg_swap.cdbbin2427 -> 2425 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.sld_design_entry.scibin227 -> 225 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.sld_design_entry_dsc.scibin227 -> 225 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.smart_action.txt2
-rwxr-xr-xpart_2/ex8/db/ex8.smp_dump.txt26
-rwxr-xr-xpart_2/ex8/db/ex8.sta.qmsg106
-rwxr-xr-xpart_2/ex8/db/ex8.sta.rdbbin11613 -> 11590 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdbbin51532 -> 48643 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.tis_db_list.ddbbin301 -> 297 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddbbin350291 -> 347116 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddbbin344147 -> 340986 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddbbin347301 -> 344367 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddbbin353437 -> 349641 bytes
-rwxr-xr-xpart_2/ex8/db/ex8.tmw_info12
-rwxr-xr-xpart_2/ex8/db/ex8.vpr.ammdbbin697 -> 720 bytes
-rwxr-xr-xpart_2/ex8/db/ex8_partition_pins.json256
-rwxr-xr-xpart_2/ex8/db/prev_cmp_ex8.qmsg248
-rwxr-xr-xpart_2/ex8/ex8.qsf2
-rwxr-xr-xpart_2/ex8/ex8.qwsbin3585 -> 3159 bytes
-rw-r--r--part_2/ex8/ex8_assignment_defaults.qdf795
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.db_info6
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdbbin6287 -> 708 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdbbin148900 -> 148378 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdbbin1941 -> 2112 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdbbin19480 -> 19521 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdbbin19569 -> 19601 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb2
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdbbin25573 -> 24386 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdbbin11270 -> 11407 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpibin1866 -> 1878 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdbbin1446 -> 1595 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdbbin18725 -> 18882 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdbbin19198 -> 18763 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kptbin2416 -> 2360 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olf.cdbbin628 -> 0 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olm.cdbbin2420 -> 0 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.oln.cdbbin11777 -> 0 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.opi1
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orf.cdbbin688 -> 0 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orm.cdbbin4166 -> 0 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orn.cdbbin32203 -> 0 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.cdbbin11270 -> 0 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.cdbbin1446 -> 0 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.hdbbin18725 -> 0 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hdbbin19198 -> 0 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdbbin20251 -> 20890 bytes
-rwxr-xr-xpart_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdbbin402 -> 276 bytes
-rwxr-xr-xpart_2/ex8/output_files/ex8.asm.rpt184
-rwxr-xr-xpart_2/ex8/output_files/ex8.done2
-rwxr-xr-xpart_2/ex8/output_files/ex8.fit.rpt4113
-rwxr-xr-xpart_2/ex8/output_files/ex8.fit.smsg12
-rwxr-xr-xpart_2/ex8/output_files/ex8.fit.summary40
-rwxr-xr-xpart_2/ex8/output_files/ex8.flow.rpt256
-rwxr-xr-xpart_2/ex8/output_files/ex8.jdi16
-rwxr-xr-xpart_2/ex8/output_files/ex8.map.rpt1145
-rwxr-xr-xpart_2/ex8/output_files/ex8.map.smsg74
-rwxr-xr-xpart_2/ex8/output_files/ex8.map.summary34
-rwxr-xr-xpart_2/ex8/output_files/ex8.pin1953
-rwxr-xr-xpart_2/ex8/output_files/ex8.sld2
-rwxr-xr-xpart_2/ex8/output_files/ex8.sofbin6690331 -> 6690318 bytes
-rwxr-xr-xpart_2/ex8/output_files/ex8.sta.rpt1728
-rwxr-xr-xpart_2/ex8/output_files/ex8.sta.summary298
-rwxr-xr-xpart_2/ex8/verilog_files/formula_fsm.v8
-rw-r--r--part_2/ex9/c5_pin_model_dump.txt236
-rw-r--r--part_2/ex9/db/.cmp.kptbin671 -> 725 bytes
-rw-r--r--part_2/ex9/db/ex9.(0).cnf.cdbbin3548 -> 3544 bytes
-rw-r--r--part_2/ex9/db/ex9.(0).cnf.hdbbin1744 -> 1749 bytes
-rw-r--r--part_2/ex9/db/ex9.(1).cnf.cdbbin2090 -> 2088 bytes
-rw-r--r--part_2/ex9/db/ex9.(1).cnf.hdbbin853 -> 865 bytes
-rw-r--r--part_2/ex9/db/ex9.(2).cnf.cdbbin2134 -> 5190 bytes
-rw-r--r--part_2/ex9/db/ex9.(2).cnf.hdbbin838 -> 2011 bytes
-rw-r--r--part_2/ex9/db/ex9.(3).cnf.cdbbin5480 -> 1438 bytes
-rw-r--r--part_2/ex9/db/ex9.(3).cnf.hdbbin2028 -> 804 bytes
-rw-r--r--part_2/ex9/db/ex9.(4).cnf.cdbbin1442 -> 5524 bytes
-rw-r--r--part_2/ex9/db/ex9.(4).cnf.hdbbin798 -> 1477 bytes
-rw-r--r--part_2/ex9/db/ex9.(5).cnf.cdbbin5529 -> 3259 bytes
-rw-r--r--part_2/ex9/db/ex9.(5).cnf.hdbbin1457 -> 970 bytes
-rw-r--r--part_2/ex9/db/ex9.(6).cnf.cdbbin3267 -> 5129 bytes
-rw-r--r--part_2/ex9/db/ex9.(6).cnf.hdbbin968 -> 2480 bytes
-rw-r--r--part_2/ex9/db/ex9.(7).cnf.cdbbin5138 -> 1333 bytes
-rw-r--r--part_2/ex9/db/ex9.(7).cnf.hdbbin2471 -> 734 bytes
-rw-r--r--part_2/ex9/db/ex9.(8).cnf.cdbbin1335 -> 1450 bytes
-rw-r--r--part_2/ex9/db/ex9.(8).cnf.hdbbin736 -> 771 bytes
-rw-r--r--part_2/ex9/db/ex9.(9).cnf.cdbbin1452 -> 0 bytes
-rw-r--r--part_2/ex9/db/ex9.(9).cnf.hdbbin780 -> 0 bytes
-rw-r--r--part_2/ex9/db/ex9.asm.qmsg12
-rw-r--r--part_2/ex9/db/ex9.asm.rdbbin817 -> 760 bytes
-rw-r--r--part_2/ex9/db/ex9.cbx.xml10
-rw-r--r--part_2/ex9/db/ex9.cmp.ammdbbin7789 -> 0 bytes
-rw-r--r--part_2/ex9/db/ex9.cmp.bpmbin1102 -> 1125 bytes
-rw-r--r--part_2/ex9/db/ex9.cmp.cdbbin237139 -> 239556 bytes
-rw-r--r--part_2/ex9/db/ex9.cmp.hdbbin126102 -> 126112 bytes
-rw-r--r--part_2/ex9/db/ex9.cmp.idbbin3657 -> 3586 bytes
-rw-r--r--part_2/ex9/db/ex9.cmp.logdb192
-rw-r--r--part_2/ex9/db/ex9.cmp.rdbbin37633 -> 37713 bytes
-rw-r--r--part_2/ex9/db/ex9.cmp_merge.kptbin207 -> 205 bytes
-rw-r--r--part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsdbin1518177 -> 1519409 bytes
-rw-r--r--part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsdbin1520839 -> 1520837 bytes
-rw-r--r--part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsdbin1518280 -> 1518278 bytes
-rw-r--r--part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsdbin1510684 -> 1507270 bytes
-rw-r--r--part_2/ex9/db/ex9.db_info6
-rw-r--r--part_2/ex9/db/ex9.fit.qmsg91
-rw-r--r--part_2/ex9/db/ex9.hier_info1565
-rw-r--r--part_2/ex9/db/ex9.hifbin1185 -> 1133 bytes
-rw-r--r--part_2/ex9/db/ex9.lpc.html1540
-rw-r--r--part_2/ex9/db/ex9.lpc.rdbbin987 -> 985 bytes
-rw-r--r--part_2/ex9/db/ex9.lpc.txt106
-rw-r--r--part_2/ex9/db/ex9.map.ammdbbin133 -> 129 bytes
-rw-r--r--part_2/ex9/db/ex9.map.bpmbin1076 -> 1090 bytes
-rw-r--r--part_2/ex9/db/ex9.map.cdbbin16622 -> 16381 bytes
-rw-r--r--part_2/ex9/db/ex9.map.hdbbin20943 -> 21731 bytes
-rw-r--r--part_2/ex9/db/ex9.map.kptbin2796 -> 2757 bytes
-rw-r--r--part_2/ex9/db/ex9.map.logdb2
-rw-r--r--part_2/ex9/db/ex9.map.qmsg146
-rw-r--r--part_2/ex9/db/ex9.map.rdbbin1394 -> 1372 bytes
-rw-r--r--part_2/ex9/db/ex9.map_bb.cdbbin2141 -> 2305 bytes
-rw-r--r--part_2/ex9/db/ex9.map_bb.hdbbin13574 -> 14594 bytes
-rw-r--r--part_2/ex9/db/ex9.map_bb.logdb2
-rw-r--r--part_2/ex9/db/ex9.pre_map.hdbbin22382 -> 23008 bytes
-rw-r--r--part_2/ex9/db/ex9.quiproj.2651.rdr.flock0
-rw-r--r--part_2/ex9/db/ex9.root_partition.map.reg_db.cdbbin373 -> 370 bytes
-rw-r--r--part_2/ex9/db/ex9.routing.rdbbin32080 -> 34615 bytes
-rw-r--r--part_2/ex9/db/ex9.rtlv.hdbbin21730 -> 22449 bytes
-rw-r--r--part_2/ex9/db/ex9.rtlv_sg.cdbbin22454 -> 22230 bytes
-rw-r--r--part_2/ex9/db/ex9.rtlv_sg_swap.cdbbin2658 -> 2672 bytes
-rw-r--r--part_2/ex9/db/ex9.sld_design_entry.scibin227 -> 225 bytes
-rw-r--r--part_2/ex9/db/ex9.sld_design_entry_dsc.scibin227 -> 225 bytes
-rw-r--r--part_2/ex9/db/ex9.smart_action.txt2
-rw-r--r--part_2/ex9/db/ex9.smp_dump.txt26
-rw-r--r--part_2/ex9/db/ex9.sta.qmsg106
-rw-r--r--part_2/ex9/db/ex9.sta.rdbbin12991 -> 13057 bytes
-rw-r--r--part_2/ex9/db/ex9.sta_cmp.6_slow_1100mv_85c.tdbbin83729 -> 80333 bytes
-rw-r--r--part_2/ex9/db/ex9.tis_db_list.ddbbin301 -> 297 bytes
-rw-r--r--part_2/ex9/db/ex9.tiscmp.fast_1100mv_0c.ddbbin415471 -> 420677 bytes
-rw-r--r--part_2/ex9/db/ex9.tiscmp.fast_1100mv_85c.ddbbin405563 -> 411392 bytes
-rw-r--r--part_2/ex9/db/ex9.tiscmp.slow_1100mv_0c.ddbbin408684 -> 414547 bytes
-rw-r--r--part_2/ex9/db/ex9.tiscmp.slow_1100mv_85c.ddbbin418017 -> 423547 bytes
-rw-r--r--part_2/ex9/db/ex9.tmw_info12
-rw-r--r--part_2/ex9/db/ex9.vpr.ammdbbin779 -> 764 bytes
-rw-r--r--part_2/ex9/db/ex9_partition_pins.json400
-rw-r--r--part_2/ex9/ex9.qsf2
-rw-r--r--part_2/ex9/ex9.qwsbin2491 -> 0 bytes
-rw-r--r--part_2/ex9/ex9_assignment_defaults.qdf795
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.db_info6
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdbbin7745 -> 824 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdbbin180274 -> 183230 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdbbin1946 -> 2117 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdbbin20763 -> 21162 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdbbin20951 -> 21359 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb2
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdbbin42337 -> 42565 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.cdbbin15957 -> 16082 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.dpibin1937 -> 1943 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdbbin1446 -> 1594 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdbbin20163 -> 20564 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hdbbin20696 -> 20333 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.kptbin2812 -> 2786 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdbbin764 -> 0 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdbbin3586 -> 0 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdbbin16989 -> 0 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.opi1
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdbbin764 -> 0 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdbbin4612 -> 0 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdbbin32134 -> 0 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdbbin15957 -> 0 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdbbin1446 -> 0 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdbbin20163 -> 0 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdbbin20696 -> 0 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.rrp.hdbbin21513 -> 22524 bytes
-rw-r--r--part_2/ex9/incremental_db/compiled_partitions/ex9.rrs.cdbbin402 -> 274 bytes
-rw-r--r--part_2/ex9/output_files/ex9.asm.rpt184
-rw-r--r--part_2/ex9/output_files/ex9.done2
-rw-r--r--part_2/ex9/output_files/ex9.fit.rpt4258
-rw-r--r--part_2/ex9/output_files/ex9.fit.smsg12
-rw-r--r--part_2/ex9/output_files/ex9.fit.summary40
-rw-r--r--part_2/ex9/output_files/ex9.flow.rpt256
-rw-r--r--part_2/ex9/output_files/ex9.jdi16
-rw-r--r--part_2/ex9/output_files/ex9.map.rpt1232
-rw-r--r--part_2/ex9/output_files/ex9.map.smsg74
-rw-r--r--part_2/ex9/output_files/ex9.map.summary34
-rw-r--r--part_2/ex9/output_files/ex9.pin1953
-rw-r--r--part_2/ex9/output_files/ex9.sld2
-rw-r--r--part_2/ex9/output_files/ex9.sofbin6690331 -> 6690318 bytes
-rw-r--r--part_2/ex9/output_files/ex9.sta.rpt2010
-rw-r--r--part_2/ex9/output_files/ex9.sta.summary298
-rw-r--r--part_2/ex9/verilog_files/formula_fsm.v104
363 files changed, 23465 insertions, 20978 deletions
diff --git a/part_2/ex6/c5_pin_model_dump.txt b/part_2/ex6/c5_pin_model_dump.txt
index a895a64..31bb72c 100755
--- a/part_2/ex6/c5_pin_model_dump.txt
+++ b/part_2/ex6/c5_pin_model_dump.txt
@@ -1,118 +1,118 @@
-io_4iomodule_c5_index: 55gpio_index: 2
-io_4iomodule_c5_index: 54gpio_index: 465
-io_4iomodule_c5_index: 33gpio_index: 6
-io_4iomodule_c5_index: 51gpio_index: 461
-io_4iomodule_c5_index: 27gpio_index: 10
-io_4iomodule_c5_index: 57gpio_index: 457
-io_4iomodule_c5_index: 34gpio_index: 14
-io_4iomodule_c5_index: 28gpio_index: 453
-io_4iomodule_c5_index: 26gpio_index: 19
-io_4iomodule_c5_index: 47gpio_index: 449
-io_4iomodule_c5_index: 29gpio_index: 22
-io_4iomodule_c5_index: 3gpio_index: 445
-io_4iomodule_c5_index: 16gpio_index: 27
-io_4iomodule_c5_index: 6gpio_index: 441
-io_4iomodule_c5_index: 50gpio_index: 30
-io_4iomodule_c5_index: 35gpio_index: 437
-io_4iomodule_c5_index: 7gpio_index: 35
-io_4iomodule_c5_index: 53gpio_index: 433
-io_4iomodule_c5_index: 12gpio_index: 38
-io_4iomodule_c5_index: 1gpio_index: 429
-io_4iomodule_c5_index: 22gpio_index: 43
-io_4iomodule_c5_index: 8gpio_index: 425
-io_4iomodule_c5_index: 20gpio_index: 46
-io_4iomodule_c5_index: 30gpio_index: 421
-io_4iomodule_c5_index: 2gpio_index: 51
-io_4iomodule_c5_index: 31gpio_index: 417
-io_4iomodule_c5_index: 39gpio_index: 54
-io_4iomodule_c5_index: 18gpio_index: 413
-io_4iomodule_c5_index: 10gpio_index: 59
-io_4iomodule_c5_index: 42gpio_index: 409
-io_4iomodule_c5_index: 5gpio_index: 62
-io_4iomodule_c5_index: 24gpio_index: 405
-io_4iomodule_c5_index: 37gpio_index: 67
-io_4iomodule_c5_index: 13gpio_index: 401
-io_4iomodule_c5_index: 0gpio_index: 70
-io_4iomodule_c5_index: 44gpio_index: 397
-io_4iomodule_c5_index: 38gpio_index: 75
-io_4iomodule_c5_index: 52gpio_index: 393
-io_4iomodule_c5_index: 32gpio_index: 78
-io_4iomodule_c5_index: 56gpio_index: 389
-io_4iomodule_a_index: 13gpio_index: 385
-io_4iomodule_c5_index: 4gpio_index: 83
-io_4iomodule_c5_index: 23gpio_index: 86
-io_4iomodule_a_index: 15gpio_index: 381
-io_4iomodule_a_index: 8gpio_index: 377
-io_4iomodule_c5_index: 46gpio_index: 91
-io_4iomodule_a_index: 5gpio_index: 373
-io_4iomodule_a_index: 11gpio_index: 369
-io_4iomodule_c5_index: 41gpio_index: 94
-io_4iomodule_a_index: 3gpio_index: 365
-io_4iomodule_c5_index: 25gpio_index: 99
-io_4iomodule_a_index: 7gpio_index: 361
-io_4iomodule_c5_index: 9gpio_index: 102
-io_4iomodule_a_index: 0gpio_index: 357
-io_4iomodule_c5_index: 14gpio_index: 107
-io_4iomodule_a_index: 12gpio_index: 353
-io_4iomodule_c5_index: 45gpio_index: 110
-io_4iomodule_c5_index: 17gpio_index: 115
-io_4iomodule_a_index: 4gpio_index: 349
-io_4iomodule_c5_index: 36gpio_index: 118
-io_4iomodule_a_index: 10gpio_index: 345
-io_4iomodule_a_index: 16gpio_index: 341
-io_4iomodule_c5_index: 15gpio_index: 123
-io_4iomodule_a_index: 14gpio_index: 337
-io_4iomodule_c5_index: 43gpio_index: 126
-io_4iomodule_c5_index: 19gpio_index: 131
-io_4iomodule_a_index: 1gpio_index: 333
-io_4iomodule_c5_index: 59gpio_index: 134
-io_4iomodule_a_index: 2gpio_index: 329
-io_4iomodule_a_index: 9gpio_index: 325
-io_4iomodule_c5_index: 48gpio_index: 139
-io_4iomodule_a_index: 6gpio_index: 321
-io_4iomodule_a_index: 17gpio_index: 317
-io_4iomodule_c5_index: 40gpio_index: 142
-io_4iomodule_c5_index: 11gpio_index: 147
-io_4iomodule_c5_index: 58gpio_index: 150
-io_4iomodule_c5_index: 21gpio_index: 155
-io_4iomodule_c5_index: 49gpio_index: 158
-io_4iomodule_h_c5_index: 0gpio_index: 161
-io_4iomodule_h_c5_index: 6gpio_index: 165
-io_4iomodule_h_c5_index: 10gpio_index: 169
-io_4iomodule_h_c5_index: 3gpio_index: 173
-io_4iomodule_h_c5_index: 8gpio_index: 176
-io_4iomodule_h_c5_index: 11gpio_index: 180
-io_4iomodule_h_c5_index: 7gpio_index: 184
-io_4iomodule_h_c5_index: 5gpio_index: 188
-io_4iomodule_h_c5_index: 1gpio_index: 192
-io_4iomodule_h_c5_index: 2gpio_index: 196
-io_4iomodule_h_c5_index: 9gpio_index: 200
-io_4iomodule_h_c5_index: 4gpio_index: 204
-io_4iomodule_h_index: 15gpio_index: 208
-io_4iomodule_h_index: 1gpio_index: 212
-io_4iomodule_h_index: 3gpio_index: 216
-io_4iomodule_h_index: 2gpio_index: 220
-io_4iomodule_h_index: 11gpio_index: 224
-io_4iomodule_vref_h_index: 1gpio_index: 228
-io_4iomodule_h_index: 20gpio_index: 231
-io_4iomodule_h_index: 8gpio_index: 235
-io_4iomodule_h_index: 6gpio_index: 239
-io_4iomodule_h_index: 10gpio_index: 243
-io_4iomodule_h_index: 23gpio_index: 247
-io_4iomodule_h_index: 7gpio_index: 251
-io_4iomodule_h_index: 22gpio_index: 255
-io_4iomodule_h_index: 5gpio_index: 259
-io_4iomodule_h_index: 24gpio_index: 263
-io_4iomodule_h_index: 0gpio_index: 267
-io_4iomodule_h_index: 13gpio_index: 271
-io_4iomodule_h_index: 21gpio_index: 275
-io_4iomodule_h_index: 16gpio_index: 279
-io_4iomodule_vref_h_index: 0gpio_index: 283
-io_4iomodule_h_index: 12gpio_index: 286
-io_4iomodule_h_index: 4gpio_index: 290
-io_4iomodule_h_index: 19gpio_index: 294
-io_4iomodule_h_index: 18gpio_index: 298
-io_4iomodule_h_index: 17gpio_index: 302
-io_4iomodule_h_index: 25gpio_index: 306
-io_4iomodule_h_index: 14gpio_index: 310
-io_4iomodule_h_index: 9gpio_index: 314
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_2/ex6/db/.cmp.kpt b/part_2/ex6/db/.cmp.kpt
index 38aa87b..a87068f 100755
--- a/part_2/ex6/db/.cmp.kpt
+++ b/part_2/ex6/db/.cmp.kpt
Binary files differ
diff --git a/part_2/ex6/db/ex6.(0).cnf.cdb b/part_2/ex6/db/ex6.(0).cnf.cdb
index e44f8a1..15f19bc 100755
--- a/part_2/ex6/db/ex6.(0).cnf.cdb
+++ b/part_2/ex6/db/ex6.(0).cnf.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.(0).cnf.hdb b/part_2/ex6/db/ex6.(0).cnf.hdb
index de77324..b973444 100755
--- a/part_2/ex6/db/ex6.(0).cnf.hdb
+++ b/part_2/ex6/db/ex6.(0).cnf.hdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.(1).cnf.cdb b/part_2/ex6/db/ex6.(1).cnf.cdb
index 4079d9b..70d8f69 100755
--- a/part_2/ex6/db/ex6.(1).cnf.cdb
+++ b/part_2/ex6/db/ex6.(1).cnf.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.(1).cnf.hdb b/part_2/ex6/db/ex6.(1).cnf.hdb
index 39c74f3..4ce43db 100755
--- a/part_2/ex6/db/ex6.(1).cnf.hdb
+++ b/part_2/ex6/db/ex6.(1).cnf.hdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.(2).cnf.cdb b/part_2/ex6/db/ex6.(2).cnf.cdb
index c1f3aaf..e19eb61 100755
--- a/part_2/ex6/db/ex6.(2).cnf.cdb
+++ b/part_2/ex6/db/ex6.(2).cnf.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.(2).cnf.hdb b/part_2/ex6/db/ex6.(2).cnf.hdb
index ebbfbca..971fb3d 100755
--- a/part_2/ex6/db/ex6.(2).cnf.hdb
+++ b/part_2/ex6/db/ex6.(2).cnf.hdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.(3).cnf.cdb b/part_2/ex6/db/ex6.(3).cnf.cdb
index adf12ca..3593c12 100755
--- a/part_2/ex6/db/ex6.(3).cnf.cdb
+++ b/part_2/ex6/db/ex6.(3).cnf.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.(3).cnf.hdb b/part_2/ex6/db/ex6.(3).cnf.hdb
index 3d54105..900e5a3 100755
--- a/part_2/ex6/db/ex6.(3).cnf.hdb
+++ b/part_2/ex6/db/ex6.(3).cnf.hdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.(4).cnf.cdb b/part_2/ex6/db/ex6.(4).cnf.cdb
index 9bd5391..742ef6f 100755
--- a/part_2/ex6/db/ex6.(4).cnf.cdb
+++ b/part_2/ex6/db/ex6.(4).cnf.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.(4).cnf.hdb b/part_2/ex6/db/ex6.(4).cnf.hdb
index 88032e3..9f10e3d 100755
--- a/part_2/ex6/db/ex6.(4).cnf.hdb
+++ b/part_2/ex6/db/ex6.(4).cnf.hdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.(5).cnf.cdb b/part_2/ex6/db/ex6.(5).cnf.cdb
index 7e272ba..ccc0067 100755
--- a/part_2/ex6/db/ex6.(5).cnf.cdb
+++ b/part_2/ex6/db/ex6.(5).cnf.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.(5).cnf.hdb b/part_2/ex6/db/ex6.(5).cnf.hdb
index 74844fd..fc48afc 100755
--- a/part_2/ex6/db/ex6.(5).cnf.hdb
+++ b/part_2/ex6/db/ex6.(5).cnf.hdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.ae.hdb b/part_2/ex6/db/ex6.ae.hdb
deleted file mode 100755
index b847279..0000000
--- a/part_2/ex6/db/ex6.ae.hdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/db/ex6.analyze_file.qmsg b/part_2/ex6/db/ex6.analyze_file.qmsg
deleted file mode 100755
index 44ee136..0000000
--- a/part_2/ex6/db/ex6.analyze_file.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479812643770 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479812643771 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:04:03 2016 " "Processing started: Tue Nov 22 11:04:03 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479812643771 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479812643771 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 --analyze_file=\"C:/New folder/ex6/ex6.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 --analyze_file=\"C:/New folder/ex6/ex6.v\"" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479812643772 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479812644221 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479812644221 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1 Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "832 " "Peak virtual memory: 832 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479812652563 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:04:12 2016 " "Processing ended: Tue Nov 22 11:04:12 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479812652563 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479812652563 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479812652563 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479812652563 ""}
diff --git a/part_2/ex6/db/ex6.asm.qmsg b/part_2/ex6/db/ex6.asm.qmsg
index f23ddd0..2fb3897 100755
--- a/part_2/ex6/db/ex6.asm.qmsg
+++ b/part_2/ex6/db/ex6.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479815014816 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479815014818 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:43:34 2016 " "Processing started: Tue Nov 22 11:43:34 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479815014818 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479815014818 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479815014818 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479815015570 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479815020100 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "893 " "Peak virtual memory: 893 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479815020437 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:40 2016 " "Processing ended: Tue Nov 22 11:43:40 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479815020437 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479815020437 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479815020437 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479815020437 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481479710522 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481479710535 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 18:08:30 2016 " "Processing started: Sun Dec 11 18:08:30 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481479710535 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481479710535 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481479710535 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481479711198 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481479716231 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "976 " "Peak virtual memory: 976 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481479716578 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 18:08:36 2016 " "Processing ended: Sun Dec 11 18:08:36 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481479716578 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481479716578 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481479716578 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481479716578 ""}
diff --git a/part_2/ex6/db/ex6.asm.rdb b/part_2/ex6/db/ex6.asm.rdb
index 0ef85b8..db1450b 100755
--- a/part_2/ex6/db/ex6.asm.rdb
+++ b/part_2/ex6/db/ex6.asm.rdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.cbx.xml b/part_2/ex6/db/ex6.cbx.xml
index 8b16f5b..1e74979 100755
--- a/part_2/ex6/db/ex6.cbx.xml
+++ b/part_2/ex6/db/ex6.cbx.xml
@@ -1,5 +1,5 @@
-<?xml version="1.0" ?>
-<LOG_ROOT>
- <PROJECT NAME="ex6">
- </PROJECT>
-</LOG_ROOT>
+<?xml version="1.0" ?>
+<LOG_ROOT>
+ <PROJECT NAME="ex6">
+ </PROJECT>
+</LOG_ROOT>
diff --git a/part_2/ex6/db/ex6.cmp.ammdb b/part_2/ex6/db/ex6.cmp.ammdb
deleted file mode 100755
index 14e19ae..0000000
--- a/part_2/ex6/db/ex6.cmp.ammdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/db/ex6.cmp.bpm b/part_2/ex6/db/ex6.cmp.bpm
index 9fc0368..513167e 100755
--- a/part_2/ex6/db/ex6.cmp.bpm
+++ b/part_2/ex6/db/ex6.cmp.bpm
Binary files differ
diff --git a/part_2/ex6/db/ex6.cmp.cdb b/part_2/ex6/db/ex6.cmp.cdb
index f2b998b..e2b2023 100755
--- a/part_2/ex6/db/ex6.cmp.cdb
+++ b/part_2/ex6/db/ex6.cmp.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.cmp.hdb b/part_2/ex6/db/ex6.cmp.hdb
index 4c3f7f7..3dcd013 100755
--- a/part_2/ex6/db/ex6.cmp.hdb
+++ b/part_2/ex6/db/ex6.cmp.hdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.cmp.idb b/part_2/ex6/db/ex6.cmp.idb
index 08a2505..189a33e 100755
--- a/part_2/ex6/db/ex6.cmp.idb
+++ b/part_2/ex6/db/ex6.cmp.idb
Binary files differ
diff --git a/part_2/ex6/db/ex6.cmp.logdb b/part_2/ex6/db/ex6.cmp.logdb
index b26a4d2..2c1b2b8 100755
--- a/part_2/ex6/db/ex6.cmp.logdb
+++ b/part_2/ex6/db/ex6.cmp.logdb
@@ -1,77 +1,77 @@
-v1
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
-IO_RULES_MATRIX,Total Pass,38;0;38;0;0;38;38;0;38;38;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,0;38;0;38;38;0;0;38;0;0;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,28,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
+v1
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000003;IO_000001;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000022;IO_000021;IO_000046;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000047;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
+IO_RULES_MATRIX,Total Pass,0;38;38;0;0;38;38;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;38;38;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,38;0;0;38;38;0;0;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;0;0;38,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_2/ex6/db/ex6.cmp.rdb b/part_2/ex6/db/ex6.cmp.rdb
index 2650c4f..ddee90b 100755
--- a/part_2/ex6/db/ex6.cmp.rdb
+++ b/part_2/ex6/db/ex6.cmp.rdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.cmp_merge.kpt b/part_2/ex6/db/ex6.cmp_merge.kpt
index ee1a16d..432d0d8 100755
--- a/part_2/ex6/db/ex6.cmp_merge.kpt
+++ b/part_2/ex6/db/ex6.cmp_merge.kpt
Binary files differ
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsd
index 5b115d6..f484435 100755
--- a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsd
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsd
Binary files differ
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsd
index 3a7a497..8ebe269 100755
--- a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsd
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsd
Binary files differ
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsd
index aa473fa..8d531ee 100755
--- a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsd
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsd
Binary files differ
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsd
index dce4f6b..29d0225 100755
--- a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsd
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsd
Binary files differ
diff --git a/part_2/ex6/db/ex6.db_info b/part_2/ex6/db/ex6.db_info
index d880372..4f976f6 100755
--- a/part_2/ex6/db/ex6.db_info
+++ b/part_2/ex6/db/ex6.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Version_Index = 402707200
-Creation_Time = Tue Nov 22 11:44:41 2016
+Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Version_Index = 419480576
+Creation_Time = Sun Dec 11 17:54:40 2016
diff --git a/part_2/ex6/db/ex6.fit.qmsg b/part_2/ex6/db/ex6.fit.qmsg
index 520ed32..dd491d6 100755
--- a/part_2/ex6/db/ex6.fit.qmsg
+++ b/part_2/ex6/db/ex6.fit.qmsg
@@ -1,45 +1,46 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479814984340 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479814984340 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex6 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex6\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479814984583 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814984640 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814984640 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479814985024 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479814985159 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479814995125 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1479814995207 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1479814995207 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814995207 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479814995209 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814995210 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814995210 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479814995211 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479814995211 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479814995211 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479814995211 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479814995211 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479814995211 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479814995247 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814995249 ""}
-{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1479815000743 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815000745 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1479815000745 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479815000746 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1479815000747 ""}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1479815000747 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479815000747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479815000747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479815000747 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1479815000747 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479815000751 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479815000837 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815001449 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479815002122 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479815002452 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815002452 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479815003554 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" { } { { "loc" "" { Generic "C:/New folder/ex6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479815008086 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479815008086 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479815008384 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479815008384 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479815008384 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815008388 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479815009521 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479815009559 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479815009945 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479815009945 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479815010330 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815012667 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479815012909 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.fit.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479815012966 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 48 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 48 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2591 " "Peak virtual memory: 2591 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479815013395 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:33 2016 " "Processing ended: Tue Nov 22 11:43:33 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479815013395 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479815013395 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:53 " "Total CPU time (on all processors): 00:00:53" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479815013395 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479815013395 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481479681292 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481479681292 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex6 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex6\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481479681298 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481479681329 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481479681329 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481479681733 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1481479681754 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481479681813 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481479692596 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481479692676 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481479692676 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479692676 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481479692680 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481479692680 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481479692681 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481479692681 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481479692681 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481479692681 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481479692681 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481479692682 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481479692682 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481479692720 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479692722 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1481479697536 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481479697538 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1481479697538 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481479697539 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481479697539 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1481479697539 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481479697540 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481479697540 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481479697540 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1481479697540 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481479697546 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481479697639 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479698137 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481479698776 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481479699121 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479699121 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481479700015 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y11 X89_Y22 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22" { } { { "loc" "" { Generic "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22"} { { 12 { 0 ""} 78 11 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481479704739 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481479704739 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481479705011 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1481479705011 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481479705011 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479705013 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.14 " "Total time spent on timing analysis during the Fitter is 0.14 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481479706219 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481479706252 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481479706612 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481479706612 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481479706949 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479708912 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481479709016 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481479709072 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 49 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 49 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2132 " "Peak virtual memory: 2132 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481479709421 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 18:08:29 2016 " "Processing ended: Sun Dec 11 18:08:29 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481479709421 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Elapsed time: 00:00:29" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481479709421 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481479709421 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481479709421 ""}
diff --git a/part_2/ex6/db/ex6.hier_info b/part_2/ex6/db/ex6.hier_info
index df23cf1..35806ed 100755
--- a/part_2/ex6/db/ex6.hier_info
+++ b/part_2/ex6/db/ex6.hier_info
@@ -1,557 +1,557 @@
-|ex6
-CLOCK_50 => CLOCK_50.IN1
-KEY[0] => _.IN1
-KEY[1] => _.IN1
-HEX0[0] <= hex_to_7seg:SEG0.port0
-HEX0[1] <= hex_to_7seg:SEG0.port0
-HEX0[2] <= hex_to_7seg:SEG0.port0
-HEX0[3] <= hex_to_7seg:SEG0.port0
-HEX0[4] <= hex_to_7seg:SEG0.port0
-HEX0[5] <= hex_to_7seg:SEG0.port0
-HEX0[6] <= hex_to_7seg:SEG0.port0
-HEX1[0] <= hex_to_7seg:SEG1.port0
-HEX1[1] <= hex_to_7seg:SEG1.port0
-HEX1[2] <= hex_to_7seg:SEG1.port0
-HEX1[3] <= hex_to_7seg:SEG1.port0
-HEX1[4] <= hex_to_7seg:SEG1.port0
-HEX1[5] <= hex_to_7seg:SEG1.port0
-HEX1[6] <= hex_to_7seg:SEG1.port0
-HEX2[0] <= hex_to_7seg:SEG2.port0
-HEX2[1] <= hex_to_7seg:SEG2.port0
-HEX2[2] <= hex_to_7seg:SEG2.port0
-HEX2[3] <= hex_to_7seg:SEG2.port0
-HEX2[4] <= hex_to_7seg:SEG2.port0
-HEX2[5] <= hex_to_7seg:SEG2.port0
-HEX2[6] <= hex_to_7seg:SEG2.port0
-HEX3[0] <= hex_to_7seg:SEG3.port0
-HEX3[1] <= hex_to_7seg:SEG3.port0
-HEX3[2] <= hex_to_7seg:SEG3.port0
-HEX3[3] <= hex_to_7seg:SEG3.port0
-HEX3[4] <= hex_to_7seg:SEG3.port0
-HEX3[5] <= hex_to_7seg:SEG3.port0
-HEX3[6] <= hex_to_7seg:SEG3.port0
-HEX4[0] <= hex_to_7seg:SEG4.port0
-HEX4[1] <= hex_to_7seg:SEG4.port0
-HEX4[2] <= hex_to_7seg:SEG4.port0
-HEX4[3] <= hex_to_7seg:SEG4.port0
-HEX4[4] <= hex_to_7seg:SEG4.port0
-HEX4[5] <= hex_to_7seg:SEG4.port0
-HEX4[6] <= hex_to_7seg:SEG4.port0
-
-
-|ex6|tick_50000:tck
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => count[12].CLK
-CLOCK_IN => count[13].CLK
-CLOCK_IN => count[14].CLK
-CLOCK_IN => count[15].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|counter_16:C
-clock => count[0]~reg0.CLK
-clock => count[1]~reg0.CLK
-clock => count[2]~reg0.CLK
-clock => count[3]~reg0.CLK
-clock => count[4]~reg0.CLK
-clock => count[5]~reg0.CLK
-clock => count[6]~reg0.CLK
-clock => count[7]~reg0.CLK
-clock => count[8]~reg0.CLK
-clock => count[9]~reg0.CLK
-clock => count[10]~reg0.CLK
-clock => count[11]~reg0.CLK
-clock => count[12]~reg0.CLK
-clock => count[13]~reg0.CLK
-clock => count[14]~reg0.CLK
-clock => count[15]~reg0.CLK
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B
-B[0] => BCD_0[0].DATAIN
-B[1] => w29[0].IN1
-B[2] => w25[0].IN1
-B[3] => w21[0].IN1
-B[4] => w17[0].IN1
-B[5] => w14[0].IN1
-B[6] => w11[0].IN1
-B[7] => w8[0].IN1
-B[8] => w6[0].IN1
-B[9] => w4[0].IN1
-B[10] => w2[0].IN1
-B[11] => w1[0].IN1
-B[12] => w1[1].IN1
-B[13] => w1[2].IN1
-B[14] => w1[3].IN1
-B[15] => w3[2].IN1
-BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
-BCD_0[1] <= add3_ge5:A29.port1
-BCD_0[2] <= add3_ge5:A29.port1
-BCD_0[3] <= add3_ge5:A29.port1
-BCD_1[0] <= add3_ge5:A29.port1
-BCD_1[1] <= add3_ge5:A28.port1
-BCD_1[2] <= add3_ge5:A28.port1
-BCD_1[3] <= add3_ge5:A28.port1
-BCD_2[0] <= add3_ge5:A28.port1
-BCD_2[1] <= add3_ge5:A27.port1
-BCD_2[2] <= add3_ge5:A27.port1
-BCD_2[3] <= add3_ge5:A27.port1
-BCD_3[0] <= add3_ge5:A27.port1
-BCD_3[1] <= add3_ge5:A26.port1
-BCD_3[2] <= add3_ge5:A26.port1
-BCD_3[3] <= add3_ge5:A26.port1
-BCD_4[0] <= add3_ge5:A26.port1
-BCD_4[1] <= add3_ge5:A22.port1
-BCD_4[2] <= add3_ge5:A18.port1
-BCD_4[3] <= <GND>
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A1
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A2
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A3
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A4
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A5
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A6
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A7
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A8
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A9
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A10
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A11
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A12
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A13
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A14
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A15
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A16
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A17
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A18
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A19
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A20
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A21
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A22
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A23
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A24
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A25
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A26
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A27
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A28
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A29
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|hex_to_7seg:SEG0
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex6|hex_to_7seg:SEG1
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex6|hex_to_7seg:SEG2
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex6|hex_to_7seg:SEG3
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex6|hex_to_7seg:SEG4
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
+|ex6
+CLOCK_50 => CLOCK_50.IN1
+KEY[0] => _.IN1
+KEY[1] => _.IN1
+HEX0[0] << hex_to_7seg:SEG0.port0
+HEX0[1] << hex_to_7seg:SEG0.port0
+HEX0[2] << hex_to_7seg:SEG0.port0
+HEX0[3] << hex_to_7seg:SEG0.port0
+HEX0[4] << hex_to_7seg:SEG0.port0
+HEX0[5] << hex_to_7seg:SEG0.port0
+HEX0[6] << hex_to_7seg:SEG0.port0
+HEX1[0] << hex_to_7seg:SEG1.port0
+HEX1[1] << hex_to_7seg:SEG1.port0
+HEX1[2] << hex_to_7seg:SEG1.port0
+HEX1[3] << hex_to_7seg:SEG1.port0
+HEX1[4] << hex_to_7seg:SEG1.port0
+HEX1[5] << hex_to_7seg:SEG1.port0
+HEX1[6] << hex_to_7seg:SEG1.port0
+HEX2[0] << hex_to_7seg:SEG2.port0
+HEX2[1] << hex_to_7seg:SEG2.port0
+HEX2[2] << hex_to_7seg:SEG2.port0
+HEX2[3] << hex_to_7seg:SEG2.port0
+HEX2[4] << hex_to_7seg:SEG2.port0
+HEX2[5] << hex_to_7seg:SEG2.port0
+HEX2[6] << hex_to_7seg:SEG2.port0
+HEX3[0] << hex_to_7seg:SEG3.port0
+HEX3[1] << hex_to_7seg:SEG3.port0
+HEX3[2] << hex_to_7seg:SEG3.port0
+HEX3[3] << hex_to_7seg:SEG3.port0
+HEX3[4] << hex_to_7seg:SEG3.port0
+HEX3[5] << hex_to_7seg:SEG3.port0
+HEX3[6] << hex_to_7seg:SEG3.port0
+HEX4[0] << hex_to_7seg:SEG4.port0
+HEX4[1] << hex_to_7seg:SEG4.port0
+HEX4[2] << hex_to_7seg:SEG4.port0
+HEX4[3] << hex_to_7seg:SEG4.port0
+HEX4[4] << hex_to_7seg:SEG4.port0
+HEX4[5] << hex_to_7seg:SEG4.port0
+HEX4[6] << hex_to_7seg:SEG4.port0
+
+
+|ex6|tick_50000:tck
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => count[12].CLK
+CLOCK_IN => count[13].CLK
+CLOCK_IN => count[14].CLK
+CLOCK_IN => count[15].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|counter_16:C
+clock => count[0]~reg0.CLK
+clock => count[1]~reg0.CLK
+clock => count[2]~reg0.CLK
+clock => count[3]~reg0.CLK
+clock => count[4]~reg0.CLK
+clock => count[5]~reg0.CLK
+clock => count[6]~reg0.CLK
+clock => count[7]~reg0.CLK
+clock => count[8]~reg0.CLK
+clock => count[9]~reg0.CLK
+clock => count[10]~reg0.CLK
+clock => count[11]~reg0.CLK
+clock => count[12]~reg0.CLK
+clock => count[13]~reg0.CLK
+clock => count[14]~reg0.CLK
+clock => count[15]~reg0.CLK
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B
+B[0] => BCD_0[0].DATAIN
+B[1] => w29[0].IN1
+B[2] => w25[0].IN1
+B[3] => w21[0].IN1
+B[4] => w17[0].IN1
+B[5] => w14[0].IN1
+B[6] => w11[0].IN1
+B[7] => w8[0].IN1
+B[8] => w6[0].IN1
+B[9] => w4[0].IN1
+B[10] => w2[0].IN1
+B[11] => w1[0].IN1
+B[12] => w1[1].IN1
+B[13] => w1[2].IN1
+B[14] => w1[3].IN1
+B[15] => w3[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A29.port1
+BCD_0[2] <= add3_ge5:A29.port1
+BCD_0[3] <= add3_ge5:A29.port1
+BCD_1[0] <= add3_ge5:A29.port1
+BCD_1[1] <= add3_ge5:A28.port1
+BCD_1[2] <= add3_ge5:A28.port1
+BCD_1[3] <= add3_ge5:A28.port1
+BCD_2[0] <= add3_ge5:A28.port1
+BCD_2[1] <= add3_ge5:A27.port1
+BCD_2[2] <= add3_ge5:A27.port1
+BCD_2[3] <= add3_ge5:A27.port1
+BCD_3[0] <= add3_ge5:A27.port1
+BCD_3[1] <= add3_ge5:A26.port1
+BCD_3[2] <= add3_ge5:A26.port1
+BCD_3[3] <= add3_ge5:A26.port1
+BCD_4[0] <= add3_ge5:A26.port1
+BCD_4[1] <= add3_ge5:A22.port1
+BCD_4[2] <= add3_ge5:A18.port1
+BCD_4[3] <= <GND>
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A1
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A2
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A3
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A4
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A5
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A6
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A7
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A8
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A9
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A10
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A11
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A12
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A13
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A14
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A15
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A16
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A17
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A18
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A19
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A20
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A21
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A22
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A23
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A24
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A25
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A26
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A27
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A28
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A29
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
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diff --git a/part_2/ex6/db/ex6.hif b/part_2/ex6/db/ex6.hif
index 922b5ce..f1930bf 100755
--- a/part_2/ex6/db/ex6.hif
+++ b/part_2/ex6/db/ex6.hif
Binary files differ
diff --git a/part_2/ex6/db/ex6.lpc.html b/part_2/ex6/db/ex6.lpc.html
index 86c7f81..e1700bc 100755
--- a/part_2/ex6/db/ex6.lpc.html
+++ b/part_2/ex6/db/ex6.lpc.html
@@ -1,610 +1,610 @@
-<TABLE>
-<TR bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-<TR >
-<TD >SEG4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG3</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG1</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A29</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A28</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A27</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A26</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A25</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A24</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A23</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A22</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A21</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A20</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A19</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A18</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A17</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A16</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A15</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A14</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A13</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A12</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A11</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A10</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A9</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A8</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A7</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A6</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A5</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A3</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A1</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B</TD>
-<TD >16</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >20</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >C</TD>
-<TD >3</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >16</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >tck</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-</TABLE>
+<TABLE>
+<TR bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A29</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A28</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A27</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A26</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A25</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A24</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A23</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A22</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A21</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A20</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A19</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A18</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A17</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A16</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A15</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A14</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A13</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A12</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A11</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A10</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A9</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A3</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B</TD>
+<TD >16</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >20</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >C</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >tck</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_2/ex6/db/ex6.lpc.rdb b/part_2/ex6/db/ex6.lpc.rdb
index 0635761..c83ad8a 100755
--- a/part_2/ex6/db/ex6.lpc.rdb
+++ b/part_2/ex6/db/ex6.lpc.rdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.lpc.txt b/part_2/ex6/db/ex6.lpc.txt
index f2fb5a2..f546b48 100755
--- a/part_2/ex6/db/ex6.lpc.txt
+++ b/part_2/ex6/db/ex6.lpc.txt
@@ -1,43 +1,43 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; SEG4 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; SEG3 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; SEG2 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; SEG1 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; SEG0 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A29 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A28 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A27 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A26 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A25 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A24 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A23 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A22 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A21 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A20 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A19 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A18 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A17 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A16 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A15 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A14 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A13 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A12 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A11 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A10 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A9 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A8 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A7 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A6 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A5 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A4 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A3 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A2 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B|A1 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; B ; 16 ; 1 ; 0 ; 1 ; 20 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; C ; 3 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; tck ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG4 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG3 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG2 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG1 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG0 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A29 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A28 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A27 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A26 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A25 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A24 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A23 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A22 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A21 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A20 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A19 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A18 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A17 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A16 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A15 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A14 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A13 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A12 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A11 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A10 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A9 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A8 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A7 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A6 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A5 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A4 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A3 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A2 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B|A1 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; B ; 16 ; 1 ; 0 ; 1 ; 20 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; C ; 3 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; tck ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_2/ex6/db/ex6.map.ammdb b/part_2/ex6/db/ex6.map.ammdb
index 174eb00..a4afc79 100755
--- a/part_2/ex6/db/ex6.map.ammdb
+++ b/part_2/ex6/db/ex6.map.ammdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.map.bpm b/part_2/ex6/db/ex6.map.bpm
index bb857d4..c10665c 100755
--- a/part_2/ex6/db/ex6.map.bpm
+++ b/part_2/ex6/db/ex6.map.bpm
Binary files differ
diff --git a/part_2/ex6/db/ex6.map.cdb b/part_2/ex6/db/ex6.map.cdb
index 728c972..0e9e5f2 100755
--- a/part_2/ex6/db/ex6.map.cdb
+++ b/part_2/ex6/db/ex6.map.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.map.hdb b/part_2/ex6/db/ex6.map.hdb
index 774cef6..230028c 100755
--- a/part_2/ex6/db/ex6.map.hdb
+++ b/part_2/ex6/db/ex6.map.hdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.map.kpt b/part_2/ex6/db/ex6.map.kpt
index 4c58c4c..1110780 100755
--- a/part_2/ex6/db/ex6.map.kpt
+++ b/part_2/ex6/db/ex6.map.kpt
Binary files differ
diff --git a/part_2/ex6/db/ex6.map.logdb b/part_2/ex6/db/ex6.map.logdb
index d45424f..626799f 100755
--- a/part_2/ex6/db/ex6.map.logdb
+++ b/part_2/ex6/db/ex6.map.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex6/db/ex6.map.qmsg b/part_2/ex6/db/ex6.map.qmsg
index 591b373..9e929a3 100755
--- a/part_2/ex6/db/ex6.map.qmsg
+++ b/part_2/ex6/db/ex6.map.qmsg
@@ -1,51 +1,50 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479814972603 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814972605 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:42:52 2016 " "Processing started: Tue Nov 22 11:42:52 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814972605 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814972605 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814972605 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479814973084 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479814973084 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex6/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981494 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981494 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981496 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex6/verilog_files/add3_ge5.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981498 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981498 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" { } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex6/verilog_files/counter_16.v" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981500 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981500 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex6.v 1 1 " "Found 1 design units, including 1 entities, in source file ex6.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex6 " "Found entity 1: ex6" { } { { "ex6.v" "" { Text "C:/New folder/ex6/ex6.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981503 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981503 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" { } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex6/verilog_files/tick_50000.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981504 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981504 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex6 " "Elaborating entity \"ex6\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479814981532 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:tck " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:tck\"" { } { { "ex6.v" "tck" { Text "C:/New folder/ex6/ex6.v" 11 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981539 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:C " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:C\"" { } { { "ex6.v" "C" { Text "C:/New folder/ex6/ex6.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981540 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:B " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:B\"" { } { { "ex6.v" "B" { Text "C:/New folder/ex6/ex6.v" 15 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981541 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:B\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:B\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981542 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "ex6.v" "SEG0" { Text "C:/New folder/ex6/ex6.v" 17 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981546 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479814982201 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.map.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814982507 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479814982587 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814982587 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "225 " "Implemented 225 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479814982622 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479814982622 ""} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Implemented 187 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479814982622 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479814982622 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "897 " "Peak virtual memory: 897 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814982634 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:02 2016 " "Processing ended: Tue Nov 22 11:43:02 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814982634 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814982634 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814982634 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814982634 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481479670637 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481479670651 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 18:07:50 2016 " "Processing started: Sun Dec 11 18:07:50 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481479670651 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479670651 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479670651 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481479670912 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481479670912 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679501 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679501 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679503 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/add3_ge5.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679504 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679504 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" { } { { "verilog_files/counter_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/counter_16.v" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679504 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679504 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex6.v 1 1 " "Found 1 design units, including 1 entities, in source file ex6.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex6 " "Found entity 1: ex6" { } { { "ex6.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679505 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679505 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" { } { { "verilog_files/tick_50000.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/tick_50000.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679505 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679505 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex6 " "Elaborating entity \"ex6\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481479679548 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:tck " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:tck\"" { } { { "ex6.v" "tck" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 11 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479679550 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:C " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:C\"" { } { { "ex6.v" "C" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479679550 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:B " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:B\"" { } { { "ex6.v" "B" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 15 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479679551 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:B\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:B\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_16.v" "A1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479679552 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "ex6.v" "SEG0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 17 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479679559 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481479680040 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481479680334 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479680334 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "225 " "Implemented 225 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481479680373 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481479680373 ""} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Implemented 187 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481479680373 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481479680373 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1071 " "Peak virtual memory: 1071 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481479680379 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 18:08:00 2016 " "Processing ended: Sun Dec 11 18:08:00 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481479680379 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481479680379 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481479680379 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479680379 ""}
diff --git a/part_2/ex6/db/ex6.map.rdb b/part_2/ex6/db/ex6.map.rdb
index 8b9a683..b328103 100755
--- a/part_2/ex6/db/ex6.map.rdb
+++ b/part_2/ex6/db/ex6.map.rdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.map_bb.cdb b/part_2/ex6/db/ex6.map_bb.cdb
index b4b07ef..21d85e3 100755
--- a/part_2/ex6/db/ex6.map_bb.cdb
+++ b/part_2/ex6/db/ex6.map_bb.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.map_bb.hdb b/part_2/ex6/db/ex6.map_bb.hdb
index d29fcef..7a1ee8d 100755
--- a/part_2/ex6/db/ex6.map_bb.hdb
+++ b/part_2/ex6/db/ex6.map_bb.hdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.map_bb.logdb b/part_2/ex6/db/ex6.map_bb.logdb
index d45424f..626799f 100755
--- a/part_2/ex6/db/ex6.map_bb.logdb
+++ b/part_2/ex6/db/ex6.map_bb.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex6/db/ex6.pre_map.cdb b/part_2/ex6/db/ex6.pre_map.cdb
deleted file mode 100755
index b754542..0000000
--- a/part_2/ex6/db/ex6.pre_map.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/db/ex6.pre_map.hdb b/part_2/ex6/db/ex6.pre_map.hdb
index 8df99d8..ed5b85a 100755
--- a/part_2/ex6/db/ex6.pre_map.hdb
+++ b/part_2/ex6/db/ex6.pre_map.hdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.quiproj.2528.rdr.flock b/part_2/ex6/db/ex6.quiproj.2528.rdr.flock
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex6/db/ex6.quiproj.2528.rdr.flock
diff --git a/part_2/ex6/db/ex6.root_partition.map.reg_db.cdb b/part_2/ex6/db/ex6.root_partition.map.reg_db.cdb
index 62aaf66..c5ac118 100755
--- a/part_2/ex6/db/ex6.root_partition.map.reg_db.cdb
+++ b/part_2/ex6/db/ex6.root_partition.map.reg_db.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.routing.rdb b/part_2/ex6/db/ex6.routing.rdb
index 3790313..8c6966f 100755
--- a/part_2/ex6/db/ex6.routing.rdb
+++ b/part_2/ex6/db/ex6.routing.rdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.rtlv.hdb b/part_2/ex6/db/ex6.rtlv.hdb
index ba7fb52..98d4df4 100755
--- a/part_2/ex6/db/ex6.rtlv.hdb
+++ b/part_2/ex6/db/ex6.rtlv.hdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.rtlv_sg.cdb b/part_2/ex6/db/ex6.rtlv_sg.cdb
index ca2154e..497481a 100755
--- a/part_2/ex6/db/ex6.rtlv_sg.cdb
+++ b/part_2/ex6/db/ex6.rtlv_sg.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.rtlv_sg_swap.cdb b/part_2/ex6/db/ex6.rtlv_sg_swap.cdb
index 69494b0..dc11731 100755
--- a/part_2/ex6/db/ex6.rtlv_sg_swap.cdb
+++ b/part_2/ex6/db/ex6.rtlv_sg_swap.cdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.sld_design_entry.sci b/part_2/ex6/db/ex6.sld_design_entry.sci
index 92c1102..03eacdc 100755
--- a/part_2/ex6/db/ex6.sld_design_entry.sci
+++ b/part_2/ex6/db/ex6.sld_design_entry.sci
Binary files differ
diff --git a/part_2/ex6/db/ex6.sld_design_entry_dsc.sci b/part_2/ex6/db/ex6.sld_design_entry_dsc.sci
index 92c1102..03eacdc 100755
--- a/part_2/ex6/db/ex6.sld_design_entry_dsc.sci
+++ b/part_2/ex6/db/ex6.sld_design_entry_dsc.sci
Binary files differ
diff --git a/part_2/ex6/db/ex6.smart_action.txt b/part_2/ex6/db/ex6.smart_action.txt
index 437a63e..c8e8a13 100755
--- a/part_2/ex6/db/ex6.smart_action.txt
+++ b/part_2/ex6/db/ex6.smart_action.txt
@@ -1 +1 @@
-DONE
+DONE
diff --git a/part_2/ex6/db/ex6.sta.qmsg b/part_2/ex6/db/ex6.sta.qmsg
index c1af911..4203916 100755
--- a/part_2/ex6/db/ex6.sta.qmsg
+++ b/part_2/ex6/db/ex6.sta.qmsg
@@ -1,50 +1,50 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479815021994 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479815021995 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:43:41 2016 " "Processing started: Tue Nov 22 11:43:41 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479815021995 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815021995 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex6 -c ex6 " "Command: quartus_sta ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815021995 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815022120 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022663 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022663 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022709 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022709 ""}
-{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023227 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815023230 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023230 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023231 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023231 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815023232 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815023239 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.377 " "Worst-case setup slack is 15.377" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 15.377 0.000 CLOCK_50 " " 15.377 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023245 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023245 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.388 " "Worst-case hold slack is 0.388" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.388 0.000 CLOCK_50 " " 0.388 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023247 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023247 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023248 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023250 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.900 " "Worst-case minimum pulse width slack is 8.900" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.900 0.000 CLOCK_50 " " 8.900 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023251 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023251 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815023260 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023294 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024133 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815024176 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024176 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024176 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.286 " "Worst-case setup slack is 15.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 15.286 0.000 CLOCK_50 " " 15.286 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024181 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024181 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.385 " "Worst-case hold slack is 0.385" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.385 0.000 CLOCK_50 " " 0.385 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024183 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024183 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024184 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024186 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.899 " "Worst-case minimum pulse width slack is 8.899" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.899 0.000 CLOCK_50 " " 8.899 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024188 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024188 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815024196 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024344 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025047 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815025091 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025091 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025091 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.068 " "Worst-case setup slack is 17.068" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 17.068 0.000 CLOCK_50 " " 17.068 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025094 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025094 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.204 " "Worst-case hold slack is 0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025095 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025095 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.204 0.000 CLOCK_50 " " 0.204 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025095 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025095 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025097 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025098 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.836 " "Worst-case minimum pulse width slack is 8.836" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025100 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025100 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.836 0.000 CLOCK_50 " " 8.836 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025100 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025100 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815025108 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815025253 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025253 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025253 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.237 " "Worst-case setup slack is 17.237" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025256 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025256 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 17.237 0.000 CLOCK_50 " " 17.237 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025256 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025256 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.194 " "Worst-case hold slack is 0.194" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025258 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025258 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.194 0.000 CLOCK_50 " " 0.194 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025258 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025258 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025259 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025261 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.806 " "Worst-case minimum pulse width slack is 8.806" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025262 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025262 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.806 0.000 CLOCK_50 " " 8.806 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025262 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025262 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815026650 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815026651 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1209 " "Peak virtual memory: 1209 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479815026692 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:46 2016 " "Processing ended: Tue Nov 22 11:43:46 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479815026692 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479815026692 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479815026692 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815026692 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481479717313 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481479717320 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 18:08:37 2016 " "Processing started: Sun Dec 11 18:08:37 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481479717320 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717320 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex6 -c ex6 " "Command: quartus_sta ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717320 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479717361 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717881 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717881 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717909 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717909 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718392 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481479718394 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718394 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718395 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718395 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479718396 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479718400 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.240 " "Worst-case setup slack is 15.240" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 15.240 0.000 CLOCK_50 " " 15.240 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718404 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718404 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.387 " "Worst-case hold slack is 0.387" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.387 0.000 CLOCK_50 " " 0.387 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718405 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718405 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718406 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718407 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.843 " "Worst-case minimum pulse width slack is 8.843" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.843 0.000 CLOCK_50 " " 8.843 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718407 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718407 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479718412 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718439 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719199 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481479719243 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719243 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719244 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.100 " "Worst-case setup slack is 15.100" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 15.100 0.000 CLOCK_50 " " 15.100 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719246 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.386 " "Worst-case hold slack is 0.386" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.386 0.000 CLOCK_50 " " 0.386 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719246 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719247 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719247 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.841 " "Worst-case minimum pulse width slack is 8.841" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.841 0.000 CLOCK_50 " " 8.841 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719248 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719248 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479719252 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719378 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720016 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481479720057 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720057 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720057 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.054 " "Worst-case setup slack is 17.054" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720058 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720058 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 17.054 0.000 CLOCK_50 " " 17.054 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720058 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720058 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.204 " "Worst-case hold slack is 0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720059 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720059 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.204 0.000 CLOCK_50 " " 0.204 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720059 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720059 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720059 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720060 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.791 " "Worst-case minimum pulse width slack is 8.791" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720060 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720060 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.791 0.000 CLOCK_50 " " 8.791 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720060 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720060 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479720064 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481479720192 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720192 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720192 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.214 " "Worst-case setup slack is 17.214" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 17.214 0.000 CLOCK_50 " " 17.214 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720194 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.194 " "Worst-case hold slack is 0.194" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.194 0.000 CLOCK_50 " " 0.194 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720194 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720195 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720195 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.764 " "Worst-case minimum pulse width slack is 8.764" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720196 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720196 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.764 0.000 CLOCK_50 " " 8.764 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720196 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720196 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479721486 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479721487 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1214 " "Peak virtual memory: 1214 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481479721513 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 18:08:41 2016 " "Processing ended: Sun Dec 11 18:08:41 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481479721513 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481479721513 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481479721513 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479721513 ""}
diff --git a/part_2/ex6/db/ex6.sta.rdb b/part_2/ex6/db/ex6.sta.rdb
index ee18610..3775235 100755
--- a/part_2/ex6/db/ex6.sta.rdb
+++ b/part_2/ex6/db/ex6.sta.rdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdb
index 8e7dea4..f96e901 100755
--- a/part_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdb
+++ b/part_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdb
Binary files differ
diff --git a/part_2/ex6/db/ex6.tis_db_list.ddb b/part_2/ex6/db/ex6.tis_db_list.ddb
index 88225e8..2df45d7 100755
--- a/part_2/ex6/db/ex6.tis_db_list.ddb
+++ b/part_2/ex6/db/ex6.tis_db_list.ddb
Binary files differ
diff --git a/part_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddb b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddb
index ff58cae..5a8d3c0 100755
--- a/part_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddb
+++ b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddb
Binary files differ
diff --git a/part_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddb b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddb
index c8bf679..845e816 100755
--- a/part_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddb
+++ b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddb
Binary files differ
diff --git a/part_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddb b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddb
index 6e31afe..e22b58a 100755
--- a/part_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddb
+++ b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddb
Binary files differ
diff --git a/part_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddb b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddb
index 9ed3347..2234005 100755
--- a/part_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddb
+++ b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddb
Binary files differ
diff --git a/part_2/ex6/db/ex6.tmw_info b/part_2/ex6/db/ex6.tmw_info
index 7f48734..3f7354a 100755
--- a/part_2/ex6/db/ex6.tmw_info
+++ b/part_2/ex6/db/ex6.tmw_info
@@ -1,6 +1,6 @@
-start_full_compilation:s
-start_analysis_synthesis:s-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s-start_full_compilation
-start_assembler:s-start_full_compilation
-start_timing_analyzer:s-start_full_compilation
+start_full_compilation:s:00:00:52
+start_analysis_synthesis:s:00:00:11-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:29-start_full_compilation
+start_assembler:s:00:00:07-start_full_compilation
+start_timing_analyzer:s:00:00:05-start_full_compilation
diff --git a/part_2/ex6/db/ex6.vpr.ammdb b/part_2/ex6/db/ex6.vpr.ammdb
index b265f17..bbc75a3 100755
--- a/part_2/ex6/db/ex6.vpr.ammdb
+++ b/part_2/ex6/db/ex6.vpr.ammdb
Binary files differ
diff --git a/part_2/ex6/db/ex6_partition_pins.json b/part_2/ex6/db/ex6_partition_pins.json
index 1a004e3..4227300 100755
--- a/part_2/ex6/db/ex6_partition_pins.json
+++ b/part_2/ex6/db/ex6_partition_pins.json
@@ -1,161 +1,161 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "HEX0[0]",
- "strict" : false
- },
- {
- "name" : "HEX0[1]",
- "strict" : false
- },
- {
- "name" : "HEX0[2]",
- "strict" : false
- },
- {
- "name" : "HEX0[3]",
- "strict" : false
- },
- {
- "name" : "HEX0[4]",
- "strict" : false
- },
- {
- "name" : "HEX0[5]",
- "strict" : false
- },
- {
- "name" : "HEX0[6]",
- "strict" : false
- },
- {
- "name" : "HEX1[0]",
- "strict" : false
- },
- {
- "name" : "HEX1[1]",
- "strict" : false
- },
- {
- "name" : "HEX1[2]",
- "strict" : false
- },
- {
- "name" : "HEX1[3]",
- "strict" : false
- },
- {
- "name" : "HEX1[4]",
- "strict" : false
- },
- {
- "name" : "HEX1[5]",
- "strict" : false
- },
- {
- "name" : "HEX1[6]",
- "strict" : false
- },
- {
- "name" : "HEX2[0]",
- "strict" : false
- },
- {
- "name" : "HEX2[1]",
- "strict" : false
- },
- {
- "name" : "HEX2[2]",
- "strict" : false
- },
- {
- "name" : "HEX2[3]",
- "strict" : false
- },
- {
- "name" : "HEX2[4]",
- "strict" : false
- },
- {
- "name" : "HEX2[5]",
- "strict" : false
- },
- {
- "name" : "HEX2[6]",
- "strict" : false
- },
- {
- "name" : "HEX3[0]",
- "strict" : false
- },
- {
- "name" : "HEX3[1]",
- "strict" : false
- },
- {
- "name" : "HEX3[2]",
- "strict" : false
- },
- {
- "name" : "HEX3[3]",
- "strict" : false
- },
- {
- "name" : "HEX3[4]",
- "strict" : false
- },
- {
- "name" : "HEX3[5]",
- "strict" : false
- },
- {
- "name" : "HEX3[6]",
- "strict" : false
- },
- {
- "name" : "HEX4[0]",
- "strict" : false
- },
- {
- "name" : "HEX4[1]",
- "strict" : false
- },
- {
- "name" : "HEX4[2]",
- "strict" : false
- },
- {
- "name" : "HEX4[3]",
- "strict" : false
- },
- {
- "name" : "HEX4[4]",
- "strict" : false
- },
- {
- "name" : "HEX4[5]",
- "strict" : false
- },
- {
- "name" : "HEX4[6]",
- "strict" : false
- },
- {
- "name" : "KEY[1]",
- "strict" : false
- },
- {
- "name" : "KEY[0]",
- "strict" : false
- },
- {
- "name" : "CLOCK_50",
- "strict" : false
- }
- ]
- }
- ]
+{
+ "partitions" : [
+ {
+ "name" : "Top",
+ "pins" : [
+ {
+ "name" : "HEX0[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[6]",
+ "strict" : false
+ },
+ {
+ "name" : "KEY[1]",
+ "strict" : false
+ },
+ {
+ "name" : "KEY[0]",
+ "strict" : false
+ },
+ {
+ "name" : "CLOCK_50",
+ "strict" : false
+ }
+ ]
+ }
+ ]
} \ No newline at end of file
diff --git a/part_2/ex6/db/prev_cmp_ex6.qmsg b/part_2/ex6/db/prev_cmp_ex6.qmsg
index 3ef48ff..9ed0041 100755
--- a/part_2/ex6/db/prev_cmp_ex6.qmsg
+++ b/part_2/ex6/db/prev_cmp_ex6.qmsg
@@ -1,160 +1,160 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479814855590 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814855591 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:40:55 2016 " "Processing started: Tue Nov 22 11:40:55 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814855591 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814855591 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814855592 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479814856068 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479814856068 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex6/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864502 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864505 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864505 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex6/verilog_files/add3_ge5.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864506 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864506 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" { } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex6/verilog_files/counter_16.v" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864507 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864507 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex6.v 1 1 " "Found 1 design units, including 1 entities, in source file ex6.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex6 " "Found entity 1: ex6" { } { { "ex6.v" "" { Text "C:/New folder/ex6/ex6.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864509 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864509 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" { } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex6/verilog_files/tick_50000.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864512 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864512 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex6 " "Elaborating entity \"ex6\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479814864538 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:tck " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:tck\"" { } { { "ex6.v" "tck" { Text "C:/New folder/ex6/ex6.v" 11 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864541 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:C " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:C\"" { } { { "ex6.v" "C" { Text "C:/New folder/ex6/ex6.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864547 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:B " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:B\"" { } { { "ex6.v" "B" { Text "C:/New folder/ex6/ex6.v" 15 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864547 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:B\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:B\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864548 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "ex6.v" "SEG0" { Text "C:/New folder/ex6/ex6.v" 17 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864552 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479814865202 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.map.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814865495 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479814865576 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814865576 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "225 " "Implemented 225 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479814865610 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479814865610 ""} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Implemented 187 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479814865610 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479814865610 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "899 " "Peak virtual memory: 899 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814865623 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:05 2016 " "Processing ended: Tue Nov 22 11:41:05 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814865623 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814865623 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814865623 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814865623 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1479814867084 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814867085 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:41:06 2016 " "Processing started: Tue Nov 22 11:41:06 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814867085 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1479814867085 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1479814867085 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1479814867201 ""}
-{ "Info" "0" "" "Project = ex6" { } { } 0 0 "Project = ex6" 0 0 "Fitter" 0 0 1479814867202 ""}
-{ "Info" "0" "" "Revision = ex6" { } { } 0 0 "Revision = ex6" 0 0 "Fitter" 0 0 1479814867202 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479814867313 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479814867314 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex6 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex6\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479814867575 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814867638 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814867638 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479814868022 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479814868156 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479814878204 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1479814878285 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1479814878285 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814878285 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479814878288 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814878288 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814878288 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479814878289 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479814878289 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479814878289 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479814878289 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479814878290 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479814878290 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479814878324 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814878326 ""}
-{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1479814883778 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814883780 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1479814883780 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479814883781 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1479814883781 ""}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1479814883782 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479814883782 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479814883782 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479814883782 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1479814883782 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479814883786 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479814883871 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814884487 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479814885162 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479814885489 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814885489 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479814886599 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" { } { { "loc" "" { Generic "C:/New folder/ex6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479814891026 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479814891026 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479814891312 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479814891312 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479814891312 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814891315 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479814892475 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479814892512 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479814892890 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479814892891 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479814893257 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814895619 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479814895860 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.fit.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479814895916 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 48 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 48 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2589 " "Peak virtual memory: 2589 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814896340 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:36 2016 " "Processing ended: Tue Nov 22 11:41:36 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814896340 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814896340 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:53 " "Total CPU time (on all processors): 00:00:53" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814896340 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479814896340 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1479814897635 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814897638 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:41:37 2016 " "Processing started: Tue Nov 22 11:41:37 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814897638 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479814897638 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479814897638 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479814898389 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479814902980 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "893 " "Peak virtual memory: 893 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814903314 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:43 2016 " "Processing ended: Tue Nov 22 11:41:43 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814903314 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814903314 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814903314 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479814903314 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1479814903979 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1479814904803 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814904804 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:41:44 2016 " "Processing started: Tue Nov 22 11:41:44 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814904804 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814904804 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex6 -c ex6 " "Command: quartus_sta ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814904804 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814904930 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905472 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905472 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905519 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905519 ""}
-{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906037 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814906040 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906040 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906041 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906041 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906042 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906049 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.377 " "Worst-case setup slack is 15.377" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 15.377 0.000 CLOCK_50 " " 15.377 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906055 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906055 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.388 " "Worst-case hold slack is 0.388" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906057 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906057 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.388 0.000 CLOCK_50 " " 0.388 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906057 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906057 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906058 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906060 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.900 " "Worst-case minimum pulse width slack is 8.900" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.900 0.000 CLOCK_50 " " 8.900 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906061 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906061 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906070 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906104 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906927 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814906969 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906969 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906969 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.286 " "Worst-case setup slack is 15.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906974 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906974 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 15.286 0.000 CLOCK_50 " " 15.286 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906974 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906974 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.385 " "Worst-case hold slack is 0.385" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.385 0.000 CLOCK_50 " " 0.385 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906976 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906976 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906977 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906979 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.899 " "Worst-case minimum pulse width slack is 8.899" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.899 0.000 CLOCK_50 " " 8.899 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906980 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906980 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906989 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907132 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907832 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814907877 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907877 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907877 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.068 " "Worst-case setup slack is 17.068" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907880 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907880 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 17.068 0.000 CLOCK_50 " " 17.068 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907880 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907880 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.204 " "Worst-case hold slack is 0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.204 0.000 CLOCK_50 " " 0.204 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907883 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907883 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907885 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907887 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.836 " "Worst-case minimum pulse width slack is 8.836" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.836 0.000 CLOCK_50 " " 8.836 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907888 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907888 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814907897 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814908038 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908038 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908039 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.237 " "Worst-case setup slack is 17.237" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908041 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908041 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 17.237 0.000 CLOCK_50 " " 17.237 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908041 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908041 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.194 " "Worst-case hold slack is 0.194" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.194 0.000 CLOCK_50 " " 0.194 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908043 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908043 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908045 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908046 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.806 " "Worst-case minimum pulse width slack is 8.806" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.806 0.000 CLOCK_50 " " 8.806 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908048 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908048 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814909430 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814909431 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1207 " "Peak virtual memory: 1207 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814909471 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:49 2016 " "Processing ended: Tue Nov 22 11:41:49 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814909471 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814909471 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814909471 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814909471 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 55 s " "Quartus Prime Full Compilation was successful. 0 errors, 55 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814910195 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481478912139 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481478912154 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 17:55:11 2016 " "Processing started: Sun Dec 11 17:55:11 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481478912154 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478912154 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478912154 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481478912723 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481478912723 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921441 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921441 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921444 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/add3_ge5.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921445 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921445 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" { } { { "verilog_files/counter_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/counter_16.v" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921446 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921446 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex6.v 1 1 " "Found 1 design units, including 1 entities, in source file ex6.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex6 " "Found entity 1: ex6" { } { { "ex6.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921447 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921447 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" { } { { "verilog_files/tick_50000.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/tick_50000.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921447 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921447 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex6 " "Elaborating entity \"ex6\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481478921538 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:tck " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:tck\"" { } { { "ex6.v" "tck" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 11 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478921631 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:C " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:C\"" { } { { "ex6.v" "C" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478921639 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:B " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:B\"" { } { { "ex6.v" "B" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 15 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478921644 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:B\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:B\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_16.v" "A1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478921655 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "ex6.v" "SEG0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 17 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478921668 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481478922578 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481478923202 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478923202 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "225 " "Implemented 225 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481478923789 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481478923789 ""} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Implemented 187 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481478923789 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481478923789 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1052 " "Peak virtual memory: 1052 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481478923801 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 17:55:23 2016 " "Processing ended: Sun Dec 11 17:55:23 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481478923801 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481478923801 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481478923801 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478923801 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1481478925691 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481478925699 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 17:55:24 2016 " "Processing started: Sun Dec 11 17:55:24 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481478925699 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1481478925699 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1481478925699 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1481478926149 ""}
+{ "Info" "0" "" "Project = ex6" { } { } 0 0 "Project = ex6" 0 0 "Fitter" 0 0 1481478926156 ""}
+{ "Info" "0" "" "Revision = ex6" { } { } 0 0 "Revision = ex6" 0 0 "Fitter" 0 0 1481478926156 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481478926329 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481478926329 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex6 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex6\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481478926347 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481478926466 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481478926466 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481478927033 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1481478927140 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481478927728 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481478938933 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481478939030 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481478939030 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478939030 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481478939053 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481478939053 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481478939054 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481478939054 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481478939054 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481478939054 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481478939054 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481478939055 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481478939055 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481478939237 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478939239 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1481478945297 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481478945312 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1481478945312 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481478945323 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481478945323 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1481478945324 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481478945325 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481478945325 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481478945325 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1481478945325 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481478945341 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481478945481 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478946550 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481478947153 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481478947480 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478947480 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481478948735 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y11 X89_Y22 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22" { } { { "loc" "" { Generic "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22"} { { 12 { 0 ""} 78 11 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481478953134 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481478953134 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481478953372 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1481478953372 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481478953372 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478953374 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.11 " "Total time spent on timing analysis during the Fitter is 0.11 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481478955241 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481478955281 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481478955855 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481478955855 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481478956206 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478958150 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481478958279 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481478958364 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 49 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 49 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2136 " "Peak virtual memory: 2136 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481478958789 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 17:55:58 2016 " "Processing ended: Sun Dec 11 17:55:58 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481478958789 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481478958789 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:50 " "Total CPU time (on all processors): 00:00:50" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481478958789 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481478958789 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1481478960949 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481478960966 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 17:56:00 2016 " "Processing started: Sun Dec 11 17:56:00 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481478960966 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481478960966 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481478960967 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481478961599 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481478967716 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "977 " "Peak virtual memory: 977 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481478968247 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 17:56:08 2016 " "Processing ended: Sun Dec 11 17:56:08 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481478968247 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481478968247 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481478968247 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481478968247 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1481478968422 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1481478969236 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481478969243 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 17:56:08 2016 " "Processing started: Sun Dec 11 17:56:08 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481478969243 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969243 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex6 -c ex6 " "Command: quartus_sta ex6 -c ex6" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969244 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478969319 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969844 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969844 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969888 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969888 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970377 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481478970380 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970380 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970381 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970381 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478970381 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478970386 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.240 " "Worst-case setup slack is 15.240" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970396 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970396 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 15.240 0.000 CLOCK_50 " " 15.240 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970396 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970396 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.387 " "Worst-case hold slack is 0.387" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.387 0.000 CLOCK_50 " " 0.387 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970397 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970397 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970398 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970398 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.843 " "Worst-case minimum pulse width slack is 8.843" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970399 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970399 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.843 0.000 CLOCK_50 " " 8.843 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970399 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970399 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478970424 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970479 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971484 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481478971528 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971528 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971529 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.100 " "Worst-case setup slack is 15.100" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 15.100 0.000 CLOCK_50 " " 15.100 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971531 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.386 " "Worst-case hold slack is 0.386" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.386 0.000 CLOCK_50 " " 0.386 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971531 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971532 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971532 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.841 " "Worst-case minimum pulse width slack is 8.841" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.841 0.000 CLOCK_50 " " 8.841 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971533 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971533 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478971537 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971687 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972489 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481478972532 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972532 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972532 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.054 " "Worst-case setup slack is 17.054" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 17.054 0.000 CLOCK_50 " " 17.054 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972533 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972533 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.204 " "Worst-case hold slack is 0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.204 0.000 CLOCK_50 " " 0.204 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972534 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972534 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972535 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972535 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.791 " "Worst-case minimum pulse width slack is 8.791" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972536 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972536 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.791 0.000 CLOCK_50 " " 8.791 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972536 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972536 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478972540 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481478972668 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972668 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972669 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.214 " "Worst-case setup slack is 17.214" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 17.214 0.000 CLOCK_50 " " 17.214 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972670 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972670 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.194 " "Worst-case hold slack is 0.194" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972671 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972671 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.194 0.000 CLOCK_50 " " 0.194 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972671 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972671 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972671 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972672 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.764 " "Worst-case minimum pulse width slack is 8.764" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.764 0.000 CLOCK_50 " " 8.764 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972673 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478973979 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478973981 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1222 " "Peak virtual memory: 1222 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481478974007 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 17:56:14 2016 " "Processing ended: Sun Dec 11 17:56:14 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481478974007 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481478974007 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481478974007 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478974007 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 56 s " "Quartus Prime Full Compilation was successful. 0 errors, 56 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478974202 ""}
diff --git a/part_2/ex6/ex6.qsf b/part_2/ex6/ex6.qsf
index 1352d53..7d53d75 100755
--- a/part_2/ex6/ex6.qsf
+++ b/part_2/ex6/ex6.qsf
@@ -252,7 +252,7 @@ set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY ex6
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:55:22 NOVEMBER 22, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
diff --git a/part_2/ex6/ex6.qws b/part_2/ex6/ex6.qws
deleted file mode 100755
index 63563b7..0000000
--- a/part_2/ex6/ex6.qws
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/ex6_assignment_defaults.qdf b/part_2/ex6/ex6_assignment_defaults.qdf
new file mode 100644
index 0000000..71af25e
--- /dev/null
+++ b/part_2/ex6/ex6_assignment_defaults.qdf
@@ -0,0 +1,795 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2016 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Intel and sold by Intel or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+# Date created = 17:54:40 December 11, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+# automatically by the Quartus Prime software and is used
+# to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL -value OFF
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.db_info b/part_2/ex6/incremental_db/compiled_partitions/ex6.db_info
index 41f92fa..4f976f6 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.db_info
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Version_Index = 402707200
-Creation_Time = Tue Nov 22 10:11:38 2016
+Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Version_Index = 419480576
+Creation_Time = Sun Dec 11 17:54:40 2016
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdb
index ab3bea2..b5923ef 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdb
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdb
index dae0e0b..7ee96a8 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdb
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdb
index 21a86b2..996a72c 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdb
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdb
index 8907c68..48ea6fd 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdb
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdb
index 26f78b7..a0b4222 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdb
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb
index d45424f..626799f 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdb
index cd9fac3..4f6e44b 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdb
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdb
index 3b77930..97b904d 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdb
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpi b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpi
index 10da539..d6def8f 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpi
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpi
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdb
index 5b4ee25..ac84755 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdb
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdb
index 0cd555d..f4f72fa 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdb
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdb
index 9c8db47..96c2f5b 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdb
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kpt b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kpt
index 722be46..9d8eb24 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kpt
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kpt
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olf.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olf.cdb
deleted file mode 100755
index 1f45a5a..0000000
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olf.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olm.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olm.cdb
deleted file mode 100755
index 6e951b6..0000000
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olm.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.oln.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.oln.cdb
deleted file mode 100755
index c78c5d1..0000000
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.oln.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.opi b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.opi
deleted file mode 100755
index 56a6051..0000000
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.opi
+++ /dev/null
@@ -1 +0,0 @@
-1 \ No newline at end of file
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orf.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orf.cdb
deleted file mode 100755
index 1f45a5a..0000000
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orf.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orm.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orm.cdb
deleted file mode 100755
index d995b24..0000000
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orm.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orn.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orn.cdb
deleted file mode 100755
index 450e420..0000000
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orn.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.cdb
deleted file mode 100755
index 3b77930..0000000
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.cdb
deleted file mode 100755
index 5b4ee25..0000000
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.hdb
deleted file mode 100755
index 0cd555d..0000000
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.hdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hdb
deleted file mode 100755
index 9c8db47..0000000
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdb
index 88368d0..add48cc 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdb
Binary files differ
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdb
index 971696d..7f54a15 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdb
Binary files differ
diff --git a/part_2/ex6/output_files/ex6.asm.rpt b/part_2/ex6/output_files/ex6.asm.rpt
index c99b821..303516d 100755
--- a/part_2/ex6/output_files/ex6.asm.rpt
+++ b/part_2/ex6/output_files/ex6.asm.rpt
@@ -1,92 +1,92 @@
-Assembler report for ex6
-Tue Nov 22 11:43:40 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: C:/New folder/ex6/output_files/ex6.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Tue Nov 22 11:43:40 2016 ;
-; Revision Name ; ex6 ;
-; Top-level Entity Name ; ex6 ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+----------------------------------------+
-; Assembler Generated Files ;
-+----------------------------------------+
-; File Name ;
-+----------------------------------------+
-; C:/New folder/ex6/output_files/ex6.sof ;
-+----------------------------------------+
-
-
-+------------------------------------------------------------------+
-; Assembler Device Options: C:/New folder/ex6/output_files/ex6.sof ;
-+----------------+-------------------------------------------------+
-; Option ; Setting ;
-+----------------+-------------------------------------------------+
-; Device ; 5CSEMA5F31C6 ;
-; JTAG usercode ; 0x00B27652 ;
-; Checksum ; 0x00B27652 ;
-+----------------+-------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
- Info: Processing started: Tue Nov 22 11:43:34 2016
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 893 megabytes
- Info: Processing ended: Tue Nov 22 11:43:40 2016
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:06
-
-
+Assembler report for ex6
+Sun Dec 11 18:08:36 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: ex6.sof
+ 6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Sun Dec 11 18:08:36 2016 ;
+; Revision Name ; ex6 ;
+; Top-level Entity Name ; ex6 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++---------------------------+
+; Assembler Generated Files ;
++---------------------------+
+; File Name ;
++---------------------------+
+; ex6.sof ;
++---------------------------+
+
+
++-----------------------------------+
+; Assembler Device Options: ex6.sof ;
++----------------+------------------+
+; Option ; Setting ;
++----------------+------------------+
+; Device ; 5CSEMA5F31C6 ;
+; JTAG usercode ; 0x00B261DF ;
+; Checksum ; 0x00B261DF ;
++----------------+------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+ Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+ Info: Processing started: Sun Dec 11 18:08:30 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 976 megabytes
+ Info: Processing ended: Sun Dec 11 18:08:36 2016
+ Info: Elapsed time: 00:00:06
+ Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_2/ex6/output_files/ex6.done b/part_2/ex6/output_files/ex6.done
index 33dea98..5572926 100755
--- a/part_2/ex6/output_files/ex6.done
+++ b/part_2/ex6/output_files/ex6.done
@@ -1 +1 @@
-Tue Nov 22 11:43:47 2016
+Sun Dec 11 18:08:41 2016
diff --git a/part_2/ex6/output_files/ex6.fit.rpt b/part_2/ex6/output_files/ex6.fit.rpt
index b0a72b2..dc8ac28 100755
--- a/part_2/ex6/output_files/ex6.fit.rpt
+++ b/part_2/ex6/output_files/ex6.fit.rpt
@@ -1,2034 +1,2034 @@
-Fitter report for ex6
-Tue Nov 22 11:43:32 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. I/O Assignment Warnings
- 6. Fitter Netlist Optimizations
- 7. Ignored Assignments
- 8. Incremental Compilation Preservation Summary
- 9. Incremental Compilation Partition Settings
- 10. Incremental Compilation Placement Preservation
- 11. Pin-Out File
- 12. Fitter Resource Usage Summary
- 13. Fitter Partition Statistics
- 14. Input Pins
- 15. Output Pins
- 16. I/O Bank Usage
- 17. All Package Pins
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Global & Other Fast Signals
- 23. Routing Usage Summary
- 24. I/O Rules Summary
- 25. I/O Rules Details
- 26. I/O Rules Matrix
- 27. Fitter Device Options
- 28. Operating Settings and Conditions
- 29. Estimated Delay Added for Hold Timing Summary
- 30. Estimated Delay Added for Hold Timing Details
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+---------------------------------+-------------------------------------------------+
-; Fitter Status ; Successful - Tue Nov 22 11:43:32 2016 ;
-; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name ; ex6 ;
-; Top-level Entity Name ; ex6 ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Logic utilization (in ALMs) ; 99 / 32,070 ( < 1 % ) ;
-; Total registers ; 35 ;
-; Total pins ; 38 / 457 ( 8 % ) ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
-; Total RAM Blocks ; 0 / 397 ( 0 % ) ;
-; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 / 6 ( 0 % ) ;
-; Total DLLs ; 0 / 4 ( 0 % ) ;
-+---------------------------------+-------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; 5CSEMA5F31C6 ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Auto RAM to MLAB Conversion ; On ; On ;
-; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
-; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
-; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Clamping Diode ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-; Advanced Physical Optimization ; On ; On ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.5% ;
-; Processor 3 ; 0.5% ;
-; Processor 4 ; 0.4% ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+--------------------------------------+
-; Pin Name ; Reason ;
-+----------+--------------------------------------+
-; HEX0[0] ; Missing drive strength and slew rate ;
-; HEX0[1] ; Missing drive strength and slew rate ;
-; HEX0[2] ; Missing drive strength and slew rate ;
-; HEX0[3] ; Missing drive strength and slew rate ;
-; HEX0[4] ; Missing drive strength and slew rate ;
-; HEX0[5] ; Missing drive strength and slew rate ;
-; HEX0[6] ; Missing drive strength and slew rate ;
-; HEX1[0] ; Missing drive strength and slew rate ;
-; HEX1[1] ; Missing drive strength and slew rate ;
-; HEX1[2] ; Missing drive strength and slew rate ;
-; HEX1[3] ; Missing drive strength and slew rate ;
-; HEX1[4] ; Missing drive strength and slew rate ;
-; HEX1[5] ; Missing drive strength and slew rate ;
-; HEX1[6] ; Missing drive strength and slew rate ;
-; HEX2[0] ; Missing drive strength and slew rate ;
-; HEX2[1] ; Missing drive strength and slew rate ;
-; HEX2[2] ; Missing drive strength and slew rate ;
-; HEX2[3] ; Missing drive strength and slew rate ;
-; HEX2[4] ; Missing drive strength and slew rate ;
-; HEX2[5] ; Missing drive strength and slew rate ;
-; HEX2[6] ; Missing drive strength and slew rate ;
-; HEX3[0] ; Missing drive strength and slew rate ;
-; HEX3[1] ; Missing drive strength and slew rate ;
-; HEX3[2] ; Missing drive strength and slew rate ;
-; HEX3[3] ; Missing drive strength and slew rate ;
-; HEX3[4] ; Missing drive strength and slew rate ;
-; HEX3[5] ; Missing drive strength and slew rate ;
-; HEX3[6] ; Missing drive strength and slew rate ;
-; HEX4[0] ; Missing drive strength and slew rate ;
-; HEX4[1] ; Missing drive strength and slew rate ;
-; HEX4[2] ; Missing drive strength and slew rate ;
-; HEX4[3] ; Missing drive strength and slew rate ;
-; HEX4[4] ; Missing drive strength and slew rate ;
-; HEX4[5] ; Missing drive strength and slew rate ;
-; HEX4[6] ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Netlist Optimizations ;
-+-------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------+------------------+-----------------------+
-; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
-+-------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------+------------------+-----------------------+
-; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
-; tick_50000:tck|count[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:tck|count[1]~DUPLICATE ; ; ;
-; tick_50000:tck|count[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:tck|count[5]~DUPLICATE ; ; ;
-+-------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------+------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Location ; ; ; ADC_CS ; PIN_AG20 ; QSF Assignment ;
-; Location ; ; ; ADC_SCK ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; ADC_SDI ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; ADC_SDO ; PIN_AJ21 ; QSF Assignment ;
-; Location ; ; ; DAC_CS ; PIN_AD20 ; QSF Assignment ;
-; Location ; ; ; DAC_LD ; PIN_AK21 ; QSF Assignment ;
-; Location ; ; ; DAC_SCK ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; DAC_SDI ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AA28 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; KEY[2] ; PIN_W15 ; QSF Assignment ;
-; Location ; ; ; KEY[3] ; PIN_Y16 ; QSF Assignment ;
-; Location ; ; ; LEDR[0] ; PIN_V16 ; QSF Assignment ;
-; Location ; ; ; LEDR[1] ; PIN_W16 ; QSF Assignment ;
-; Location ; ; ; LEDR[2] ; PIN_V17 ; QSF Assignment ;
-; Location ; ; ; LEDR[3] ; PIN_V18 ; QSF Assignment ;
-; Location ; ; ; LEDR[4] ; PIN_W17 ; QSF Assignment ;
-; Location ; ; ; LEDR[5] ; PIN_W19 ; QSF Assignment ;
-; Location ; ; ; LEDR[6] ; PIN_Y19 ; QSF Assignment ;
-; Location ; ; ; LEDR[7] ; PIN_W20 ; QSF Assignment ;
-; Location ; ; ; LEDR[8] ; PIN_W21 ; QSF Assignment ;
-; Location ; ; ; LEDR[9] ; PIN_Y21 ; QSF Assignment ;
-; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ;
-; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ;
-; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ;
-; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ;
-; Location ; ; ; PWM_OUT ; PIN_AJ20 ; QSF Assignment ;
-; Location ; ; ; SW[0] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; SW[1] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; SW[2] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; SW[3] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AC9 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AE12 ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; ADC_CS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; ADC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; ADC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; ADC_SDO ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; DAC_CS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; DAC_LD ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; DAC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; DAC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; KEY[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; KEY[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; LEDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; LEDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; LEDR[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; LEDR[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; LEDR[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; LEDR[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; LEDR[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; LEDR[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; LEDR[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; LEDR[9] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; PWM_OUT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; SW[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; SW[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; SW[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; SW[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; SW[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; SW[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; SW[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; SW[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; SW[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex6 ; ; SW[9] ; 3.3-V LVTTL ; QSF Assignment ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 ) ;
-; -- Achieved ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 298 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in C:/New folder/ex6/output_files/ex6.pin.
-
-
-+------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+-------------------------------------------------------------+--------------------+-------+
-; Resource ; Usage ; % ;
-+-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 99 / 32,070 ; < 1 % ;
-; ALMs needed [=A-B+C] ; 99 ; ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 100 / 32,070 ; < 1 % ;
-; [a] ALMs used for LUT logic and registers ; 16 ; ;
-; [b] ALMs used for LUT logic ; 83 ; ;
-; [c] ALMs used for registers ; 1 ; ;
-; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
-; [B] Estimate of ALMs recoverable by dense packing ; 1 / 32,070 ; < 1 % ;
-; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ;
-; [a] Due to location constrained logic ; 0 ; ;
-; [b] Due to LAB-wide signal conflicts ; 0 ; ;
-; [c] Due to LAB input limits ; 0 ; ;
-; [d] Due to virtual I/Os ; 0 ; ;
-; ; ; ;
-; Difficulty packing design ; Low ; ;
-; ; ; ;
-; Total LABs: partially or completely used ; 17 / 3,207 ; < 1 % ;
-; -- Logic LABs ; 17 ; ;
-; -- Memory LABs (up to half of total LABs) ; 0 ; ;
-; ; ; ;
-; Combinational ALUT usage for logic ; 188 ; ;
-; -- 7 input functions ; 0 ; ;
-; -- 6 input functions ; 9 ; ;
-; -- 5 input functions ; 3 ; ;
-; -- 4 input functions ; 124 ; ;
-; -- <=3 input functions ; 52 ; ;
-; Combinational ALUT usage for route-throughs ; 1 ; ;
-; Dedicated logic registers ; 35 ; ;
-; -- By type: ; ; ;
-; -- Primary logic registers ; 33 / 64,140 ; < 1 % ;
-; -- Secondary logic registers ; 2 / 64,140 ; < 1 % ;
-; -- By function: ; ; ;
-; -- Design implementation registers ; 33 ; ;
-; -- Routing optimization registers ; 2 ; ;
-; ; ; ;
-; Virtual pins ; 0 ; ;
-; I/O pins ; 38 / 457 ; 8 % ;
-; -- Clock pins ; 1 / 8 ; 13 % ;
-; -- Dedicated input pins ; 0 / 21 ; 0 % ;
-; ; ; ;
-; Hard processor system peripheral utilization ; ; ;
-; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
-; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
-; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
-; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
-; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
-; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
-; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
-; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
-; -- JTAG ; 0 / 1 ( 0 % ) ; ;
-; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
-; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
-; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
-; -- STM event ; 0 / 1 ( 0 % ) ; ;
-; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
-; -- DMA ; 0 / 1 ( 0 % ) ; ;
-; -- CAN ; 0 / 2 ( 0 % ) ; ;
-; -- EMAC ; 0 / 2 ( 0 % ) ; ;
-; -- I2C ; 0 / 4 ( 0 % ) ; ;
-; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
-; -- QSPI ; 0 / 1 ( 0 % ) ; ;
-; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
-; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
-; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
-; -- UART ; 0 / 2 ( 0 % ) ; ;
-; -- USB ; 0 / 2 ( 0 % ) ; ;
-; ; ; ;
-; Global signals ; 1 ; ;
-; M10K blocks ; 0 / 397 ; 0 % ;
-; Total MLAB memory bits ; 0 ; ;
-; Total block memory bits ; 0 / 4,065,280 ; 0 % ;
-; Total block memory implementation bits ; 0 / 4,065,280 ; 0 % ;
-; ; ; ;
-; Total DSP Blocks ; 0 / 87 ; 0 % ;
-; ; ; ;
-; Fractional PLLs ; 0 / 6 ; 0 % ;
-; Global clocks ; 1 / 16 ; 6 % ;
-; Quadrant clocks ; 0 / 66 ; 0 % ;
-; Horizontal periphery clocks ; 0 / 18 ; 0 % ;
-; SERDES Transmitters ; 0 / 100 ; 0 % ;
-; SERDES Receivers ; 0 / 100 ; 0 % ;
-; JTAGs ; 0 / 1 ; 0 % ;
-; ASMI blocks ; 0 / 1 ; 0 % ;
-; CRC blocks ; 0 / 1 ; 0 % ;
-; Remote update blocks ; 0 / 1 ; 0 % ;
-; Oscillator blocks ; 0 / 1 ; 0 % ;
-; Impedance control blocks ; 0 / 4 ; 0 % ;
-; Hard Memory Controllers ; 0 / 2 ; 0 % ;
-; Average interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; ;
-; Peak interconnect usage (total/H/V) ; 0.9% / 0.9% / 1.0% ; ;
-; Maximum fan-out ; 18 ; ;
-; Highest non-global fan-out ; 17 ; ;
-; Total fan-out ; 852 ; ;
-; Average fan-out ; 2.83 ; ;
-+-------------------------------------------------------------+--------------------+-------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 99 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; ALMs needed [=A-B+C] ; 99 ; 0 ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 100 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; [a] ALMs used for LUT logic and registers ; 16 ; 0 ;
-; [b] ALMs used for LUT logic ; 83 ; 0 ;
-; [c] ALMs used for registers ; 1 ; 0 ;
-; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
-; [B] Estimate of ALMs recoverable by dense packing ; 1 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
-; [a] Due to location constrained logic ; 0 ; 0 ;
-; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
-; [c] Due to LAB input limits ; 0 ; 0 ;
-; [d] Due to virtual I/Os ; 0 ; 0 ;
-; ; ; ;
-; Difficulty packing design ; Low ; Low ;
-; ; ; ;
-; Total LABs: partially or completely used ; 17 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ;
-; -- Logic LABs ; 17 ; 0 ;
-; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
-; ; ; ;
-; Combinational ALUT usage for logic ; 188 ; 0 ;
-; -- 7 input functions ; 0 ; 0 ;
-; -- 6 input functions ; 9 ; 0 ;
-; -- 5 input functions ; 3 ; 0 ;
-; -- 4 input functions ; 124 ; 0 ;
-; -- <=3 input functions ; 52 ; 0 ;
-; Combinational ALUT usage for route-throughs ; 1 ; 0 ;
-; Memory ALUT usage ; 0 ; 0 ;
-; -- 64-address deep ; 0 ; 0 ;
-; -- 32-address deep ; 0 ; 0 ;
-; ; ; ;
-; Dedicated logic registers ; 0 ; 0 ;
-; -- By type: ; ; ;
-; -- Primary logic registers ; 33 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
-; -- Secondary logic registers ; 2 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
-; -- By function: ; ; ;
-; -- Design implementation registers ; 33 ; 0 ;
-; -- Routing optimization registers ; 2 ; 0 ;
-; ; ; ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 38 ; 0 ;
-; I/O registers ; 0 ; 0 ;
-; Total block memory bits ; 0 ; 0 ;
-; Total block memory implementation bits ; 0 ; 0 ;
-; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 852 ; 0 ;
-; -- Registered Connections ; 139 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 3 ; 0 ;
-; -- Output Ports ; 35 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; AF14 ; 3B ; 32 ; 0 ; 0 ; 19 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-; KEY[0] ; AA14 ; 3B ; 36 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-; KEY[1] ; AA15 ; 3B ; 36 ; 0 ; 17 ; 17 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[0] ; AJ29 ; 5A ; 89 ; 6 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[1] ; AH29 ; 5A ; 89 ; 6 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[2] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[3] ; AG30 ; 5A ; 89 ; 16 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[4] ; AF29 ; 5A ; 89 ; 15 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[5] ; AF30 ; 5A ; 89 ; 15 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[6] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[0] ; AB23 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[1] ; AE29 ; 5B ; 89 ; 23 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[2] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[3] ; AC28 ; 5B ; 89 ; 20 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[4] ; AD30 ; 5B ; 89 ; 25 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[5] ; AC29 ; 5B ; 89 ; 20 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[6] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[0] ; AD26 ; 5A ; 89 ; 16 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[1] ; AC27 ; 5A ; 89 ; 16 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[2] ; AD25 ; 5A ; 89 ; 4 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[3] ; AC25 ; 5A ; 89 ; 4 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[4] ; AB28 ; 5B ; 89 ; 21 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[5] ; AB25 ; 5A ; 89 ; 11 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[6] ; AB22 ; 5A ; 89 ; 9 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[0] ; AA24 ; 5A ; 89 ; 11 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[1] ; Y23 ; 5A ; 89 ; 13 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[2] ; Y24 ; 5A ; 89 ; 13 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[3] ; W22 ; 5A ; 89 ; 8 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[4] ; W24 ; 5A ; 89 ; 15 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[5] ; V23 ; 5A ; 89 ; 15 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[6] ; W25 ; 5B ; 89 ; 20 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+----------------------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+---------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
-+----------+------------------+---------------+--------------+---------------+
-; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
-; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
-; 3A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 3B ; 3 / 48 ( 6 % ) ; 3.3V ; -- ; 3.3V ;
-; 4A ; 0 / 80 ( 0 % ) ; 3.3V ; -- ; 3.3V ;
-; 5A ; 27 / 32 ( 84 % ) ; 3.3V ; -- ; 3.3V ;
-; 5B ; 8 / 16 ( 50 % ) ; 3.3V ; -- ; 3.3V ;
-; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-+----------+------------------+---------------+--------------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
-; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
-; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 122 ; 3B ; KEY[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AA15 ; 120 ; 3B ; KEY[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; AA24 ; 228 ; 5A ; HEX4[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB12 ; 72 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB14 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 225 ; 5A ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AB23 ; 227 ; 5A ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB25 ; 230 ; 5A ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 249 ; 5B ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC11 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC12 ; 82 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC21 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AC25 ; 215 ; 5A ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC27 ; 242 ; 5A ; HEX3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 245 ; 5B ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AC29 ; 247 ; 5B ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AC30 ; 259 ; 5B ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD10 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 80 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 213 ; 5A ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD26 ; 240 ; 5A ; HEX3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD27 ; 222 ; 5A ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD29 ; 255 ; 5B ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD30 ; 257 ; 5B ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE11 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE29 ; 253 ; 5B ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE30 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 67 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 57 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 114 ; 3B ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AF29 ; 237 ; 5A ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AF30 ; 239 ; 5A ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AG30 ; 243 ; 5A ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH16 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AH29 ; 218 ; 5A ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AH30 ; 241 ; 5A ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ29 ; 216 ; 5A ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK10 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK20 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
-; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
-; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
-; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
-; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
-; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
-; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
-; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
-; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
-; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
-; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
-; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
-; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U23 ; ; 5B ; VCCPD5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V16 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; V18 ; 194 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; V23 ; 236 ; 5A ; HEX4[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W15 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; W16 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; W17 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W19 ; 192 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; W20 ; 217 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W21 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 223 ; 5A ; HEX4[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; W24 ; 238 ; 5A ; HEX4[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; W25 ; 244 ; 5B ; HEX4[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y16 ; 128 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y19 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y21 ; 219 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y23 ; 232 ; 5A ; HEX4[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; Y24 ; 234 ; 5A ; HEX4[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
-; |ex6 ; 98.5 (0.5) ; 99.5 (0.5) ; 1.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 188 (1) ; 35 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 38 ; 0 ; |ex6 ; ex6 ; work ;
-; |bin2bcd_16:B| ; 57.0 (0.0) ; 57.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 106 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B ; bin2bcd_16 ; work ;
-; |add3_ge5:A1| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A1 ; add3_ge5 ; work ;
-; |add3_ge5:A10| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A10 ; add3_ge5 ; work ;
-; |add3_ge5:A11| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A11 ; add3_ge5 ; work ;
-; |add3_ge5:A12| ; 4.0 (4.0) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A12 ; add3_ge5 ; work ;
-; |add3_ge5:A13| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A13 ; add3_ge5 ; work ;
-; |add3_ge5:A14| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A14 ; add3_ge5 ; work ;
-; |add3_ge5:A15| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A15 ; add3_ge5 ; work ;
-; |add3_ge5:A16| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A16 ; add3_ge5 ; work ;
-; |add3_ge5:A17| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A17 ; add3_ge5 ; work ;
-; |add3_ge5:A18| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A18 ; add3_ge5 ; work ;
-; |add3_ge5:A19| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A19 ; add3_ge5 ; work ;
-; |add3_ge5:A2| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A2 ; add3_ge5 ; work ;
-; |add3_ge5:A20| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A20 ; add3_ge5 ; work ;
-; |add3_ge5:A21| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A21 ; add3_ge5 ; work ;
-; |add3_ge5:A22| ; 4.0 (4.0) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A22 ; add3_ge5 ; work ;
-; |add3_ge5:A23| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A23 ; add3_ge5 ; work ;
-; |add3_ge5:A24| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A24 ; add3_ge5 ; work ;
-; |add3_ge5:A25| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A25 ; add3_ge5 ; work ;
-; |add3_ge5:A26| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A26 ; add3_ge5 ; work ;
-; |add3_ge5:A27| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A27 ; add3_ge5 ; work ;
-; |add3_ge5:A28| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A28 ; add3_ge5 ; work ;
-; |add3_ge5:A29| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A29 ; add3_ge5 ; work ;
-; |add3_ge5:A3| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A3 ; add3_ge5 ; work ;
-; |add3_ge5:A4| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A4 ; add3_ge5 ; work ;
-; |add3_ge5:A5| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A5 ; add3_ge5 ; work ;
-; |add3_ge5:A6| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A6 ; add3_ge5 ; work ;
-; |add3_ge5:A7| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A7 ; add3_ge5 ; work ;
-; |add3_ge5:A8| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A8 ; add3_ge5 ; work ;
-; |add3_ge5:A9| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A9 ; add3_ge5 ; work ;
-; |counter_16:C| ; 8.5 (8.5) ; 8.5 (8.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|counter_16:C ; counter_16 ; work ;
-; |hex_to_7seg:SEG0| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG1| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG2| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG3| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG3 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG4| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG4 ; hex_to_7seg ; work ;
-; |tick_50000:tck| ; 15.0 (15.0) ; 16.0 (16.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (29) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|tick_50000:tck ; tick_50000 ; work ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; KEY[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; KEY[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; CLOCK_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-
-
-+---------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+---------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------------------+-------------------+---------+
-; KEY[1] ; ; ;
-; - counter_16:C|count[14] ; 0 ; 0 ;
-; - counter_16:C|count[15] ; 0 ; 0 ;
-; - counter_16:C|count[0] ; 0 ; 0 ;
-; - counter_16:C|count[1] ; 0 ; 0 ;
-; - counter_16:C|count[2] ; 0 ; 0 ;
-; - counter_16:C|count[3] ; 0 ; 0 ;
-; - counter_16:C|count[4] ; 0 ; 0 ;
-; - counter_16:C|count[5] ; 0 ; 0 ;
-; - counter_16:C|count[6] ; 0 ; 0 ;
-; - counter_16:C|count[7] ; 0 ; 0 ;
-; - counter_16:C|count[8] ; 0 ; 0 ;
-; - counter_16:C|count[9] ; 0 ; 0 ;
-; - counter_16:C|count[10] ; 0 ; 0 ;
-; - counter_16:C|count[11] ; 0 ; 0 ;
-; - counter_16:C|count[12] ; 0 ; 0 ;
-; - counter_16:C|count[13] ; 0 ; 0 ;
-; - counter_16:C|count[14]~0 ; 0 ; 0 ;
-; KEY[0] ; ; ;
-; - counter_16:C|count[14]~0 ; 0 ; 0 ;
-; CLOCK_50 ; ; ;
-; - tick_50000:tck|CLK_OUT ; 0 ; 0 ;
-+---------------------------------+-------------------+---------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 2 ; Clock ; no ; -- ; -- ; -- ;
-; CLOCK_50 ; PIN_AF14 ; 18 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ;
-; KEY[1] ; PIN_AA15 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ;
-; counter_16:C|count[14]~0 ; LABCELL_X46_Y1_N30 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
-; tick_50000:tck|CLK_OUT ; FF_X33_Y1_N20 ; 17 ; Clock ; no ; -- ; -- ; -- ;
-; tick_50000:tck|Equal0~3 ; LABCELL_X33_Y1_N48 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ;
-+--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 18 ; Global Clock ; GCLK6 ; -- ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------+
-; Routing Usage Summary ;
-+---------------------------------------------+-------------------------+
-; Routing Resource Type ; Usage ;
-+---------------------------------------------+-------------------------+
-; Block interconnects ; 179 / 289,320 ( < 1 % ) ;
-; C12 interconnects ; 5 / 13,420 ( < 1 % ) ;
-; C2 interconnects ; 61 / 119,108 ( < 1 % ) ;
-; C4 interconnects ; 56 / 56,300 ( < 1 % ) ;
-; DQS bus muxes ; 0 / 25 ( 0 % ) ;
-; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
-; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
-; Direct links ; 45 / 289,320 ( < 1 % ) ;
-; Global clocks ; 1 / 16 ( 6 % ) ;
-; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
-; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
-; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
-; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
-; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ;
-; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
-; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
-; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
-; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
-; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
-; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ;
-; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
-; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
-; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
-; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
-; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
-; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
-; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
-; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
-; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
-; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
-; Local interconnects ; 81 / 84,580 ( < 1 % ) ;
-; Quadrant clocks ; 0 / 66 ( 0 % ) ;
-; R14 interconnects ; 7 / 12,676 ( < 1 % ) ;
-; R14/C12 interconnect drivers ; 12 / 20,720 ( < 1 % ) ;
-; R3 interconnects ; 80 / 130,992 ( < 1 % ) ;
-; R6 interconnects ; 160 / 266,960 ( < 1 % ) ;
-; Spine clocks ; 1 / 360 ( < 1 % ) ;
-; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
-+---------------------------------------------+-------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 28 ;
-; Number of I/O Rules Passed ; 6 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 22 ;
-+----------------------------------+-------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-; Total Pass ; 38 ; 0 ; 38 ; 0 ; 0 ; 38 ; 38 ; 0 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 0 ; 38 ; 0 ; 38 ; 38 ; 0 ; 0 ; 38 ; 0 ; 0 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+-----------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+-----------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Passive Serial ;
-; Enable Error Detection CRC_ERROR pin ; Off ;
-; Enable CvP_CONFDONE pin ; Off ;
-; Enable open drain on CRC_ERROR pin ; On ;
-; Enable open drain on CvP_CONFDONE pin ; On ;
-; Enable open drain on INIT_DONE pin ; On ;
-; Enable open drain on Partial Reconfiguration pins ; Off ;
-; Enable open drain on nCEO pin ; On ;
-; Enable Partial Reconfiguration pins ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Enable internal scrubbing ; Off ;
-; Active Serial clock source ; 100 MHz Internal Oscillator ;
-; Device initialization clock source ; Internal Oscillator ;
-; Configuration via Protocol ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; Enable nCEO output ; Off ;
-; Data[15..8] ; Unreserved ;
-; Data[7..5] ; Unreserved ;
-; Base pin-out file on sameframe device ; Off ;
-+------------------------------------------------------------------+-----------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.10 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary ;
-+-----------------+----------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
-
-
-+-----------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details ;
-+--------------------------+------------------------+-------------------+
-; Source Register ; Destination Register ; Delay Added in ns ;
-+--------------------------+------------------------+-------------------+
-; tick_50000:tck|count[14] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[13] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[12] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[11] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[10] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[9] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[8] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[15] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[5] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[4] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[3] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[2] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[1] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[0] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[7] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|count[6] ; tick_50000:tck|CLK_OUT ; 0.948 ;
-; tick_50000:tck|CLK_OUT ; tick_50000:tck|CLK_OUT ; 0.948 ;
-+--------------------------+------------------------+-------------------+
-Note: This table only shows the top 17 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device 5CSEMA5F31C6 for design "ex6"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Info (184020): Starting Fitter periphery placement operations
-Info (11191): Automatically promoted 1 clock (1 global)
- Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
-Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
-Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10
-Info (332104): Reading SDC File: 'ex6.sdc'
-Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
- Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
-Info (332111): Found 1 clocks
- Info (332111): Period Clock Name
- Info (332111): ======== ============
- Info (332111): 20.000 CLOCK_50
-Info (170189): Fitter placement preparation operations beginning
-Info (14951): The Fitter is using Advanced Physical Optimization.
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.13 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file C:/New folder/ex6/output_files/ex6.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 48 warnings
- Info: Peak virtual memory: 2591 megabytes
- Info: Processing ended: Tue Nov 22 11:43:33 2016
- Info: Elapsed time: 00:00:30
- Info: Total CPU time (on all processors): 00:00:53
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in C:/New folder/ex6/output_files/ex6.fit.smsg.
-
-
+Fitter report for ex6
+Sun Dec 11 18:08:29 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Fitter Netlist Optimizations
+ 6. Ignored Assignments
+ 7. Incremental Compilation Preservation Summary
+ 8. Incremental Compilation Partition Settings
+ 9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. I/O Assignment Warnings
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Routing Usage Summary
+ 24. I/O Rules Summary
+ 25. I/O Rules Details
+ 26. I/O Rules Matrix
+ 27. Fitter Device Options
+ 28. Operating Settings and Conditions
+ 29. Estimated Delay Added for Hold Timing Summary
+ 30. Estimated Delay Added for Hold Timing Details
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-------------------------------------------------------------------------------+
+; Fitter Summary ;
++---------------------------------+---------------------------------------------+
+; Fitter Status ; Successful - Sun Dec 11 18:08:29 2016 ;
+; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Revision Name ; ex6 ;
+; Top-level Entity Name ; ex6 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 99 / 32,070 ( < 1 % ) ;
+; Total registers ; 33 ;
+; Total pins ; 38 / 457 ( 8 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total RAM Blocks ; 0 / 397 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
+; Optimize Hold Timing ; All Paths ; All Paths ;
+; Optimize Multi-Corner Timing ; On ; On ;
+; Auto RAM to MLAB Conversion ; On ; On ;
+; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
+; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
+; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
+; SSN Optimization ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
+; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification ; Auto ; Auto ;
+; Enable Beneficial Skew Optimization ; On ; On ;
+; Optimize Design for Metastability ; On ; On ;
+; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+; Clamping Diode ; Off ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
+; Advanced Physical Optimization ; On ; On ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.01 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.5% ;
+; Processor 3 ; 0.5% ;
+; Processor 4 ; 0.5% ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations ;
++-----------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
+; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
++-----------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
++-----------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location ; ; ; ADC_CS ; PIN_AG20 ; QSF Assignment ;
+; Location ; ; ; ADC_SCK ; PIN_AF21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDI ; PIN_AG21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDO ; PIN_AJ21 ; QSF Assignment ;
+; Location ; ; ; DAC_CS ; PIN_AD20 ; QSF Assignment ;
+; Location ; ; ; DAC_LD ; PIN_AK21 ; QSF Assignment ;
+; Location ; ; ; DAC_SCK ; PIN_AF20 ; QSF Assignment ;
+; Location ; ; ; DAC_SDI ; PIN_AG18 ; QSF Assignment ;
+; Location ; ; ; HEX5[0] ; PIN_V25 ; QSF Assignment ;
+; Location ; ; ; HEX5[1] ; PIN_AA28 ; QSF Assignment ;
+; Location ; ; ; HEX5[2] ; PIN_Y27 ; QSF Assignment ;
+; Location ; ; ; HEX5[3] ; PIN_AB27 ; QSF Assignment ;
+; Location ; ; ; HEX5[4] ; PIN_AB26 ; QSF Assignment ;
+; Location ; ; ; HEX5[5] ; PIN_AA26 ; QSF Assignment ;
+; Location ; ; ; HEX5[6] ; PIN_AA25 ; QSF Assignment ;
+; Location ; ; ; KEY[2] ; PIN_W15 ; QSF Assignment ;
+; Location ; ; ; KEY[3] ; PIN_Y16 ; QSF Assignment ;
+; Location ; ; ; LEDR[0] ; PIN_V16 ; QSF Assignment ;
+; Location ; ; ; LEDR[1] ; PIN_W16 ; QSF Assignment ;
+; Location ; ; ; LEDR[2] ; PIN_V17 ; QSF Assignment ;
+; Location ; ; ; LEDR[3] ; PIN_V18 ; QSF Assignment ;
+; Location ; ; ; LEDR[4] ; PIN_W17 ; QSF Assignment ;
+; Location ; ; ; LEDR[5] ; PIN_W19 ; QSF Assignment ;
+; Location ; ; ; LEDR[6] ; PIN_Y19 ; QSF Assignment ;
+; Location ; ; ; LEDR[7] ; PIN_W20 ; QSF Assignment ;
+; Location ; ; ; LEDR[8] ; PIN_W21 ; QSF Assignment ;
+; Location ; ; ; LEDR[9] ; PIN_Y21 ; QSF Assignment ;
+; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ;
+; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ;
+; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ;
+; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ;
+; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ;
+; Location ; ; ; PWM_OUT ; PIN_AJ20 ; QSF Assignment ;
+; Location ; ; ; SW[0] ; PIN_AB12 ; QSF Assignment ;
+; Location ; ; ; SW[1] ; PIN_AC12 ; QSF Assignment ;
+; Location ; ; ; SW[2] ; PIN_AF9 ; QSF Assignment ;
+; Location ; ; ; SW[3] ; PIN_AF10 ; QSF Assignment ;
+; Location ; ; ; SW[4] ; PIN_AD11 ; QSF Assignment ;
+; Location ; ; ; SW[5] ; PIN_AD12 ; QSF Assignment ;
+; Location ; ; ; SW[6] ; PIN_AE11 ; QSF Assignment ;
+; Location ; ; ; SW[7] ; PIN_AC9 ; QSF Assignment ;
+; Location ; ; ; SW[8] ; PIN_AD10 ; QSF Assignment ;
+; Location ; ; ; SW[9] ; PIN_AE12 ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; ADC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; ADC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; ADC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; ADC_SDO ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; DAC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; DAC_LD ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; DAC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; DAC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; KEY[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; KEY[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; LEDR[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; LEDR[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; LEDR[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; LEDR[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; LEDR[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; LEDR[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; LEDR[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; LEDR[7] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; LEDR[8] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; LEDR[9] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; PWM_OUT ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; SW[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; SW[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; SW[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; SW[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; SW[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; SW[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; SW[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; SW[7] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; SW[8] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex6 ; ; SW[9] ; 3.3-V LVTTL ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 ) ;
+; -- Achieved ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 ) ;
+; ; ; ; ;
+; Routing (by net) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
+; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top ; 0.00 % ( 0 / 298 ) ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource ; Usage ; % ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 99 / 32,070 ; < 1 % ;
+; ALMs needed [=A-B+C] ; 99 ; ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 100 / 32,070 ; < 1 % ;
+; [a] ALMs used for LUT logic and registers ; 16 ; ;
+; [b] ALMs used for LUT logic ; 83 ; ;
+; [c] ALMs used for registers ; 1 ; ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
+; [B] Estimate of ALMs recoverable by dense packing ; 1 / 32,070 ; < 1 % ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ;
+; [a] Due to location constrained logic ; 0 ; ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; ;
+; [c] Due to LAB input limits ; 0 ; ;
+; [d] Due to virtual I/Os ; 0 ; ;
+; ; ; ;
+; Difficulty packing design ; Low ; ;
+; ; ; ;
+; Total LABs: partially or completely used ; 15 / 3,207 ; < 1 % ;
+; -- Logic LABs ; 15 ; ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 188 ; ;
+; -- 7 input functions ; 0 ; ;
+; -- 6 input functions ; 9 ; ;
+; -- 5 input functions ; 3 ; ;
+; -- 4 input functions ; 124 ; ;
+; -- <=3 input functions ; 52 ; ;
+; Combinational ALUT usage for route-throughs ; 1 ; ;
+; ; ; ;
+; Dedicated logic registers ; 33 ; ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 33 / 64,140 ; < 1 % ;
+; -- Secondary logic registers ; 0 / 64,140 ; 0 % ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 33 ; ;
+; -- Routing optimization registers ; 0 ; ;
+; ; ; ;
+; Virtual pins ; 0 ; ;
+; I/O pins ; 38 / 457 ; 8 % ;
+; -- Clock pins ; 1 / 8 ; 13 % ;
+; -- Dedicated input pins ; 0 / 21 ; 0 % ;
+; ; ; ;
+; Hard processor system peripheral utilization ; ; ;
+; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
+; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
+; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
+; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
+; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
+; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
+; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
+; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
+; -- JTAG ; 0 / 1 ( 0 % ) ; ;
+; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
+; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
+; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
+; -- STM event ; 0 / 1 ( 0 % ) ; ;
+; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
+; -- DMA ; 0 / 1 ( 0 % ) ; ;
+; -- CAN ; 0 / 2 ( 0 % ) ; ;
+; -- EMAC ; 0 / 2 ( 0 % ) ; ;
+; -- I2C ; 0 / 4 ( 0 % ) ; ;
+; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
+; -- QSPI ; 0 / 1 ( 0 % ) ; ;
+; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
+; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
+; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
+; -- UART ; 0 / 2 ( 0 % ) ; ;
+; -- USB ; 0 / 2 ( 0 % ) ; ;
+; ; ; ;
+; M10K blocks ; 0 / 397 ; 0 % ;
+; Total MLAB memory bits ; 0 ; ;
+; Total block memory bits ; 0 / 4,065,280 ; 0 % ;
+; Total block memory implementation bits ; 0 / 4,065,280 ; 0 % ;
+; ; ; ;
+; Total DSP Blocks ; 0 / 87 ; 0 % ;
+; ; ; ;
+; Fractional PLLs ; 0 / 6 ; 0 % ;
+; Global signals ; 1 ; ;
+; -- Global clocks ; 1 / 16 ; 6 % ;
+; -- Quadrant clocks ; 0 / 66 ; 0 % ;
+; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ;
+; SERDES Transmitters ; 0 / 100 ; 0 % ;
+; SERDES Receivers ; 0 / 100 ; 0 % ;
+; JTAGs ; 0 / 1 ; 0 % ;
+; ASMI blocks ; 0 / 1 ; 0 % ;
+; CRC blocks ; 0 / 1 ; 0 % ;
+; Remote update blocks ; 0 / 1 ; 0 % ;
+; Oscillator blocks ; 0 / 1 ; 0 % ;
+; Impedance control blocks ; 0 / 4 ; 0 % ;
+; Hard Memory Controllers ; 0 / 2 ; 0 % ;
+; Average interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; ;
+; Peak interconnect usage (total/H/V) ; 0.8% / 0.7% / 1.0% ; ;
+; Maximum fan-out ; 17 ; ;
+; Highest non-global fan-out ; 17 ; ;
+; Total fan-out ; 848 ; ;
+; Average fan-out ; 2.84 ; ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Statistic ; Top ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 99 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; ALMs needed [=A-B+C] ; 99 ; 0 ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 100 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] ALMs used for LUT logic and registers ; 16 ; 0 ;
+; [b] ALMs used for LUT logic ; 83 ; 0 ;
+; [c] ALMs used for registers ; 1 ; 0 ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
+; [B] Estimate of ALMs recoverable by dense packing ; 1 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] Due to location constrained logic ; 0 ; 0 ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
+; [c] Due to LAB input limits ; 0 ; 0 ;
+; [d] Due to virtual I/Os ; 0 ; 0 ;
+; ; ; ;
+; Difficulty packing design ; Low ; Low ;
+; ; ; ;
+; Total LABs: partially or completely used ; 15 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ;
+; -- Logic LABs ; 15 ; 0 ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 188 ; 0 ;
+; -- 7 input functions ; 0 ; 0 ;
+; -- 6 input functions ; 9 ; 0 ;
+; -- 5 input functions ; 3 ; 0 ;
+; -- 4 input functions ; 124 ; 0 ;
+; -- <=3 input functions ; 52 ; 0 ;
+; Combinational ALUT usage for route-throughs ; 1 ; 0 ;
+; Memory ALUT usage ; 0 ; 0 ;
+; -- 64-address deep ; 0 ; 0 ;
+; -- 32-address deep ; 0 ; 0 ;
+; ; ; ;
+; Dedicated logic registers ; 0 ; 0 ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 33 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
+; -- Secondary logic registers ; 0 / 64140 ( 0 % ) ; 0 / 64140 ( 0 % ) ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 33 ; 0 ;
+; -- Routing optimization registers ; 0 ; 0 ;
+; ; ; ;
+; ; ; ;
+; Virtual pins ; 0 ; 0 ;
+; I/O pins ; 38 ; 0 ;
+; I/O registers ; 0 ; 0 ;
+; Total block memory bits ; 0 ; 0 ;
+; Total block memory implementation bits ; 0 ; 0 ;
+; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ;
+; ; ; ;
+; Connections ; ; ;
+; -- Input Connections ; 0 ; 0 ;
+; -- Registered Input Connections ; 0 ; 0 ;
+; -- Output Connections ; 0 ; 0 ;
+; -- Registered Output Connections ; 0 ; 0 ;
+; ; ; ;
+; Internal Connections ; ; ;
+; -- Total Connections ; 848 ; 0 ;
+; -- Registered Connections ; 139 ; 0 ;
+; ; ; ;
+; External Connections ; ; ;
+; -- Top ; 0 ; 0 ;
+; -- hard_block:auto_generated_inst ; 0 ; 0 ;
+; ; ; ;
+; Partition Interface ; ; ;
+; -- Input Ports ; 3 ; 0 ;
+; -- Output Ports ; 35 ; 0 ;
+; -- Bidir Ports ; 0 ; 0 ;
+; ; ; ;
+; Registered Ports ; ; ;
+; -- Registered Input Ports ; 0 ; 0 ;
+; -- Registered Output Ports ; 0 ; 0 ;
+; ; ; ;
+; Port Connectivity ; ; ;
+; -- Input Ports driven by GND ; 0 ; 0 ;
+; -- Output Ports driven by GND ; 0 ; 0 ;
+; -- Input Ports driven by VCC ; 0 ; 0 ;
+; -- Output Ports driven by VCC ; 0 ; 0 ;
+; -- Input Ports with no Source ; 0 ; 0 ;
+; -- Output Ports with no Source ; 0 ; 0 ;
+; -- Input Ports with no Fanout ; 0 ; 0 ;
+; -- Output Ports with no Fanout ; 0 ; 0 ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; CLOCK_50 ; AF14 ; 3B ; 32 ; 0 ; 0 ; 17 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; KEY[0] ; AA14 ; 3B ; 36 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; KEY[1] ; AA15 ; 3B ; 36 ; 0 ; 17 ; 17 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[0] ; AJ29 ; 5A ; 89 ; 6 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[1] ; AH29 ; 5A ; 89 ; 6 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[2] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[3] ; AG30 ; 5A ; 89 ; 16 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[4] ; AF29 ; 5A ; 89 ; 15 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[5] ; AF30 ; 5A ; 89 ; 15 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[6] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[0] ; AB23 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[1] ; AE29 ; 5B ; 89 ; 23 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[2] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[3] ; AC28 ; 5B ; 89 ; 20 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[4] ; AD30 ; 5B ; 89 ; 25 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[5] ; AC29 ; 5B ; 89 ; 20 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[6] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[0] ; AD26 ; 5A ; 89 ; 16 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[1] ; AC27 ; 5A ; 89 ; 16 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[2] ; AD25 ; 5A ; 89 ; 4 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[3] ; AC25 ; 5A ; 89 ; 4 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[4] ; AB28 ; 5B ; 89 ; 21 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[5] ; AB25 ; 5A ; 89 ; 11 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[6] ; AB22 ; 5A ; 89 ; 9 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[0] ; AA24 ; 5A ; 89 ; 11 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[1] ; Y23 ; 5A ; 89 ; 13 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[2] ; Y24 ; 5A ; 89 ; 13 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[3] ; W22 ; 5A ; 89 ; 8 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[4] ; W24 ; 5A ; 89 ; 15 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[5] ; V23 ; 5A ; 89 ; 15 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[6] ; W25 ; 5B ; 89 ; 20 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; 3A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 3B ; 3 / 48 ( 6 % ) ; 3.3V ; -- ; 3.3V ;
+; 4A ; 0 / 80 ( 0 % ) ; 3.3V ; -- ; 3.3V ;
+; 5A ; 27 / 32 ( 84 % ) ; 3.3V ; -- ; 3.3V ;
+; 5B ; 8 / 16 ( 50 % ) ; 3.3V ; -- ; 3.3V ;
+; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
+; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
+; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA14 ; 122 ; 3B ; KEY[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA15 ; 120 ; 3B ; KEY[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA17 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AA24 ; 228 ; 5A ; HEX4[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA27 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB12 ; 72 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB14 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB22 ; 225 ; 5A ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB23 ; 227 ; 5A ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB25 ; 230 ; 5A ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB28 ; 249 ; 5B ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC11 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC12 ; 82 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC21 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AC25 ; 215 ; 5A ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC27 ; 242 ; 5A ; HEX3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC28 ; 245 ; 5B ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC29 ; 247 ; 5B ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC30 ; 259 ; 5B ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD8 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD10 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD11 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD12 ; 80 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD18 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD25 ; 213 ; 5A ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD26 ; 240 ; 5A ; HEX3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD27 ; 222 ; 5A ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD29 ; 255 ; 5B ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD30 ; 257 ; 5B ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE11 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE12 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE15 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE25 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE29 ; 253 ; 5B ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE30 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF9 ; 67 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF10 ; 57 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF14 ; 114 ; 3B ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF22 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AF29 ; 237 ; 5A ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AF30 ; 239 ; 5A ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG4 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG19 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG30 ; 243 ; 5A ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH16 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH26 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH29 ; 218 ; 5A ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH30 ; 241 ; 5A ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ29 ; 216 ; 5A ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK10 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK20 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
+; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
+; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
+; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
+; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
+; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
+; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
+; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
+; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
+; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
+; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
+; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
+; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
+; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
+; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
+; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U23 ; ; 5B ; VCCPD5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V16 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V18 ; 194 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V23 ; 236 ; 5A ; HEX4[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W15 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W16 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W17 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W19 ; 192 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; W20 ; 217 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W21 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W22 ; 223 ; 5A ; HEX4[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; W24 ; 238 ; 5A ; HEX4[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W25 ; 244 ; 5B ; HEX4[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y16 ; 128 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y19 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y21 ; 219 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; Y23 ; 232 ; 5A ; HEX4[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y24 ; 234 ; 5A ; HEX4[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings ;
++----------+--------------------------------------+
+; Pin Name ; Reason ;
++----------+--------------------------------------+
+; HEX0[0] ; Missing drive strength and slew rate ;
+; HEX0[1] ; Missing drive strength and slew rate ;
+; HEX0[2] ; Missing drive strength and slew rate ;
+; HEX0[3] ; Missing drive strength and slew rate ;
+; HEX0[4] ; Missing drive strength and slew rate ;
+; HEX0[5] ; Missing drive strength and slew rate ;
+; HEX0[6] ; Missing drive strength and slew rate ;
+; HEX1[0] ; Missing drive strength and slew rate ;
+; HEX1[1] ; Missing drive strength and slew rate ;
+; HEX1[2] ; Missing drive strength and slew rate ;
+; HEX1[3] ; Missing drive strength and slew rate ;
+; HEX1[4] ; Missing drive strength and slew rate ;
+; HEX1[5] ; Missing drive strength and slew rate ;
+; HEX1[6] ; Missing drive strength and slew rate ;
+; HEX2[0] ; Missing drive strength and slew rate ;
+; HEX2[1] ; Missing drive strength and slew rate ;
+; HEX2[2] ; Missing drive strength and slew rate ;
+; HEX2[3] ; Missing drive strength and slew rate ;
+; HEX2[4] ; Missing drive strength and slew rate ;
+; HEX2[5] ; Missing drive strength and slew rate ;
+; HEX2[6] ; Missing drive strength and slew rate ;
+; HEX3[0] ; Missing drive strength and slew rate ;
+; HEX3[1] ; Missing drive strength and slew rate ;
+; HEX3[2] ; Missing drive strength and slew rate ;
+; HEX3[3] ; Missing drive strength and slew rate ;
+; HEX3[4] ; Missing drive strength and slew rate ;
+; HEX3[5] ; Missing drive strength and slew rate ;
+; HEX3[6] ; Missing drive strength and slew rate ;
+; HEX4[0] ; Missing drive strength and slew rate ;
+; HEX4[1] ; Missing drive strength and slew rate ;
+; HEX4[2] ; Missing drive strength and slew rate ;
+; HEX4[3] ; Missing drive strength and slew rate ;
+; HEX4[4] ; Missing drive strength and slew rate ;
+; HEX4[5] ; Missing drive strength and slew rate ;
+; HEX4[6] ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
+; |ex6 ; 98.5 (0.5) ; 99.5 (0.5) ; 1.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 188 (1) ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 38 ; 0 ; |ex6 ; ex6 ; work ;
+; |bin2bcd_16:B| ; 57.0 (0.0) ; 57.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 106 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B ; bin2bcd_16 ; work ;
+; |add3_ge5:A1| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A1 ; add3_ge5 ; work ;
+; |add3_ge5:A10| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A10 ; add3_ge5 ; work ;
+; |add3_ge5:A11| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A11 ; add3_ge5 ; work ;
+; |add3_ge5:A12| ; 4.0 (4.0) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A12 ; add3_ge5 ; work ;
+; |add3_ge5:A13| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A13 ; add3_ge5 ; work ;
+; |add3_ge5:A14| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A14 ; add3_ge5 ; work ;
+; |add3_ge5:A15| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A15 ; add3_ge5 ; work ;
+; |add3_ge5:A16| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A16 ; add3_ge5 ; work ;
+; |add3_ge5:A17| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A17 ; add3_ge5 ; work ;
+; |add3_ge5:A18| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A18 ; add3_ge5 ; work ;
+; |add3_ge5:A19| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A19 ; add3_ge5 ; work ;
+; |add3_ge5:A2| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A2 ; add3_ge5 ; work ;
+; |add3_ge5:A20| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A20 ; add3_ge5 ; work ;
+; |add3_ge5:A21| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A21 ; add3_ge5 ; work ;
+; |add3_ge5:A22| ; 4.0 (4.0) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A22 ; add3_ge5 ; work ;
+; |add3_ge5:A23| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A23 ; add3_ge5 ; work ;
+; |add3_ge5:A24| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A24 ; add3_ge5 ; work ;
+; |add3_ge5:A25| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A25 ; add3_ge5 ; work ;
+; |add3_ge5:A26| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A26 ; add3_ge5 ; work ;
+; |add3_ge5:A27| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A27 ; add3_ge5 ; work ;
+; |add3_ge5:A28| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A28 ; add3_ge5 ; work ;
+; |add3_ge5:A29| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A29 ; add3_ge5 ; work ;
+; |add3_ge5:A3| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A3 ; add3_ge5 ; work ;
+; |add3_ge5:A4| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A4 ; add3_ge5 ; work ;
+; |add3_ge5:A5| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A5 ; add3_ge5 ; work ;
+; |add3_ge5:A6| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A6 ; add3_ge5 ; work ;
+; |add3_ge5:A7| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A7 ; add3_ge5 ; work ;
+; |add3_ge5:A8| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A8 ; add3_ge5 ; work ;
+; |add3_ge5:A9| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A9 ; add3_ge5 ; work ;
+; |counter_16:C| ; 8.5 (8.5) ; 8.5 (8.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|counter_16:C ; counter_16 ; work ;
+; |hex_to_7seg:SEG0| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG1| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG2| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG3| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG3 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG4| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG4 ; hex_to_7seg ; work ;
+; |tick_50000:tck| ; 15.0 (15.0) ; 16.0 (16.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (29) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex6|tick_50000:tck ; tick_50000 ; work ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; KEY[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; KEY[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; CLOCK_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++---------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------------------+-------------------+---------+
+; KEY[1] ; ; ;
+; - counter_16:C|count[11] ; 0 ; 0 ;
+; - counter_16:C|count[15] ; 0 ; 0 ;
+; - counter_16:C|count[14] ; 0 ; 0 ;
+; - counter_16:C|count[13] ; 0 ; 0 ;
+; - counter_16:C|count[12] ; 0 ; 0 ;
+; - counter_16:C|count[10] ; 0 ; 0 ;
+; - counter_16:C|count[9] ; 0 ; 0 ;
+; - counter_16:C|count[7] ; 0 ; 0 ;
+; - counter_16:C|count[8] ; 0 ; 0 ;
+; - counter_16:C|count[6] ; 0 ; 0 ;
+; - counter_16:C|count[5] ; 0 ; 0 ;
+; - counter_16:C|count[4] ; 0 ; 0 ;
+; - counter_16:C|count[3] ; 0 ; 0 ;
+; - counter_16:C|count[2] ; 0 ; 0 ;
+; - counter_16:C|count[1] ; 0 ; 0 ;
+; - counter_16:C|count[0] ; 0 ; 0 ;
+; - counter_16:C|count[11]~0 ; 0 ; 0 ;
+; KEY[0] ; ; ;
+; - counter_16:C|count[11]~0 ; 1 ; 0 ;
+; CLOCK_50 ; ; ;
+; - tick_50000:tck|CLK_OUT ; 0 ; 0 ;
++---------------------------------+-------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 2 ; Clock ; no ; -- ; -- ; -- ;
+; CLOCK_50 ; PIN_AF14 ; 16 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ;
+; KEY[1] ; PIN_AA15 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ;
+; counter_16:C|count[11]~0 ; LABCELL_X40_Y2_N0 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
+; tick_50000:tck|CLK_OUT ; FF_X33_Y2_N2 ; 17 ; Clock ; no ; -- ; -- ; -- ;
+; tick_50000:tck|Equal0~3 ; LABCELL_X31_Y1_N30 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ;
++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 16 ; Global Clock ; GCLK6 ; -- ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type ; Usage ;
++---------------------------------------------+-------------------------+
+; Block interconnects ; 160 / 289,320 ( < 1 % ) ;
+; C12 interconnects ; 2 / 13,420 ( < 1 % ) ;
+; C2 interconnects ; 58 / 119,108 ( < 1 % ) ;
+; C4 interconnects ; 63 / 56,300 ( < 1 % ) ;
+; DQS bus muxes ; 0 / 25 ( 0 % ) ;
+; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
+; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
+; Direct links ; 40 / 289,320 ( < 1 % ) ;
+; Global clocks ; 1 / 16 ( 6 % ) ;
+; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
+; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
+; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
+; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
+; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
+; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
+; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
+; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
+; Local interconnects ; 85 / 84,580 ( < 1 % ) ;
+; Quadrant clocks ; 0 / 66 ( 0 % ) ;
+; R14 interconnects ; 22 / 12,676 ( < 1 % ) ;
+; R14/C12 interconnect drivers ; 24 / 20,720 ( < 1 % ) ;
+; R3 interconnects ; 67 / 130,992 ( < 1 % ) ;
+; R6 interconnects ; 132 / 266,960 ( < 1 % ) ;
+; Spine clocks ; 1 / 360 ( < 1 % ) ;
+; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary ;
++----------------------------------+-------+
+; I/O Rules Statistic ; Total ;
++----------------------------------+-------+
+; Total I/O Rules ; 28 ;
+; Number of I/O Rules Passed ; 6 ;
+; Number of I/O Rules Failed ; 0 ;
+; Number of I/O Rules Unchecked ; 0 ;
+; Number of I/O Rules Inapplicable ; 22 ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
+; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
+; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+; Pin/Rules ; IO_000002 ; IO_000003 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000022 ; IO_000021 ; IO_000046 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000047 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+; Total Pass ; 0 ; 38 ; 38 ; 0 ; 0 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 38 ; 38 ; 0 ;
+; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Inapplicable ; 38 ; 0 ; 0 ; 38 ; 38 ; 0 ; 0 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 38 ; 0 ; 0 ; 38 ;
+; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; HEX0[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; CLOCK_50 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options ;
++------------------------------------------------------------------+-----------------------------+
+; Option ; Setting ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Passive Serial ;
+; Enable Error Detection CRC_ERROR pin ; Off ;
+; Enable CvP_CONFDONE pin ; Off ;
+; Enable open drain on CRC_ERROR pin ; On ;
+; Enable open drain on CvP_CONFDONE pin ; On ;
+; Enable open drain on INIT_DONE pin ; On ;
+; Enable open drain on Partial Reconfiguration pins ; Off ;
+; Enable open drain on nCEO pin ; On ;
+; Enable Partial Reconfiguration pins ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ;
+; Enable internal scrubbing ; Off ;
+; Active Serial clock source ; 100 MHz Internal Oscillator ;
+; Device initialization clock source ; Internal Oscillator ;
+; Configuration via Protocol ; Off ;
+; Configuration Voltage Level ; Auto ;
+; Force Configuration Voltage Level ; Off ;
+; Enable nCEO output ; Off ;
+; Data[15..8] ; Unreserved ;
+; Data[7..5] ; Unreserved ;
+; Base pin-out file on sameframe device ; Off ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.10 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++-----------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details ;
++--------------------------+------------------------+-------------------+
+; Source Register ; Destination Register ; Delay Added in ns ;
++--------------------------+------------------------+-------------------+
+; tick_50000:tck|count[14] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[13] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[15] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[11] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[9] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[8] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[12] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[6] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[5] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[4] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[3] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[2] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[1] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[0] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[7] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|count[10] ; tick_50000:tck|CLK_OUT ; 0.748 ;
+; tick_50000:tck|CLK_OUT ; tick_50000:tck|CLK_OUT ; 0.748 ;
++--------------------------+------------------------+-------------------+
+Note: This table only shows the top 17 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex6"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+ Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+ Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+ Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11
+Info (332104): Reading SDC File: 'ex6.sdc'
+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
+ Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 1 clocks
+ Info (332111): Period Clock Name
+ Info (332111): ======== ============
+ Info (332111): 20.000 CLOCK_50
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22
+Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info (170201): Optimizations that may affect the design's routability were skipped
+ Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.14 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:02
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 49 warnings
+ Info: Peak virtual memory: 2132 megabytes
+ Info: Processing ended: Sun Dec 11 18:08:29 2016
+ Info: Elapsed time: 00:00:29
+ Info: Total CPU time (on all processors): 00:00:48
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg.
+
+
diff --git a/part_2/ex6/output_files/ex6.fit.smsg b/part_2/ex6/output_files/ex6.fit.smsg
index 43eead5..9302919 100755
--- a/part_2/ex6/output_files/ex6.fit.smsg
+++ b/part_2/ex6/output_files/ex6.fit.smsg
@@ -1,6 +1,6 @@
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
-Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_2/ex6/output_files/ex6.fit.summary b/part_2/ex6/output_files/ex6.fit.summary
index bc14ca7..54af65e 100755
--- a/part_2/ex6/output_files/ex6.fit.summary
+++ b/part_2/ex6/output_files/ex6.fit.summary
@@ -1,20 +1,20 @@
-Fitter Status : Successful - Tue Nov 22 11:43:32 2016
-Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex6
-Top-level Entity Name : ex6
-Family : Cyclone V
-Device : 5CSEMA5F31C6
-Timing Models : Final
-Logic utilization (in ALMs) : 99 / 32,070 ( < 1 % )
-Total registers : 35
-Total pins : 38 / 457 ( 8 % )
-Total virtual pins : 0
-Total block memory bits : 0 / 4,065,280 ( 0 % )
-Total RAM Blocks : 0 / 397 ( 0 % )
-Total DSP Blocks : 0 / 87 ( 0 % )
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0 / 6 ( 0 % )
-Total DLLs : 0 / 4 ( 0 % )
+Fitter Status : Successful - Sun Dec 11 18:08:29 2016
+Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Revision Name : ex6
+Top-level Entity Name : ex6
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 99 / 32,070 ( < 1 % )
+Total registers : 33
+Total pins : 38 / 457 ( 8 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_2/ex6/output_files/ex6.flow.rpt b/part_2/ex6/output_files/ex6.flow.rpt
index 1e44f79..5369166 100755
--- a/part_2/ex6/output_files/ex6.flow.rpt
+++ b/part_2/ex6/output_files/ex6.flow.rpt
@@ -1,128 +1,128 @@
-Flow report for ex6
-Tue Nov 22 11:43:46 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Flow Summary ;
-+---------------------------------+-------------------------------------------------+
-; Flow Status ; Successful - Tue Nov 22 11:43:40 2016 ;
-; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name ; ex6 ;
-; Top-level Entity Name ; ex6 ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Logic utilization (in ALMs) ; 99 / 32,070 ( < 1 % ) ;
-; Total registers ; 35 ;
-; Total pins ; 38 / 457 ( 8 % ) ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
-; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 / 6 ( 0 % ) ;
-; Total DLLs ; 0 / 4 ( 0 % ) ;
-+---------------------------------+-------------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 11/22/2016 11:42:53 ;
-; Main task ; Compilation ;
-; Revision Name ; ex6 ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID ; 260248564170200.147981497204968 ; -- ; -- ; -- ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 897 MB ; 00:00:21 ;
-; Fitter ; 00:00:29 ; 1.0 ; 2591 MB ; 00:00:53 ;
-; Assembler ; 00:00:06 ; 1.0 ; 892 MB ; 00:00:06 ;
-; TimeQuest Timing Analyzer ; 00:00:05 ; 1.1 ; 1209 MB ; 00:00:05 ;
-; Total ; 00:00:50 ; -- ; -- ; 00:01:25 ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Analysis & Synthesis ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
-; Fitter ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
-; Assembler ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
-; TimeQuest Timing Analyzer ; eews104a-016 ; Windows 7 ; 6.1 ; x86_64 ;
-+---------------------------+------------------+-----------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6
-quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6
-quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6
-quartus_sta ex6 -c ex6
-
-
-
+Flow report for ex6
+Sun Dec 11 18:08:41 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+ 8. Flow Messages
+ 9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-------------------------------------------------------------------------------+
+; Flow Summary ;
++---------------------------------+---------------------------------------------+
+; Flow Status ; Successful - Sun Dec 11 18:08:36 2016 ;
+; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Revision Name ; ex6 ;
+; Top-level Entity Name ; ex6 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 99 / 32,070 ( < 1 % ) ;
+; Total registers ; 33 ;
+; Total pins ; 38 / 457 ( 8 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 12/11/2016 18:07:50 ;
+; Main task ; Compilation ;
+; Revision Name ; ex6 ;
++-------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 158515234070422.148147967004252 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
+; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 1028 MB ; 00:00:24 ;
+; Fitter ; 00:00:29 ; 1.0 ; 2132 MB ; 00:00:48 ;
+; Assembler ; 00:00:06 ; 1.0 ; 976 MB ; 00:00:06 ;
+; TimeQuest Timing Analyzer ; 00:00:04 ; 1.1 ; 1214 MB ; 00:00:05 ;
+; Total ; 00:00:49 ; -- ; -- ; 00:01:23 ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++-----------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++---------------------------+------------------+------------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++---------------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
+; Fitter ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
+; Assembler ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
+; TimeQuest Timing Analyzer ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
++---------------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6
+quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6
+quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6
+quartus_sta ex6 -c ex6
+
+
+
diff --git a/part_2/ex6/output_files/ex6.jdi b/part_2/ex6/output_files/ex6.jdi
index 30e9a8a..e913aee 100755
--- a/part_2/ex6/output_files/ex6.jdi
+++ b/part_2/ex6/output_files/ex6.jdi
@@ -1,8 +1,8 @@
-<sld_project_info>
- <project>
- <hash md5_digest_80b="baef6963dc4d960fc697"/>
- </project>
- <file_info>
- <file device="5CSEMA5F31C6" path="ex6.sof" usercode="0xFFFFFFFF"/>
- </file_info>
-</sld_project_info>
+<sld_project_info>
+ <project>
+ <hash md5_digest_80b="486dd37dbb5b652de768"/>
+ </project>
+ <file_info>
+ <file device="5CSEMA5F31C6" path="ex6.sof" usercode="0xFFFFFFFF"/>
+ </file_info>
+</sld_project_info>
diff --git a/part_2/ex6/output_files/ex6.map.rpt b/part_2/ex6/output_files/ex6.map.rpt
index a381799..6d7a2e4 100755
--- a/part_2/ex6/output_files/ex6.map.rpt
+++ b/part_2/ex6/output_files/ex6.map.rpt
@@ -1,438 +1,430 @@
-Analysis & Synthesis report for ex6
-Tue Nov 22 11:43:02 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Inverted Register Statistics
- 10. Multiplexer Restructuring Statistics (Restructuring Performed)
- 11. Parameter Settings for User Entity Instance: tick_50000:tck
- 12. Parameter Settings for User Entity Instance: counter_16:C
- 13. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A18"
- 14. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A9"
- 15. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A3"
- 16. Post-Synthesis Netlist Statistics for Top Partition
- 17. Elapsed Time Per Partition
- 18. Analysis & Synthesis Messages
- 19. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+---------------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Tue Nov 22 11:43:02 2016 ;
-; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name ; ex6 ;
-; Top-level Entity Name ; ex6 ;
-; Family ; Cyclone V ;
-; Logic utilization (in ALMs) ; N/A ;
-; Total registers ; 33 ;
-; Total pins ; 38 ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 0 ;
-; Total DSP Blocks ; 0 ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 ;
-; Total DLLs ; 0 ;
-+---------------------------------+-------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Device ; 5CSEMA5F31C6 ; ;
-; Top-level entity name ; ex6 ; ex6 ;
-; Family name ; Cyclone V ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 3 ; 3 ;
-; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-; Synthesis Seed ; 1 ; 1 ;
-; Automatic Parallel Synthesis ; On ; On ;
-; Partial Reconfiguration Bitstream ID ; Off ; Off ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
-; verilog_files/hex_to_7seg.v ; yes ; User Verilog HDL File ; C:/New folder/ex6/verilog_files/hex_to_7seg.v ; ;
-; verilog_files/bin2bcd_16.v ; yes ; User Verilog HDL File ; C:/New folder/ex6/verilog_files/bin2bcd_16.v ; ;
-; verilog_files/add3_ge5.v ; yes ; User Verilog HDL File ; C:/New folder/ex6/verilog_files/add3_ge5.v ; ;
-; verilog_files/counter_16.v ; yes ; User Verilog HDL File ; C:/New folder/ex6/verilog_files/counter_16.v ; ;
-; ex6.v ; yes ; User Verilog HDL File ; C:/New folder/ex6/ex6.v ; ;
-; verilog_files/tick_50000.v ; yes ; User Verilog HDL File ; C:/New folder/ex6/verilog_files/tick_50000.v ; ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
-
-
-+----------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+------------------------+
-; Estimate of Logic utilization (ALMs needed) ; 98 ;
-; ; ;
-; Combinational ALUT usage for logic ; 187 ;
-; -- 7 input functions ; 0 ;
-; -- 6 input functions ; 9 ;
-; -- 5 input functions ; 3 ;
-; -- 4 input functions ; 124 ;
-; -- <=3 input functions ; 51 ;
-; ; ;
-; Dedicated logic registers ; 33 ;
-; ; ;
-; I/O pins ; 38 ;
-; ; ;
-; Total DSP Blocks ; 0 ;
-; ; ;
-; Maximum fan-out node ; tick_50000:tck|CLK_OUT ;
-; Maximum fan-out ; 17 ;
-; Total fan-out ; 846 ;
-; Average fan-out ; 2.86 ;
-+---------------------------------------------+------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
-; |ex6 ; 187 (0) ; 33 (0) ; 0 ; 0 ; 38 ; 0 ; |ex6 ; ex6 ; work ;
-; |bin2bcd_16:B| ; 106 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B ; bin2bcd_16 ; work ;
-; |add3_ge5:A10| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A10 ; add3_ge5 ; work ;
-; |add3_ge5:A11| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A11 ; add3_ge5 ; work ;
-; |add3_ge5:A12| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A12 ; add3_ge5 ; work ;
-; |add3_ge5:A13| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A13 ; add3_ge5 ; work ;
-; |add3_ge5:A14| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A14 ; add3_ge5 ; work ;
-; |add3_ge5:A15| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A15 ; add3_ge5 ; work ;
-; |add3_ge5:A16| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A16 ; add3_ge5 ; work ;
-; |add3_ge5:A17| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A17 ; add3_ge5 ; work ;
-; |add3_ge5:A18| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A18 ; add3_ge5 ; work ;
-; |add3_ge5:A19| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A19 ; add3_ge5 ; work ;
-; |add3_ge5:A1| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A1 ; add3_ge5 ; work ;
-; |add3_ge5:A20| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A20 ; add3_ge5 ; work ;
-; |add3_ge5:A21| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A21 ; add3_ge5 ; work ;
-; |add3_ge5:A22| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A22 ; add3_ge5 ; work ;
-; |add3_ge5:A23| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A23 ; add3_ge5 ; work ;
-; |add3_ge5:A24| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A24 ; add3_ge5 ; work ;
-; |add3_ge5:A25| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A25 ; add3_ge5 ; work ;
-; |add3_ge5:A26| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A26 ; add3_ge5 ; work ;
-; |add3_ge5:A27| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A27 ; add3_ge5 ; work ;
-; |add3_ge5:A28| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A28 ; add3_ge5 ; work ;
-; |add3_ge5:A29| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A29 ; add3_ge5 ; work ;
-; |add3_ge5:A2| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A2 ; add3_ge5 ; work ;
-; |add3_ge5:A3| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A3 ; add3_ge5 ; work ;
-; |add3_ge5:A4| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A4 ; add3_ge5 ; work ;
-; |add3_ge5:A5| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A5 ; add3_ge5 ; work ;
-; |add3_ge5:A6| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A6 ; add3_ge5 ; work ;
-; |add3_ge5:A7| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A7 ; add3_ge5 ; work ;
-; |add3_ge5:A8| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A8 ; add3_ge5 ; work ;
-; |add3_ge5:A9| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A9 ; add3_ge5 ; work ;
-; |counter_16:C| ; 17 (17) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; |ex6|counter_16:C ; counter_16 ; work ;
-; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG3 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG4| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG4 ; hex_to_7seg ; work ;
-; |tick_50000:tck| ; 29 (29) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex6|tick_50000:tck ; tick_50000 ; work ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 33 ;
-; Number of registers using Synchronous Clear ; 24 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 16 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+--------------------------------------------------+
-; Inverted Register Statistics ;
-+----------------------------------------+---------+
-; Inverted Register ; Fan out ;
-+----------------------------------------+---------+
-; tick_50000:tck|count[8] ; 3 ;
-; tick_50000:tck|count[0] ; 2 ;
-; tick_50000:tck|count[1] ; 2 ;
-; tick_50000:tck|count[2] ; 2 ;
-; tick_50000:tck|count[5] ; 2 ;
-; tick_50000:tck|count[7] ; 2 ;
-; tick_50000:tck|count[13] ; 2 ;
-; tick_50000:tck|count[14] ; 2 ;
-; Total number of inverted registers = 8 ; ;
-+----------------------------------------+---------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
-; 3:1 ; 16 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |ex6|counter_16:C|count[14] ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
-
-
-+-------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_50000:tck ;
-+----------------+-------+------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+------------------------------------+
-; NBIT ; 16 ; Signed Integer ;
-+----------------+-------+------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------+
-; Parameter Settings for User Entity Instance: counter_16:C ;
-+----------------+-------+----------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+----------------------------------+
-; BIT_SZ ; 16 ; Signed Integer ;
-+----------------+-------+----------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A18" ;
-+------+-------+----------+-----------------------------+
-; Port ; Type ; Severity ; Details ;
-+------+-------+----------+-----------------------------+
-; w[3] ; Input ; Info ; Stuck at GND ;
-+------+-------+----------+-----------------------------+
-
-
-+------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A9" ;
-+------+-------+----------+----------------------------+
-; Port ; Type ; Severity ; Details ;
-+------+-------+----------+----------------------------+
-; w[3] ; Input ; Info ; Stuck at GND ;
-+------+-------+----------+----------------------------+
-
-
-+------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A3" ;
-+------+-------+----------+----------------------------+
-; Port ; Type ; Severity ; Details ;
-+------+-------+----------+----------------------------+
-; w[3] ; Input ; Info ; Stuck at GND ;
-+------+-------+----------+----------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; arriav_ff ; 33 ;
-; ENA SCLR ; 16 ;
-; SCLR ; 8 ;
-; plain ; 9 ;
-; arriav_lcell_comb ; 204 ;
-; arith ; 32 ;
-; 1 data inputs ; 32 ;
-; normal ; 172 ;
-; 1 data inputs ; 25 ;
-; 2 data inputs ; 1 ;
-; 3 data inputs ; 10 ;
-; 4 data inputs ; 124 ;
-; 5 data inputs ; 3 ;
-; 6 data inputs ; 9 ;
-; boundary_port ; 38 ;
-; ; ;
-; Max LUT depth ; 13.00 ;
-; Average LUT depth ; 8.75 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
- Info: Processing started: Tue Nov 22 11:42:52 2016
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
- Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex6/verilog_files/hex_to_7seg.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
- Info (12023): Found entity 1: bin2bcd_16 File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 12
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
- Info (12023): Found entity 1: add3_ge5 File: C:/New folder/ex6/verilog_files/add3_ge5.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
- Info (12023): Found entity 1: counter_16 File: C:/New folder/ex6/verilog_files/counter_16.v Line: 3
-Info (12021): Found 1 design units, including 1 entities, in source file ex6.v
- Info (12023): Found entity 1: ex6 File: C:/New folder/ex6/ex6.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
- Info (12023): Found entity 1: tick_50000 File: C:/New folder/ex6/verilog_files/tick_50000.v Line: 1
-Info (12127): Elaborating entity "ex6" for the top level hierarchy
-Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:tck" File: C:/New folder/ex6/ex6.v Line: 11
-Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:C" File: C:/New folder/ex6/ex6.v Line: 13
-Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:B" File: C:/New folder/ex6/ex6.v Line: 15
-Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:B|add3_ge5:A1" File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 26
-Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: C:/New folder/ex6/ex6.v Line: 17
-Info (286030): Timing-Driven Synthesis is running
-Info (144001): Generated suppressed messages file C:/New folder/ex6/output_files/ex6.map.smsg
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 225 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 3 input pins
- Info (21059): Implemented 35 output pins
- Info (21061): Implemented 187 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 897 megabytes
- Info: Processing ended: Tue Nov 22 11:43:02 2016
- Info: Elapsed time: 00:00:10
- Info: Total CPU time (on all processors): 00:00:21
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in C:/New folder/ex6/output_files/ex6.map.smsg.
-
-
+Analysis & Synthesis report for ex6
+Sun Dec 11 18:08:00 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Source Files Read
+ 6. Analysis & Synthesis Resource Usage Summary
+ 7. Analysis & Synthesis Resource Utilization by Entity
+ 8. General Register Statistics
+ 9. Inverted Register Statistics
+ 10. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 11. Parameter Settings for User Entity Instance: tick_50000:tck
+ 12. Parameter Settings for User Entity Instance: counter_16:C
+ 13. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A18"
+ 14. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A9"
+ 15. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A3"
+ 16. Post-Synthesis Netlist Statistics for Top Partition
+ 17. Elapsed Time Per Partition
+ 18. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++---------------------------------+---------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Sun Dec 11 18:08:00 2016 ;
+; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Revision Name ; ex6 ;
+; Top-level Entity Name ; ex6 ;
+; Family ; Cyclone V ;
+; Logic utilization (in ALMs) ; N/A ;
+; Total registers ; 33 ;
+; Total pins ; 38 ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 ;
+; Total DSP Blocks ; 0 ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++---------------------------------+---------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Top-level entity name ; ex6 ; ex6 ;
+; Family name ; Cyclone V ; Cyclone V ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; OpenCore Plus hardware evaluation ; Enable ; Enable ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Infer RAMs from Raw Logic ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; On ; On ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 3 ; 3 ;
+; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
+; Automatic Parallel Synthesis ; On ; On ;
+; Partial Reconfiguration Bitstream ID ; Off ; Off ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.0% ;
+; Processors 3-4 ; 0.0% ;
++----------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
+; verilog_files/hex_to_7seg.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/hex_to_7seg.v ; ;
+; verilog_files/bin2bcd_16.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v ; ;
+; verilog_files/add3_ge5.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/add3_ge5.v ; ;
+; verilog_files/counter_16.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/counter_16.v ; ;
+; ex6.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v ; ;
+; verilog_files/tick_50000.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/tick_50000.v ; ;
++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
+
+
++----------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+------------------------+
+; Resource ; Usage ;
++---------------------------------------------+------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 98 ;
+; ; ;
+; Combinational ALUT usage for logic ; 187 ;
+; -- 7 input functions ; 0 ;
+; -- 6 input functions ; 9 ;
+; -- 5 input functions ; 3 ;
+; -- 4 input functions ; 124 ;
+; -- <=3 input functions ; 51 ;
+; ; ;
+; Dedicated logic registers ; 33 ;
+; ; ;
+; I/O pins ; 38 ;
+; ; ;
+; Total DSP Blocks ; 0 ;
+; ; ;
+; Maximum fan-out node ; tick_50000:tck|CLK_OUT ;
+; Maximum fan-out ; 17 ;
+; Total fan-out ; 846 ;
+; Average fan-out ; 2.86 ;
++---------------------------------------------+------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
+; |ex6 ; 187 (0) ; 33 (0) ; 0 ; 0 ; 38 ; 0 ; |ex6 ; ex6 ; work ;
+; |bin2bcd_16:B| ; 106 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B ; bin2bcd_16 ; work ;
+; |add3_ge5:A10| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A10 ; add3_ge5 ; work ;
+; |add3_ge5:A11| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A11 ; add3_ge5 ; work ;
+; |add3_ge5:A12| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A12 ; add3_ge5 ; work ;
+; |add3_ge5:A13| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A13 ; add3_ge5 ; work ;
+; |add3_ge5:A14| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A14 ; add3_ge5 ; work ;
+; |add3_ge5:A15| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A15 ; add3_ge5 ; work ;
+; |add3_ge5:A16| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A16 ; add3_ge5 ; work ;
+; |add3_ge5:A17| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A17 ; add3_ge5 ; work ;
+; |add3_ge5:A18| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A18 ; add3_ge5 ; work ;
+; |add3_ge5:A19| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A19 ; add3_ge5 ; work ;
+; |add3_ge5:A1| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A1 ; add3_ge5 ; work ;
+; |add3_ge5:A20| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A20 ; add3_ge5 ; work ;
+; |add3_ge5:A21| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A21 ; add3_ge5 ; work ;
+; |add3_ge5:A22| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A22 ; add3_ge5 ; work ;
+; |add3_ge5:A23| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A23 ; add3_ge5 ; work ;
+; |add3_ge5:A24| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A24 ; add3_ge5 ; work ;
+; |add3_ge5:A25| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A25 ; add3_ge5 ; work ;
+; |add3_ge5:A26| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A26 ; add3_ge5 ; work ;
+; |add3_ge5:A27| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A27 ; add3_ge5 ; work ;
+; |add3_ge5:A28| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A28 ; add3_ge5 ; work ;
+; |add3_ge5:A29| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A29 ; add3_ge5 ; work ;
+; |add3_ge5:A2| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A2 ; add3_ge5 ; work ;
+; |add3_ge5:A3| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A3 ; add3_ge5 ; work ;
+; |add3_ge5:A4| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A4 ; add3_ge5 ; work ;
+; |add3_ge5:A5| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A5 ; add3_ge5 ; work ;
+; |add3_ge5:A6| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A6 ; add3_ge5 ; work ;
+; |add3_ge5:A7| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A7 ; add3_ge5 ; work ;
+; |add3_ge5:A8| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A8 ; add3_ge5 ; work ;
+; |add3_ge5:A9| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|bin2bcd_16:B|add3_ge5:A9 ; add3_ge5 ; work ;
+; |counter_16:C| ; 17 (17) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; |ex6|counter_16:C ; counter_16 ; work ;
+; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG3 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG4| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex6|hex_to_7seg:SEG4 ; hex_to_7seg ; work ;
+; |tick_50000:tck| ; 29 (29) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex6|tick_50000:tck ; tick_50000 ; work ;
++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 33 ;
+; Number of registers using Synchronous Clear ; 24 ;
+; Number of registers using Synchronous Load ; 0 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 16 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics ;
++----------------------------------------+---------+
+; Inverted Register ; Fan out ;
++----------------------------------------+---------+
+; tick_50000:tck|count[8] ; 3 ;
+; tick_50000:tck|count[0] ; 2 ;
+; tick_50000:tck|count[1] ; 2 ;
+; tick_50000:tck|count[2] ; 2 ;
+; tick_50000:tck|count[5] ; 2 ;
+; tick_50000:tck|count[7] ; 2 ;
+; tick_50000:tck|count[13] ; 2 ;
+; tick_50000:tck|count[14] ; 2 ;
+; Total number of inverted registers = 8 ; ;
++----------------------------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+; 3:1 ; 16 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |ex6|counter_16:C|count[11] ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+
+
++-------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_50000:tck ;
++----------------+-------+------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+------------------------------------+
+; NBIT ; 16 ; Signed Integer ;
++----------------+-------+------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------+
+; Parameter Settings for User Entity Instance: counter_16:C ;
++----------------+-------+----------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+----------------------------------+
+; BIT_SZ ; 16 ; Signed Integer ;
++----------------+-------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A18" ;
++------+-------+----------+-----------------------------+
+; Port ; Type ; Severity ; Details ;
++------+-------+----------+-----------------------------+
+; w[3] ; Input ; Info ; Stuck at GND ;
++------+-------+----------+-----------------------------+
+
+
++------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A9" ;
++------+-------+----------+----------------------------+
+; Port ; Type ; Severity ; Details ;
++------+-------+----------+----------------------------+
+; w[3] ; Input ; Info ; Stuck at GND ;
++------+-------+----------+----------------------------+
+
+
++------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A3" ;
++------+-------+----------+----------------------------+
+; Port ; Type ; Severity ; Details ;
++------+-------+----------+----------------------------+
+; w[3] ; Input ; Info ; Stuck at GND ;
++------+-------+----------+----------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type ; Count ;
++-----------------------+-----------------------------+
+; arriav_ff ; 33 ;
+; ENA SCLR ; 16 ;
+; SCLR ; 8 ;
+; plain ; 9 ;
+; arriav_lcell_comb ; 204 ;
+; arith ; 32 ;
+; 1 data inputs ; 32 ;
+; normal ; 172 ;
+; 1 data inputs ; 25 ;
+; 2 data inputs ; 1 ;
+; 3 data inputs ; 10 ;
+; 4 data inputs ; 124 ;
+; 5 data inputs ; 3 ;
+; 6 data inputs ; 9 ;
+; boundary_port ; 38 ;
+; ; ;
+; Max LUT depth ; 13.00 ;
+; Average LUT depth ; 8.75 ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top ; 00:00:00 ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+ Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+ Info: Processing started: Sun Dec 11 18:07:50 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+ Info (12023): Found entity 1: hex_to_7seg File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+ Info (12023): Found entity 1: bin2bcd_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+ Info (12023): Found entity 1: add3_ge5 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/add3_ge5.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
+ Info (12023): Found entity 1: counter_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/counter_16.v Line: 3
+Info (12021): Found 1 design units, including 1 entities, in source file ex6.v
+ Info (12023): Found entity 1: ex6 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
+ Info (12023): Found entity 1: tick_50000 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/tick_50000.v Line: 1
+Info (12127): Elaborating entity "ex6" for the top level hierarchy
+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:tck" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v Line: 11
+Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:C" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v Line: 13
+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:B" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v Line: 15
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:B|add3_ge5:A1" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v Line: 26
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v Line: 17
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+ Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 225 device resources after synthesis - the final resource count might be different
+ Info (21058): Implemented 3 input pins
+ Info (21059): Implemented 35 output pins
+ Info (21061): Implemented 187 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 1071 megabytes
+ Info: Processing ended: Sun Dec 11 18:08:00 2016
+ Info: Elapsed time: 00:00:10
+ Info: Total CPU time (on all processors): 00:00:25
+
+
diff --git a/part_2/ex6/output_files/ex6.map.summary b/part_2/ex6/output_files/ex6.map.summary
index c25655f..7cf513f 100755
--- a/part_2/ex6/output_files/ex6.map.summary
+++ b/part_2/ex6/output_files/ex6.map.summary
@@ -1,17 +1,17 @@
-Analysis & Synthesis Status : Successful - Tue Nov 22 11:43:02 2016
-Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex6
-Top-level Entity Name : ex6
-Family : Cyclone V
-Logic utilization (in ALMs) : N/A
-Total registers : 33
-Total pins : 38
-Total virtual pins : 0
-Total block memory bits : 0
-Total DSP Blocks : 0
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0
-Total DLLs : 0
+Analysis & Synthesis Status : Successful - Sun Dec 11 18:08:00 2016
+Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Revision Name : ex6
+Top-level Entity Name : ex6
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 33
+Total pins : 38
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_2/ex6/output_files/ex6.pin b/part_2/ex6/output_files/ex6.pin
index c13fc33..119ca1d 100755
--- a/part_2/ex6/output_files/ex6.pin
+++ b/part_2/ex6/output_files/ex6.pin
@@ -1,976 +1,977 @@
- -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
- -- Your use of Altera Corporation's design tools, logic functions
- -- and other software and tools, and its AMPP partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Altera Program License
- -- Subscription Agreement, the Altera Quartus Prime License Agreement,
- -- the Altera MegaCore Function License Agreement, or other
- -- applicable license agreement, including, without limitation,
- -- that your use is for the sole purpose of programming logic
- -- devices manufactured by Altera and sold by Altera or its
- -- authorized distributors. Please refer to the applicable
- -- agreement for further details.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 3A: 2.5V
- -- Bank 3B: 3.3V
- -- Bank 4A: 3.3V
- -- Bank 5A: 3.3V
- -- Bank 5B: 3.3V
- -- Bank 6B: 2.5V
- -- Bank 6A: 2.5V
- -- Bank 7A: 2.5V
- -- Bank 7B: 2.5V
- -- Bank 7C: 2.5V
- -- Bank 7D: 2.5V
- -- Bank 8A: 2.5V
- -- RREF : External reference resistor for the quad, MUST be connected to
- -- GND via a 2k Ohm resistor.
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
- -- must not be connected.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-CHIP "ex6" ASSIGNED TO AN: 5CSEMA5F31C6
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND : A2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A :
-VCCIO8A : A7 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A :
-GND : A12 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C :
-GND : A17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B :
-GND : A22 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A :
-GND : A26 : : : : 7A :
-GND : A27 : gnd : : : :
-HPS_TRST : A28 : : : : 7A :
-HPS_TMS : A29 : : : : 7A :
-GND : AA1 : gnd : : : :
-GND : AA2 : gnd : : : :
-GND : AA3 : gnd : : : :
-GND : AA4 : gnd : : : :
-VCC : AA5 : power : : 1.1V : :
-GND : AA6 : gnd : : : :
-DNU : AA7 : : : : :
-VCCA_FPLL : AA8 : power : : 2.5V : :
-GND : AA9 : gnd : : : :
-VCCPD3A : AA10 : power : : 2.5V : 3A :
-GND : AA11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3B :
-KEY[0] : AA14 : input : 3.3-V LVTTL : : 3B : Y
-KEY[1] : AA15 : input : 3.3-V LVTTL : : 3B : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
-VCCIO4A : AA17 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
-GND : AA22 : gnd : : : :
-VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : :
-HEX4[0] : AA24 : output : 3.3-V LVTTL : : 5A : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
-VCCIO5B : AA27 : power : : 3.3V : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 5B :
-VREFB5BN0 : AA29 : power : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B :
-GND : AB1 : gnd : : : :
-GND : AB2 : gnd : : : :
-DNU : AB3 : : : : :
-DNU : AB4 : : : : :
-GND : AB5 : gnd : : : :
-VCCA_FPLL : AB6 : power : : 2.5V : :
-GND : AB7 : gnd : : : :
-nCSO, DATA4 : AB8 : : : : 3A :
-TDO : AB9 : output : : : 3A :
-VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : :
-VCC_AUX : AB11 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B :
-VCCIO3B : AB14 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B :
-VCC_AUX : AB16 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
-VCCPD3B4A : AB18 : power : : 3.3V : 3B, 4A :
-GND : AB19 : gnd : : : :
-VCCPD3B4A : AB20 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A :
-HEX3[6] : AB22 : output : 3.3-V LVTTL : : 5A : Y
-HEX2[0] : AB23 : output : 3.3-V LVTTL : : 5A : Y
-VCCIO5A : AB24 : power : : 3.3V : 5A :
-HEX3[5] : AB25 : output : 3.3-V LVTTL : : 5A : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5B :
-HEX3[4] : AB28 : output : 3.3-V LVTTL : : 5B : Y
-GND : AB29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B :
-GND : AC1 : gnd : : : :
-GND : AC2 : gnd : : : :
-GND : AC3 : gnd : : : :
-GND : AC4 : gnd : : : :
-TCK : AC5 : input : : : 3A :
-GND : AC6 : gnd : : : :
-AS_DATA3, DATA3 : AC7 : : : : 3A :
-GND : AC8 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3A :
-VCCPD3A : AC10 : power : : 2.5V : 3A :
-VCCIO3A : AC11 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3A :
-VCCPD3B4A : AC13 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3B :
-VCCPD3B4A : AC15 : power : : 3.3V : 3B, 4A :
-GND : AC16 : gnd : : : :
-VCCPD3B4A : AC17 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
-VCCPD3B4A : AC19 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
-VCCIO4A : AC21 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
-VREFB5AN0 : AC24 : power : : : 5A :
-HEX3[3] : AC25 : output : 3.3-V LVTTL : : 5A : Y
-GND : AC26 : gnd : : : :
-HEX3[1] : AC27 : output : 3.3-V LVTTL : : 5A : Y
-HEX2[3] : AC28 : output : 3.3-V LVTTL : : 5B : Y
-HEX2[5] : AC29 : output : 3.3-V LVTTL : : 5B : Y
-HEX2[6] : AC30 : output : 3.3-V LVTTL : : 5B : Y
-GND : AD1 : gnd : : : :
-GND : AD2 : gnd : : : :
-DNU : AD3 : : : : :
-DNU : AD4 : : : : :
-GND : AD5 : gnd : : : :
-VREFB3AN0 : AD6 : power : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
-VCCIO3A : AD8 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3A :
-VCCIO3B : AD13 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B :
-DNU : AD15 : : : : :
-VCCPD3B4A : AD16 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
-VCCIO4A : AD18 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
-VCC_AUX : AD22 : power : : 2.5V : :
-GND : AD23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A :
-HEX3[2] : AD25 : output : 3.3-V LVTTL : : 5A : Y
-HEX3[0] : AD26 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[6] : AD27 : output : 3.3-V LVTTL : : 5A : Y
-VCCIO5A : AD28 : power : : 3.3V : 5A :
-HEX2[2] : AD29 : output : 3.3-V LVTTL : : 5B : Y
-HEX2[4] : AD30 : output : 3.3-V LVTTL : : 5B : Y
-GND : AE1 : gnd : : : :
-GND : AE2 : gnd : : : :
-GND : AE3 : gnd : : : :
-GND : AE4 : gnd : : : :
-AS_DATA1, DATA1 : AE5 : : : : 3A :
-AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3A :
-AS_DATA2, DATA2 : AE8 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3A :
-GND : AE10 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B :
-VCCIO3B : AE15 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
-GND : AE20 : gnd : : : :
-VCCPD3B4A : AE21 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
-VCCIO4A : AE25 : power : : 3.3V : 4A :
-HEX0[0] : AE26 : output : 3.3-V LVTTL : : 5A : Y
-HEX0[1] : AE27 : output : 3.3-V LVTTL : : 5A : Y
-HEX0[2] : AE28 : output : 3.3-V LVTTL : : 5A : Y
-HEX2[1] : AE29 : output : 3.3-V LVTTL : : 5B : Y
-VCCIO5B : AE30 : power : : 3.3V : 5B :
-GND : AF1 : gnd : : : :
-GND : AF2 : gnd : : : :
-GND : AF3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A :
-VCCIO3A : AF7 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
-GND : AF12 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B :
-CLOCK_50 : AF14 : input : 3.3-V LVTTL : : 3B : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
-GND : AF17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
-VCCIO4A : AF22 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A :
-GND : AF27 : gnd : : : :
-HEX0[4] : AF28 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[4] : AF29 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[5] : AF30 : output : 3.3-V LVTTL : : 5A : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A :
-VCCIO3A : AG4 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3A :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B :
-GND : AG14 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
-VCCIO4A : AG19 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
-HEX0[3] : AG27 : output : 3.3-V LVTTL : : 5A : Y
-HEX0[5] : AG28 : output : 3.3-V LVTTL : : 5A : Y
-VCCIO5A : AG29 : power : : 3.3V : 5A :
-HEX1[3] : AG30 : output : 3.3-V LVTTL : : 5A : Y
-GND : AH1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A :
-GND : AH6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3B :
-GND : AH11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH15 : : : : 3B :
-VCCIO4A : AH16 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A :
-GND : AH21 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4A :
-VCCIO4A : AH26 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
-HEX0[6] : AH28 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[1] : AH29 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[2] : AH30 : output : 3.3-V LVTTL : : 5A : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2 : : : : 3A :
-GND : AJ3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B :
-VCCIO3B : AJ8 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B :
-VCCIO3B : AJ13 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B :
-VREFB3BN0 : AJ15 : power : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A :
-GND : AJ18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 4A :
-VCCIO4A : AJ23 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A :
-GND : AJ28 : gnd : : : :
-HEX1[0] : AJ29 : output : 3.3-V LVTTL : : 5A : Y
-GND : AJ30 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK4 : : : : 3B :
-GND : AK5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B :
-VCCIO3B : AK10 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B :
-GND : AK15 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A :
-VREFB4AN0 : AK17 : power : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A :
-VCCIO4A : AK20 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A :
-GND : AK25 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK29 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A :
-VCCIO8A : B4 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A :
-GND : B9 : gnd : : : :
-VREFB8AN0 : B10 : power : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A :
-GND : B14 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B :
-GND : B19 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A :
-HPS_TDI : B27 : : : : 7A :
-HPS_TDO : B28 : : : : 7A :
-GND : B29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A :
-GND : C6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A :
-VCCIO8A : C11 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D :
-GND : C16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B :
-GND : C21 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A :
-GND : C26 : gnd : : : :
-HPS_nRST : C27 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
-VCCIO8A : D8 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
-GND : D13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C :
-VCCIO7C_HPS : D18 : power : : 2.5V : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A :
-GND : D23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A :
-HPS_CLK1 : D25 : : : : 7A :
-GND : D26 : : : : 7A :
-HPS_RZQ_0 : D27 : : : : 6A :
-VCCIO6A_HPS : D28 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A :
-VCCIO8A : E5 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
-GND : E10 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D :
-VCCIO7D_HPS : E15 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B :
-VCCIO7B_HPS : E20 : power : : 2.5V : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B :
-VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A :
-GND : E25 : gnd : : : :
-DNU : E26 : : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A :
-GND : E30 : gnd : : : :
-DNU : F1 : : : : :
-GND : F2 : gnd : : : :
-CONF_DONE : F3 : : : : 9A :
-nSTATUS : F4 : : : : 9A :
-GND : F5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
-GND : F7 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A :
-VCCIO8A : F12 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D :
-GND : F17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B :
-VCCIO7A_HPS : F22 : power : : 2.5V : 7A :
-HPS_nPOR : F23 : : : : 7A :
-HPS_PORSEL : F24 : : : : 7A :
-HPS_CLK2 : F25 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
-GND : F27 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A :
-GND : G1 : : : : :
-DNU : G2 : : : : :
-GND : G3 : gnd : : : :
-GND : G4 : gnd : : : :
-nCE : G5 : : : : 9A :
-MSEL2 : G6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8A :
-VCCIO8A : G9 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A :
-VCCIO8A : G14 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C :
-VCCIO7B_HPS : G19 : power : : 2.5V : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A :
-VCCRSTCLK_HPS : G23 : : : : 7A :
-GND : G24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
-VCCIO6A_HPS : G29 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A :
-GND : H1 : gnd : : : :
-GND : H2 : gnd : : : :
-DNU : H3 : : : : :
-DNU : H4 : : : : :
-GND : H5 : gnd : : : :
-VCCIO8A : H6 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
-VCCBAT : H9 : power : : 1.2V : :
-VCC_AUX : H10 : power : : 2.5V : :
-GND : H11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A :
-VCCIO7D_HPS : H16 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A :
-VCCIO7A_HPS : H21 : power : : 2.5V : 7A :
-HPS_TCK : H22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
-VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A :
-GND : J1 : gnd : : : :
-GND : J2 : gnd : : : :
-GND : J3 : gnd : : : :
-GND : J4 : gnd : : : :
-nCONFIG : J5 : : : : 9A :
-GND : J6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
-GND : J8 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
-VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A :
-VCCIO8A : J13 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8A :
-DNU : J15 : : : : :
-VCC_AUX : J16 : power : : 2.5V : :
-VCCPD7C_HPS : J17 : power : : 2.5V : 7C :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B :
-VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : :
-VCC_AUX_SHARED : J21 : power : : 2.5V : :
-GND : J22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
-GND : J28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A :
-GND : K1 : gnd : : : :
-GND : K2 : gnd : : : :
-DNU : K3 : : : : :
-DNU : K4 : : : : :
-GND : K5 : gnd : : : :
-MSEL1 : K6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
-VCCA_FPLL : K9 : power : : 2.5V : :
-GND : K10 : gnd : : : :
-VCCPD8A : K11 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 8A :
-VCCPD8A : K13 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A :
-GND : K15 : gnd : : : :
-VCCPD7D_HPS : K16 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B :
-VCCPD7B_HPS : K18 : power : : 2.5V : 7B :
-VCCPD7A_HPS : K19 : power : : 2.5V : 7A :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
-VCCIO6A_HPS : K24 : power : : 2.5V : 6A :
-GND : K25 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A :
-VCCIO6A_HPS : K30 : power : : 2.5V : 6A :
-GND : L1 : gnd : : : :
-GND : L2 : gnd : : : :
-GND : L3 : gnd : : : :
-GND : L4 : gnd : : : :
-VCC : L5 : power : : 1.1V : :
-GND : L6 : gnd : : : :
-MSEL3 : L7 : : : : 9A :
-MSEL0 : L8 : : : : 9A :
-MSEL4 : L9 : : : : 9A :
-VCCPD8A : L10 : power : : 2.5V : 8A :
-GND : L11 : gnd : : : :
-VCCPD8A : L12 : power : : 2.5V : 8A :
-GND : L13 : gnd : : : :
-VCCPD8A : L14 : power : : 2.5V : 8A :
-GND : L15 : gnd : : : :
-VCC_HPS : L16 : power : : 1.1V : :
-GND : L17 : gnd : : : :
-VCC_HPS : L18 : power : : 1.1V : :
-GND : L19 : gnd : : : :
-VCC_HPS : L20 : power : : 1.1V : :
-VCCPLL_HPS : L21 : power : : 2.5V : :
-GND : L22 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A :
-VCCIO6A_HPS : L27 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A :
-GND : M1 : gnd : : : :
-GND : M2 : gnd : : : :
-DNU : M3 : : : : :
-DNU : M4 : : : : :
-GND : M5 : gnd : : : :
-VCC : M6 : power : : 1.1V : :
-GND : M7 : gnd : : : :
-GND : M8 : gnd : : : :
-VCC : M9 : power : : 1.1V : :
-GND : M10 : gnd : : : :
-VCC : M11 : power : : 1.1V : :
-GND : M12 : gnd : : : :
-VCC : M13 : power : : 1.1V : :
-GND : M14 : gnd : : : :
-VCC_HPS : M15 : power : : 1.1V : :
-GND : M16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D :
-GND : M18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A :
-GND : M20 : gnd : : : :
-VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A :
-VCCIO6A_HPS : M24 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
-GND : M29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A :
-GND : N1 : gnd : : : :
-GND : N2 : gnd : : : :
-GND : N3 : gnd : : : :
-GND : N4 : gnd : : : :
-VCC : N5 : power : : 1.1V : :
-GND : N6 : gnd : : : :
-VCCA_FPLL : N7 : power : : 2.5V : :
-GND : N8 : gnd : : : :
-GND : N9 : gnd : : : :
-VCC : N10 : power : : 1.1V : :
-GND : N11 : gnd : : : :
-VCC : N12 : power : : 1.1V : :
-GND : N13 : gnd : : : :
-VCC : N14 : power : : 1.1V : :
-GND : N15 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D :
-GND : N17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A :
-GND : N19 : gnd : : : :
-VCC_HPS : N20 : power : : 1.1V : :
-VCCIO6A_HPS : N21 : power : : 2.5V : 6A :
-VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A :
-GND : N26 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B :
-GND : P1 : gnd : : : :
-GND : P2 : gnd : : : :
-DNU : P3 : : : : :
-DNU : P4 : : : : :
-GND : P5 : gnd : : : :
-VCCA_FPLL : P6 : power : : 2.5V : :
-GND : P7 : gnd : : : :
-GND : P8 : gnd : : : :
-GND : P9 : gnd : : : :
-GND : P10 : gnd : : : :
-VCC : P11 : power : : 1.1V : :
-GND : P12 : gnd : : : :
-VCC : P13 : power : : 1.1V : :
-GND : P14 : gnd : : : :
-VCC_HPS : P15 : power : : 1.1V : :
-GND : P16 : gnd : : : :
-VCC_HPS : P17 : power : : 1.1V : :
-GND : P18 : gnd : : : :
-VCC_HPS : P19 : power : : 1.1V : :
-GND : P20 : gnd : : : :
-VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B :
-VCCIO6B_HPS : P23 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B :
-VCCIO6B_HPS : P28 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B :
-GND : R1 : gnd : : : :
-GND : R2 : gnd : : : :
-GND : R3 : gnd : : : :
-GND : R4 : gnd : : : :
-VCC : R5 : power : : 1.1V : :
-GND : R6 : gnd : : : :
-VCCA_FPLL : R7 : power : : 2.5V : :
-GND : R8 : gnd : : : :
-GND : R9 : gnd : : : :
-VCC : R10 : power : : 1.1V : :
-GND : R11 : gnd : : : :
-VCC : R12 : power : : 1.1V : :
-GND : R13 : gnd : : : :
-VCC : R14 : power : : 1.1V : :
-GND : R15 : gnd : : : :
-VCC_HPS : R16 : power : : 1.1V : :
-GND : R17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B :
-VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B :
-VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
-VCCIO6B_HPS : R25 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B :
-GND : R30 : gnd : : : :
-GND : T1 : gnd : : : :
-GND : T2 : gnd : : : :
-DNU : T3 : : : : :
-DNU : T4 : : : : :
-GND : T5 : gnd : : : :
-VCC : T6 : power : : 1.1V : :
-GND : T7 : gnd : : : :
-GND : T8 : gnd : : : :
-GND : T9 : gnd : : : :
-GND : T10 : gnd : : : :
-VCC : T11 : power : : 1.1V : :
-GND : T12 : gnd : : : :
-VCC : T13 : power : : 1.1V : :
-GND : T14 : gnd : : : :
-GND : T15 : gnd : : : :
-GND : T16 : gnd : : : :
-VCC_HPS : T17 : power : : 1.1V : :
-GND : T18 : gnd : : : :
-VCC_HPS : T19 : power : : 1.1V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B :
-VCCIO6B_HPS : T22 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
-GND : T27 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B :
-GND : U1 : gnd : : : :
-GND : U2 : gnd : : : :
-GND : U3 : gnd : : : :
-GND : U4 : gnd : : : :
-VCC : U5 : power : : 1.1V : :
-GND : U6 : gnd : : : :
-DCLK : U7 : : : : 3A :
-TDI : U8 : input : : : 3A :
-GND : U9 : gnd : : : :
-VCC : U10 : power : : 1.1V : :
-GND : U11 : gnd : : : :
-VCC : U12 : power : : 1.1V : :
-GND : U13 : gnd : : : :
-VCC : U14 : power : : 1.1V : :
-GND : U15 : gnd : : : :
-VCC_HPS : U16 : power : : 1.1V : :
-GND : U17 : gnd : : : :
-VCC_HPS : U18 : power : : 1.1V : :
-VCCIO6B_HPS : U19 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B :
-VCC : U21 : power : : 1.1V : :
-GND : U22 : gnd : : : :
-VCCPD5B : U23 : power : : 3.3V : 5B :
-GND : U24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
-GND : U29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B :
-GND : V1 : gnd : : : :
-GND : V2 : gnd : : : :
-DNU : V3 : : : : :
-DNU : V4 : : : : :
-GND : V5 : gnd : : : :
-VCCA_FPLL : V6 : power : : 2.5V : :
-GND : V7 : gnd : : : :
-VCCA_FPLL : V8 : power : : 2.5V : :
-TMS : V9 : input : : : 3A :
-GND : V10 : gnd : : : :
-VCC : V11 : power : : 1.1V : :
-GND : V12 : gnd : : : :
-VCC : V13 : power : : 1.1V : :
-GND : V14 : gnd : : : :
-VCC : V15 : power : : 1.1V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
-GND : V19 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
-GND : V21 : gnd : : : :
-VCCPD5A : V22 : power : : 3.3V : 5A :
-HEX4[5] : V23 : output : 3.3-V LVTTL : : 5A : Y
-VCCPD5A : V24 : power : : 3.3V : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
-VCCIO6B_HPS : V26 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B :
-GND : W1 : gnd : : : :
-GND : W2 : gnd : : : :
-GND : W3 : gnd : : : :
-GND : W4 : gnd : : : :
-VCC : W5 : power : : 1.1V : :
-GND : W6 : gnd : : : :
-GND : W7 : gnd : : : :
-GND : W8 : gnd : : : :
-GND : W9 : gnd : : : :
-VCC : W10 : power : : 1.1V : :
-GND : W11 : gnd : : : :
-VCC : W12 : power : : 1.1V : :
-GND : W13 : gnd : : : :
-VCC : W14 : power : : 1.1V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
-GND : W18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
-HEX4[3] : W22 : output : 3.3-V LVTTL : : 5A : Y
-VCCIO5A : W23 : power : : 3.3V : 5A :
-HEX4[4] : W24 : output : 3.3-V LVTTL : : 5A : Y
-HEX4[6] : W25 : output : 3.3-V LVTTL : : 5B : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B :
-GND : W28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B :
-GND : Y1 : gnd : : : :
-GND : Y2 : gnd : : : :
-DNU : Y3 : : : : :
-DNU : Y4 : : : : :
-GND : Y5 : gnd : : : :
-VCC : Y6 : power : : 1.1V : :
-GND : Y7 : gnd : : : :
-GND : Y8 : gnd : : : :
-VCC : Y9 : power : : 1.1V : :
-GND : Y10 : gnd : : : :
-VCC : Y11 : power : : 1.1V : :
-GND : Y12 : gnd : : : :
-VCC : Y13 : power : : 1.1V : :
-GND : Y14 : gnd : : : :
-GND : Y15 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
-GND : Y20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5A :
-VCCA_FPLL : Y22 : power : : 2.5V : :
-HEX4[1] : Y23 : output : 3.3-V LVTTL : : 5A : Y
-HEX4[2] : Y24 : output : 3.3-V LVTTL : : 5A : Y
-GND : Y25 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B :
-GND : Y30 : gnd : : : :
+ -- Copyright (C) 2016 Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Intel Program License
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel MegaCore Function License Agreement, or other
+ -- applicable license agreement, including, without limitation,
+ -- that your use is for the sole purpose of programming logic
+ -- devices manufactured by Intel and sold by Intel or its
+ -- authorized distributors. Please refer to the applicable
+ -- agreement for further details.
+ --
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 3A: 2.5V
+ -- Bank 3B: 3.3V
+ -- Bank 4A: 3.3V
+ -- Bank 5A: 3.3V
+ -- Bank 5B: 3.3V
+ -- Bank 6B: 2.5V
+ -- Bank 6A: 2.5V
+ -- Bank 7A: 2.5V
+ -- Bank 7B: 2.5V
+ -- Bank 7C: 2.5V
+ -- Bank 7D: 2.5V
+ -- Bank 8A: 2.5V
+ -- Bank 9A: Dedicated configuration pins only, no VCCIO required.
+ -- RREF : External reference resistor for the quad, MUST be connected to
+ -- GND via a 2k Ohm resistor.
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
+ -- must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+CHIP "ex6" ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A :
+VCCIO8A : A7 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A :
+GND : A12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C :
+GND : A17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B :
+GND : A22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A :
+GND : A26 : : : : 7A :
+GND : A27 : gnd : : : :
+HPS_TRST : A28 : : : : 7A :
+HPS_TMS : A29 : : : : 7A :
+GND : AA1 : gnd : : : :
+GND : AA2 : gnd : : : :
+GND : AA3 : gnd : : : :
+GND : AA4 : gnd : : : :
+VCC : AA5 : power : : 1.1V : :
+GND : AA6 : gnd : : : :
+DNU : AA7 : : : : :
+VCCA_FPLL : AA8 : power : : 2.5V : :
+GND : AA9 : gnd : : : :
+VCCPD3A : AA10 : power : : 2.5V : 3A :
+GND : AA11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3B :
+KEY[0] : AA14 : input : 3.3-V LVTTL : : 3B : Y
+KEY[1] : AA15 : input : 3.3-V LVTTL : : 3B : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
+VCCIO4A : AA17 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
+GND : AA22 : gnd : : : :
+VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : :
+HEX4[0] : AA24 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
+VCCIO5B : AA27 : power : : 3.3V : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 5B :
+VREFB5BN0 : AA29 : power : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B :
+GND : AB1 : gnd : : : :
+GND : AB2 : gnd : : : :
+DNU : AB3 : : : : :
+DNU : AB4 : : : : :
+GND : AB5 : gnd : : : :
+VCCA_FPLL : AB6 : power : : 2.5V : :
+GND : AB7 : gnd : : : :
+nCSO, DATA4 : AB8 : : : : 3A :
+TDO : AB9 : output : : : 3A :
+VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX : AB11 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B :
+VCCIO3B : AB14 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B :
+VCC_AUX : AB16 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
+VCCPD3B4A : AB18 : power : : 3.3V : 3B, 4A :
+GND : AB19 : gnd : : : :
+VCCPD3B4A : AB20 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A :
+HEX3[6] : AB22 : output : 3.3-V LVTTL : : 5A : Y
+HEX2[0] : AB23 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AB24 : power : : 3.3V : 5A :
+HEX3[5] : AB25 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5B :
+HEX3[4] : AB28 : output : 3.3-V LVTTL : : 5B : Y
+GND : AB29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B :
+GND : AC1 : gnd : : : :
+GND : AC2 : gnd : : : :
+GND : AC3 : gnd : : : :
+GND : AC4 : gnd : : : :
+TCK : AC5 : input : : : 3A :
+GND : AC6 : gnd : : : :
+AS_DATA3, DATA3 : AC7 : : : : 3A :
+GND : AC8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3A :
+VCCPD3A : AC10 : power : : 2.5V : 3A :
+VCCIO3A : AC11 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3A :
+VCCPD3B4A : AC13 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3B :
+VCCPD3B4A : AC15 : power : : 3.3V : 3B, 4A :
+GND : AC16 : gnd : : : :
+VCCPD3B4A : AC17 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
+VCCPD3B4A : AC19 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
+VCCIO4A : AC21 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
+VREFB5AN0 : AC24 : power : : : 5A :
+HEX3[3] : AC25 : output : 3.3-V LVTTL : : 5A : Y
+GND : AC26 : gnd : : : :
+HEX3[1] : AC27 : output : 3.3-V LVTTL : : 5A : Y
+HEX2[3] : AC28 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[5] : AC29 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[6] : AC30 : output : 3.3-V LVTTL : : 5B : Y
+GND : AD1 : gnd : : : :
+GND : AD2 : gnd : : : :
+DNU : AD3 : : : : :
+DNU : AD4 : : : : :
+GND : AD5 : gnd : : : :
+VREFB3AN0 : AD6 : power : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
+VCCIO3A : AD8 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3A :
+VCCIO3B : AD13 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B :
+DNU : AD15 : : : : :
+VCCPD3B4A : AD16 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
+VCCIO4A : AD18 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
+VCC_AUX : AD22 : power : : 2.5V : :
+GND : AD23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A :
+HEX3[2] : AD25 : output : 3.3-V LVTTL : : 5A : Y
+HEX3[0] : AD26 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[6] : AD27 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AD28 : power : : 3.3V : 5A :
+HEX2[2] : AD29 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[4] : AD30 : output : 3.3-V LVTTL : : 5B : Y
+GND : AE1 : gnd : : : :
+GND : AE2 : gnd : : : :
+GND : AE3 : gnd : : : :
+GND : AE4 : gnd : : : :
+AS_DATA1, DATA1 : AE5 : : : : 3A :
+AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3A :
+AS_DATA2, DATA2 : AE8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3A :
+GND : AE10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B :
+VCCIO3B : AE15 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
+GND : AE20 : gnd : : : :
+VCCPD3B4A : AE21 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
+VCCIO4A : AE25 : power : : 3.3V : 4A :
+HEX0[0] : AE26 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[1] : AE27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[2] : AE28 : output : 3.3-V LVTTL : : 5A : Y
+HEX2[1] : AE29 : output : 3.3-V LVTTL : : 5B : Y
+VCCIO5B : AE30 : power : : 3.3V : 5B :
+GND : AF1 : gnd : : : :
+GND : AF2 : gnd : : : :
+GND : AF3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A :
+VCCIO3A : AF7 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
+GND : AF12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B :
+CLOCK_50 : AF14 : input : 3.3-V LVTTL : : 3B : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
+GND : AF17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
+VCCIO4A : AF22 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A :
+GND : AF27 : gnd : : : :
+HEX0[4] : AF28 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[4] : AF29 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[5] : AF30 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A :
+VCCIO3A : AG4 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3A :
+GND : AG9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B :
+GND : AG14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
+VCCIO4A : AG19 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
+GND : AG24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
+HEX0[3] : AG27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[5] : AG28 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AG29 : power : : 3.3V : 5A :
+HEX1[3] : AG30 : output : 3.3-V LVTTL : : 5A : Y
+GND : AH1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A :
+GND : AH6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3B :
+GND : AH11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15 : : : : 3B :
+VCCIO4A : AH16 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A :
+GND : AH21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4A :
+VCCIO4A : AH26 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
+HEX0[6] : AH28 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[1] : AH29 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[2] : AH30 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2 : : : : 3A :
+GND : AJ3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B :
+VCCIO3B : AJ8 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B :
+VCCIO3B : AJ13 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B :
+VREFB3BN0 : AJ15 : power : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A :
+GND : AJ18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 4A :
+VCCIO4A : AJ23 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A :
+GND : AJ28 : gnd : : : :
+HEX1[0] : AJ29 : output : 3.3-V LVTTL : : 5A : Y
+GND : AJ30 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4 : : : : 3B :
+GND : AK5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B :
+VCCIO3B : AK10 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B :
+GND : AK15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A :
+VREFB4AN0 : AK17 : power : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A :
+VCCIO4A : AK20 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A :
+GND : AK25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A :
+VCCIO8A : B4 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A :
+GND : B9 : gnd : : : :
+VREFB8AN0 : B10 : power : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A :
+GND : B14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B :
+GND : B19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A :
+GND : B24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A :
+HPS_TDI : B27 : : : : 7A :
+HPS_TDO : B28 : : : : 7A :
+GND : B29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A :
+GND : C1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A :
+GND : C6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A :
+VCCIO8A : C11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D :
+GND : C16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B :
+GND : C21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A :
+GND : C26 : gnd : : : :
+HPS_nRST : C27 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A :
+GND : D3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
+VCCIO8A : D8 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
+GND : D13 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C :
+VCCIO7C_HPS : D18 : power : : 2.5V : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A :
+GND : D23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A :
+HPS_CLK1 : D25 : : : : 7A :
+GND : D26 : : : : 7A :
+HPS_RZQ_0 : D27 : : : : 6A :
+VCCIO6A_HPS : D28 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A :
+VCCIO8A : E5 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
+GND : E10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D :
+VCCIO7D_HPS : E15 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B :
+VCCIO7B_HPS : E20 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B :
+VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A :
+GND : E25 : gnd : : : :
+DNU : E26 : : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A :
+GND : E30 : gnd : : : :
+DNU : F1 : : : : :
+GND : F2 : gnd : : : :
+CONF_DONE : F3 : : : : 9A :
+nSTATUS : F4 : : : : 9A :
+GND : F5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
+GND : F7 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A :
+VCCIO8A : F12 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D :
+GND : F17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B :
+VCCIO7A_HPS : F22 : power : : 2.5V : 7A :
+HPS_nPOR : F23 : : : : 7A :
+HPS_PORSEL : F24 : : : : 7A :
+HPS_CLK2 : F25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
+GND : F27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A :
+GND : G1 : : : : :
+DNU : G2 : : : : :
+GND : G3 : gnd : : : :
+GND : G4 : gnd : : : :
+nCE : G5 : : : : 9A :
+MSEL2 : G6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8A :
+VCCIO8A : G9 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A :
+VCCIO8A : G14 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C :
+VCCIO7B_HPS : G19 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A :
+VCCRSTCLK_HPS : G23 : : : : 7A :
+GND : G24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
+VCCIO6A_HPS : G29 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A :
+GND : H1 : gnd : : : :
+GND : H2 : gnd : : : :
+DNU : H3 : : : : :
+DNU : H4 : : : : :
+GND : H5 : gnd : : : :
+VCCIO8A : H6 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
+VCCBAT : H9 : power : : 1.2V : :
+VCC_AUX : H10 : power : : 2.5V : :
+GND : H11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A :
+VCCIO7D_HPS : H16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A :
+VCCIO7A_HPS : H21 : power : : 2.5V : 7A :
+HPS_TCK : H22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
+VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A :
+GND : J1 : gnd : : : :
+GND : J2 : gnd : : : :
+GND : J3 : gnd : : : :
+GND : J4 : gnd : : : :
+nCONFIG : J5 : : : : 9A :
+GND : J6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
+GND : J8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
+VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A :
+VCCIO8A : J13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8A :
+DNU : J15 : : : : :
+VCC_AUX : J16 : power : : 2.5V : :
+VCCPD7C_HPS : J17 : power : : 2.5V : 7C :
+GND : J18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B :
+VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX_SHARED : J21 : power : : 2.5V : :
+GND : J22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
+GND : J28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A :
+GND : K1 : gnd : : : :
+GND : K2 : gnd : : : :
+DNU : K3 : : : : :
+DNU : K4 : : : : :
+GND : K5 : gnd : : : :
+MSEL1 : K6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
+VCCA_FPLL : K9 : power : : 2.5V : :
+GND : K10 : gnd : : : :
+VCCPD8A : K11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 8A :
+VCCPD8A : K13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A :
+GND : K15 : gnd : : : :
+VCCPD7D_HPS : K16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B :
+VCCPD7B_HPS : K18 : power : : 2.5V : 7B :
+VCCPD7A_HPS : K19 : power : : 2.5V : 7A :
+GND : K20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
+VCCIO6A_HPS : K24 : power : : 2.5V : 6A :
+GND : K25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A :
+VCCIO6A_HPS : K30 : power : : 2.5V : 6A :
+GND : L1 : gnd : : : :
+GND : L2 : gnd : : : :
+GND : L3 : gnd : : : :
+GND : L4 : gnd : : : :
+VCC : L5 : power : : 1.1V : :
+GND : L6 : gnd : : : :
+MSEL3 : L7 : : : : 9A :
+MSEL0 : L8 : : : : 9A :
+MSEL4 : L9 : : : : 9A :
+VCCPD8A : L10 : power : : 2.5V : 8A :
+GND : L11 : gnd : : : :
+VCCPD8A : L12 : power : : 2.5V : 8A :
+GND : L13 : gnd : : : :
+VCCPD8A : L14 : power : : 2.5V : 8A :
+GND : L15 : gnd : : : :
+VCC_HPS : L16 : power : : 1.1V : :
+GND : L17 : gnd : : : :
+VCC_HPS : L18 : power : : 1.1V : :
+GND : L19 : gnd : : : :
+VCC_HPS : L20 : power : : 1.1V : :
+VCCPLL_HPS : L21 : power : : 2.5V : :
+GND : L22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A :
+VCCIO6A_HPS : L27 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A :
+GND : M1 : gnd : : : :
+GND : M2 : gnd : : : :
+DNU : M3 : : : : :
+DNU : M4 : : : : :
+GND : M5 : gnd : : : :
+VCC : M6 : power : : 1.1V : :
+GND : M7 : gnd : : : :
+GND : M8 : gnd : : : :
+VCC : M9 : power : : 1.1V : :
+GND : M10 : gnd : : : :
+VCC : M11 : power : : 1.1V : :
+GND : M12 : gnd : : : :
+VCC : M13 : power : : 1.1V : :
+GND : M14 : gnd : : : :
+VCC_HPS : M15 : power : : 1.1V : :
+GND : M16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D :
+GND : M18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A :
+GND : M20 : gnd : : : :
+VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A :
+VCCIO6A_HPS : M24 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
+GND : M29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A :
+GND : N1 : gnd : : : :
+GND : N2 : gnd : : : :
+GND : N3 : gnd : : : :
+GND : N4 : gnd : : : :
+VCC : N5 : power : : 1.1V : :
+GND : N6 : gnd : : : :
+VCCA_FPLL : N7 : power : : 2.5V : :
+GND : N8 : gnd : : : :
+GND : N9 : gnd : : : :
+VCC : N10 : power : : 1.1V : :
+GND : N11 : gnd : : : :
+VCC : N12 : power : : 1.1V : :
+GND : N13 : gnd : : : :
+VCC : N14 : power : : 1.1V : :
+GND : N15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D :
+GND : N17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A :
+GND : N19 : gnd : : : :
+VCC_HPS : N20 : power : : 1.1V : :
+VCCIO6A_HPS : N21 : power : : 2.5V : 6A :
+VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A :
+GND : N26 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B :
+GND : P1 : gnd : : : :
+GND : P2 : gnd : : : :
+DNU : P3 : : : : :
+DNU : P4 : : : : :
+GND : P5 : gnd : : : :
+VCCA_FPLL : P6 : power : : 2.5V : :
+GND : P7 : gnd : : : :
+GND : P8 : gnd : : : :
+GND : P9 : gnd : : : :
+GND : P10 : gnd : : : :
+VCC : P11 : power : : 1.1V : :
+GND : P12 : gnd : : : :
+VCC : P13 : power : : 1.1V : :
+GND : P14 : gnd : : : :
+VCC_HPS : P15 : power : : 1.1V : :
+GND : P16 : gnd : : : :
+VCC_HPS : P17 : power : : 1.1V : :
+GND : P18 : gnd : : : :
+VCC_HPS : P19 : power : : 1.1V : :
+GND : P20 : gnd : : : :
+VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B :
+VCCIO6B_HPS : P23 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B :
+VCCIO6B_HPS : P28 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B :
+GND : R1 : gnd : : : :
+GND : R2 : gnd : : : :
+GND : R3 : gnd : : : :
+GND : R4 : gnd : : : :
+VCC : R5 : power : : 1.1V : :
+GND : R6 : gnd : : : :
+VCCA_FPLL : R7 : power : : 2.5V : :
+GND : R8 : gnd : : : :
+GND : R9 : gnd : : : :
+VCC : R10 : power : : 1.1V : :
+GND : R11 : gnd : : : :
+VCC : R12 : power : : 1.1V : :
+GND : R13 : gnd : : : :
+VCC : R14 : power : : 1.1V : :
+GND : R15 : gnd : : : :
+VCC_HPS : R16 : power : : 1.1V : :
+GND : R17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B :
+VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B :
+VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
+VCCIO6B_HPS : R25 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B :
+GND : R30 : gnd : : : :
+GND : T1 : gnd : : : :
+GND : T2 : gnd : : : :
+DNU : T3 : : : : :
+DNU : T4 : : : : :
+GND : T5 : gnd : : : :
+VCC : T6 : power : : 1.1V : :
+GND : T7 : gnd : : : :
+GND : T8 : gnd : : : :
+GND : T9 : gnd : : : :
+GND : T10 : gnd : : : :
+VCC : T11 : power : : 1.1V : :
+GND : T12 : gnd : : : :
+VCC : T13 : power : : 1.1V : :
+GND : T14 : gnd : : : :
+GND : T15 : gnd : : : :
+GND : T16 : gnd : : : :
+VCC_HPS : T17 : power : : 1.1V : :
+GND : T18 : gnd : : : :
+VCC_HPS : T19 : power : : 1.1V : :
+GND : T20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B :
+VCCIO6B_HPS : T22 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
+GND : T27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B :
+GND : U1 : gnd : : : :
+GND : U2 : gnd : : : :
+GND : U3 : gnd : : : :
+GND : U4 : gnd : : : :
+VCC : U5 : power : : 1.1V : :
+GND : U6 : gnd : : : :
+DCLK : U7 : : : : 3A :
+TDI : U8 : input : : : 3A :
+GND : U9 : gnd : : : :
+VCC : U10 : power : : 1.1V : :
+GND : U11 : gnd : : : :
+VCC : U12 : power : : 1.1V : :
+GND : U13 : gnd : : : :
+VCC : U14 : power : : 1.1V : :
+GND : U15 : gnd : : : :
+VCC_HPS : U16 : power : : 1.1V : :
+GND : U17 : gnd : : : :
+VCC_HPS : U18 : power : : 1.1V : :
+VCCIO6B_HPS : U19 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B :
+VCC : U21 : power : : 1.1V : :
+GND : U22 : gnd : : : :
+VCCPD5B : U23 : power : : 3.3V : 5B :
+GND : U24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
+GND : U29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B :
+GND : V1 : gnd : : : :
+GND : V2 : gnd : : : :
+DNU : V3 : : : : :
+DNU : V4 : : : : :
+GND : V5 : gnd : : : :
+VCCA_FPLL : V6 : power : : 2.5V : :
+GND : V7 : gnd : : : :
+VCCA_FPLL : V8 : power : : 2.5V : :
+TMS : V9 : input : : : 3A :
+GND : V10 : gnd : : : :
+VCC : V11 : power : : 1.1V : :
+GND : V12 : gnd : : : :
+VCC : V13 : power : : 1.1V : :
+GND : V14 : gnd : : : :
+VCC : V15 : power : : 1.1V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
+GND : V19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
+GND : V21 : gnd : : : :
+VCCPD5A : V22 : power : : 3.3V : 5A :
+HEX4[5] : V23 : output : 3.3-V LVTTL : : 5A : Y
+VCCPD5A : V24 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
+VCCIO6B_HPS : V26 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B :
+GND : W1 : gnd : : : :
+GND : W2 : gnd : : : :
+GND : W3 : gnd : : : :
+GND : W4 : gnd : : : :
+VCC : W5 : power : : 1.1V : :
+GND : W6 : gnd : : : :
+GND : W7 : gnd : : : :
+GND : W8 : gnd : : : :
+GND : W9 : gnd : : : :
+VCC : W10 : power : : 1.1V : :
+GND : W11 : gnd : : : :
+VCC : W12 : power : : 1.1V : :
+GND : W13 : gnd : : : :
+VCC : W14 : power : : 1.1V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
+GND : W18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
+HEX4[3] : W22 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : W23 : power : : 3.3V : 5A :
+HEX4[4] : W24 : output : 3.3-V LVTTL : : 5A : Y
+HEX4[6] : W25 : output : 3.3-V LVTTL : : 5B : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B :
+GND : W28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B :
+GND : Y1 : gnd : : : :
+GND : Y2 : gnd : : : :
+DNU : Y3 : : : : :
+DNU : Y4 : : : : :
+GND : Y5 : gnd : : : :
+VCC : Y6 : power : : 1.1V : :
+GND : Y7 : gnd : : : :
+GND : Y8 : gnd : : : :
+VCC : Y9 : power : : 1.1V : :
+GND : Y10 : gnd : : : :
+VCC : Y11 : power : : 1.1V : :
+GND : Y12 : gnd : : : :
+VCC : Y13 : power : : 1.1V : :
+GND : Y14 : gnd : : : :
+GND : Y15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
+GND : Y20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5A :
+VCCA_FPLL : Y22 : power : : 2.5V : :
+HEX4[1] : Y23 : output : 3.3-V LVTTL : : 5A : Y
+HEX4[2] : Y24 : output : 3.3-V LVTTL : : 5A : Y
+GND : Y25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B :
+GND : Y30 : gnd : : : :
diff --git a/part_2/ex6/output_files/ex6.sld b/part_2/ex6/output_files/ex6.sld
index 41a6030..f7d3ed7 100755
--- a/part_2/ex6/output_files/ex6.sld
+++ b/part_2/ex6/output_files/ex6.sld
@@ -1 +1 @@
-<sld_project_info/>
+<sld_project_info/>
diff --git a/part_2/ex6/output_files/ex6.sof b/part_2/ex6/output_files/ex6.sof
index 596fc0b..bf15168 100755
--- a/part_2/ex6/output_files/ex6.sof
+++ b/part_2/ex6/output_files/ex6.sof
Binary files differ
diff --git a/part_2/ex6/output_files/ex6.sta.rpt b/part_2/ex6/output_files/ex6.sta.rpt
index 48220e4..628adb0 100755
--- a/part_2/ex6/output_files/ex6.sta.rpt
+++ b/part_2/ex6/output_files/ex6.sta.rpt
@@ -1,839 +1,839 @@
-TimeQuest Timing Analyzer report for ex6
-Tue Nov 22 11:43:46 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. TimeQuest Timing Analyzer Summary
- 3. Parallel Compilation
- 4. SDC File List
- 5. Clocks
- 6. Slow 1100mV 85C Model Fmax Summary
- 7. Timing Closure Recommendations
- 8. Slow 1100mV 85C Model Setup Summary
- 9. Slow 1100mV 85C Model Hold Summary
- 10. Slow 1100mV 85C Model Recovery Summary
- 11. Slow 1100mV 85C Model Removal Summary
- 12. Slow 1100mV 85C Model Minimum Pulse Width Summary
- 13. Slow 1100mV 85C Model Metastability Summary
- 14. Slow 1100mV 0C Model Fmax Summary
- 15. Slow 1100mV 0C Model Setup Summary
- 16. Slow 1100mV 0C Model Hold Summary
- 17. Slow 1100mV 0C Model Recovery Summary
- 18. Slow 1100mV 0C Model Removal Summary
- 19. Slow 1100mV 0C Model Minimum Pulse Width Summary
- 20. Slow 1100mV 0C Model Metastability Summary
- 21. Fast 1100mV 85C Model Setup Summary
- 22. Fast 1100mV 85C Model Hold Summary
- 23. Fast 1100mV 85C Model Recovery Summary
- 24. Fast 1100mV 85C Model Removal Summary
- 25. Fast 1100mV 85C Model Minimum Pulse Width Summary
- 26. Fast 1100mV 85C Model Metastability Summary
- 27. Fast 1100mV 0C Model Setup Summary
- 28. Fast 1100mV 0C Model Hold Summary
- 29. Fast 1100mV 0C Model Recovery Summary
- 30. Fast 1100mV 0C Model Removal Summary
- 31. Fast 1100mV 0C Model Minimum Pulse Width Summary
- 32. Fast 1100mV 0C Model Metastability Summary
- 33. Multicorner Timing Analysis Summary
- 34. Board Trace Model Assignments
- 35. Input Transition Times
- 36. Signal Integrity Metrics (Slow 1100mv 0c Model)
- 37. Signal Integrity Metrics (Slow 1100mv 85c Model)
- 38. Signal Integrity Metrics (Fast 1100mv 0c Model)
- 39. Signal Integrity Metrics (Fast 1100mv 85c Model)
- 40. Setup Transfers
- 41. Hold Transfers
- 42. Report TCCS
- 43. Report RSKM
- 44. Unconstrained Paths Summary
- 45. Clock Status Summary
- 46. Unconstrained Input Ports
- 47. Unconstrained Output Ports
- 48. Unconstrained Input Ports
- 49. Unconstrained Output Ports
- 50. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary ;
-+-----------------------+---------------------------------------------------------+
-; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Timing Analyzer ; TimeQuest ;
-; Revision Name ; ex6 ;
-; Device Family ; Cyclone V ;
-; Device Name ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+---------------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.10 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 3.2% ;
-; Processor 3 ; 3.2% ;
-; Processor 4 ; 3.2% ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------+
-; SDC File List ;
-+---------------+--------+--------------------------+
-; SDC File Path ; Status ; Read at ;
-+---------------+--------+--------------------------+
-; ex6.sdc ; OK ; Tue Nov 22 11:43:43 2016 ;
-+---------------+--------+--------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks ;
-+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
-+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
-; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
-+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
-
-
-+--------------------------------------------------+
-; Slow 1100mV 85C Model Fmax Summary ;
-+------------+-----------------+------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+------------+------+
-; 216.31 MHz ; 216.31 MHz ; CLOCK_50 ; ;
-+------------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+-------------------------------------+
-; Slow 1100mV 85C Model Setup Summary ;
-+----------+--------+-----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+--------+-----------------+
-; CLOCK_50 ; 15.377 ; 0.000 ;
-+----------+--------+-----------------+
-
-
-+------------------------------------+
-; Slow 1100mV 85C Model Hold Summary ;
-+----------+-------+-----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+-----------------+
-; CLOCK_50 ; 0.388 ; 0.000 ;
-+----------+-------+-----------------+
-
-
-------------------------------------------
-; Slow 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
-+----------+-------+--------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+--------------------------------+
-; CLOCK_50 ; 8.900 ; 0.000 ;
-+----------+-------+--------------------------------+
-
-
------------------------------------------------
-; Slow 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------+
-; Slow 1100mV 0C Model Fmax Summary ;
-+------------+-----------------+------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+------------+------+
-; 212.13 MHz ; 212.13 MHz ; CLOCK_50 ; ;
-+------------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+------------------------------------+
-; Slow 1100mV 0C Model Setup Summary ;
-+----------+--------+----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+--------+----------------+
-; CLOCK_50 ; 15.286 ; 0.000 ;
-+----------+--------+----------------+
-
-
-+-----------------------------------+
-; Slow 1100mV 0C Model Hold Summary ;
-+----------+-------+----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+----------------+
-; CLOCK_50 ; 0.385 ; 0.000 ;
-+----------+-------+----------------+
-
-
------------------------------------------
-; Slow 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
-+----------+-------+-------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+-------------------------------+
-; CLOCK_50 ; 8.899 ; 0.000 ;
-+----------+-------+-------------------------------+
-
-
-----------------------------------------------
-; Slow 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+-------------------------------------+
-; Fast 1100mV 85C Model Setup Summary ;
-+----------+--------+-----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+--------+-----------------+
-; CLOCK_50 ; 17.068 ; 0.000 ;
-+----------+--------+-----------------+
-
-
-+------------------------------------+
-; Fast 1100mV 85C Model Hold Summary ;
-+----------+-------+-----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+-----------------+
-; CLOCK_50 ; 0.204 ; 0.000 ;
-+----------+-------+-----------------+
-
-
-------------------------------------------
-; Fast 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
-+----------+-------+--------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+--------------------------------+
-; CLOCK_50 ; 8.836 ; 0.000 ;
-+----------+-------+--------------------------------+
-
-
------------------------------------------------
-; Fast 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+------------------------------------+
-; Fast 1100mV 0C Model Setup Summary ;
-+----------+--------+----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+--------+----------------+
-; CLOCK_50 ; 17.237 ; 0.000 ;
-+----------+--------+----------------+
-
-
-+-----------------------------------+
-; Fast 1100mV 0C Model Hold Summary ;
-+----------+-------+----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+----------------+
-; CLOCK_50 ; 0.194 ; 0.000 ;
-+----------+-------+----------------+
-
-
------------------------------------------
-; Fast 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
-+----------+-------+-------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+-------------------------------+
-; CLOCK_50 ; 8.806 ; 0.000 ;
-+----------+-------+-------------------------------+
-
-
-----------------------------------------------
-; Fast 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+--------+-------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+--------+-------+----------+---------+---------------------+
-; Worst-case Slack ; 15.286 ; 0.194 ; N/A ; N/A ; 8.806 ;
-; CLOCK_50 ; 15.286 ; 0.194 ; N/A ; N/A ; 8.806 ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-; CLOCK_50 ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ;
-+------------------+--------+-------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+-------------------------------------------------------------+
-; Input Transition Times ;
-+----------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+----------+--------------+-----------------+-----------------+
-; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-+----------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+-------------------------------------------------------------------+
-; Setup Transfers ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 289 ; 0 ; 0 ; 0 ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-------------------------------------------------------------------+
-; Hold Transfers ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 289 ; 0 ; 0 ; 0 ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 1 ; 1 ;
-; Unconstrained Input Ports ; 2 ; 2 ;
-; Unconstrained Input Port Paths ; 32 ; 32 ;
-; Unconstrained Output Ports ; 35 ; 35 ;
-; Unconstrained Output Port Paths ; 483 ; 483 ;
-+---------------------------------+-------+------+
-
-
-+----------------------------------------------------------+
-; Clock Status Summary ;
-+------------------------+----------+------+---------------+
-; Target ; Clock ; Type ; Status ;
-+------------------------+----------+------+---------------+
-; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ;
-; tick_50000:tck|CLK_OUT ; ; Base ; Unconstrained ;
-+------------------------+----------+------+---------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime TimeQuest Timing Analyzer
- Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
- Info: Processing started: Tue Nov 22 11:43:41 2016
-Info: Command: quartus_sta ex6 -c ex6
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (332104): Reading SDC File: 'ex6.sdc'
-Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
- Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1100mV 85C Model
-Info (332146): Worst-case setup slack is 15.377
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 15.377 0.000 CLOCK_50
-Info (332146): Worst-case hold slack is 0.388
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.388 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is 8.900
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 8.900 0.000 CLOCK_50
-Info: Analyzing Slow 1100mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
- Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332146): Worst-case setup slack is 15.286
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 15.286 0.000 CLOCK_50
-Info (332146): Worst-case hold slack is 0.385
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.385 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is 8.899
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 8.899 0.000 CLOCK_50
-Info: Analyzing Fast 1100mV 85C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
- Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332146): Worst-case setup slack is 17.068
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 17.068 0.000 CLOCK_50
-Info (332146): Worst-case hold slack is 0.204
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.204 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is 8.836
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 8.836 0.000 CLOCK_50
-Info: Analyzing Fast 1100mV 0C Model
-Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
- Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332146): Worst-case setup slack is 17.237
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 17.237 0.000 CLOCK_50
-Info (332146): Worst-case hold slack is 0.194
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.194 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is 8.806
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 8.806 0.000 CLOCK_50
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 1209 megabytes
- Info: Processing ended: Tue Nov 22 11:43:46 2016
- Info: Elapsed time: 00:00:05
- Info: Total CPU time (on all processors): 00:00:05
-
-
+TimeQuest Timing Analyzer report for ex6
+Sun Dec 11 18:08:41 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. TimeQuest Timing Analyzer Summary
+ 3. Parallel Compilation
+ 4. SDC File List
+ 5. Clocks
+ 6. Slow 1100mV 85C Model Fmax Summary
+ 7. Timing Closure Recommendations
+ 8. Slow 1100mV 85C Model Setup Summary
+ 9. Slow 1100mV 85C Model Hold Summary
+ 10. Slow 1100mV 85C Model Recovery Summary
+ 11. Slow 1100mV 85C Model Removal Summary
+ 12. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 13. Slow 1100mV 85C Model Metastability Summary
+ 14. Slow 1100mV 0C Model Fmax Summary
+ 15. Slow 1100mV 0C Model Setup Summary
+ 16. Slow 1100mV 0C Model Hold Summary
+ 17. Slow 1100mV 0C Model Recovery Summary
+ 18. Slow 1100mV 0C Model Removal Summary
+ 19. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 20. Slow 1100mV 0C Model Metastability Summary
+ 21. Fast 1100mV 85C Model Setup Summary
+ 22. Fast 1100mV 85C Model Hold Summary
+ 23. Fast 1100mV 85C Model Recovery Summary
+ 24. Fast 1100mV 85C Model Removal Summary
+ 25. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 26. Fast 1100mV 85C Model Metastability Summary
+ 27. Fast 1100mV 0C Model Setup Summary
+ 28. Fast 1100mV 0C Model Hold Summary
+ 29. Fast 1100mV 0C Model Recovery Summary
+ 30. Fast 1100mV 0C Model Removal Summary
+ 31. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 32. Fast 1100mV 0C Model Metastability Summary
+ 33. Multicorner Timing Analysis Summary
+ 34. Board Trace Model Assignments
+ 35. Input Transition Times
+ 36. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 37. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 39. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 40. Setup Transfers
+ 41. Hold Transfers
+ 42. Report TCCS
+ 43. Report RSKM
+ 44. Unconstrained Paths Summary
+ 45. Clock Status Summary
+ 46. Unconstrained Input Ports
+ 47. Unconstrained Output Ports
+ 48. Unconstrained Input Ports
+ 49. Unconstrained Output Ports
+ 50. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary ;
++-----------------------+-----------------------------------------------------+
+; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Timing Analyzer ; TimeQuest ;
+; Revision Name ; ex6 ;
+; Device Family ; Cyclone V ;
+; Device Name ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Delay Model ; Combined ;
+; Rise/Fall Delays ; Enabled ;
++-----------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.12 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 3.9% ;
+; Processor 3 ; 3.9% ;
+; Processor 4 ; 3.8% ;
++----------------------------+-------------+
+
+
++---------------------------------------------------+
+; SDC File List ;
++---------------+--------+--------------------------+
+; SDC File Path ; Status ; Read at ;
++---------------+--------+--------------------------+
+; ex6.sdc ; OK ; Sun Dec 11 18:08:38 2016 ;
++---------------+--------+--------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks ;
++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+
+
++--------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary ;
++------------+-----------------+------------+------+
+; Fmax ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 210.08 MHz ; 210.08 MHz ; CLOCK_50 ; ;
++------------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------+
+; Slow 1100mV 85C Model Setup Summary ;
++----------+--------+-----------------+
+; Clock ; Slack ; End Point TNS ;
++----------+--------+-----------------+
+; CLOCK_50 ; 15.240 ; 0.000 ;
++----------+--------+-----------------+
+
+
++------------------------------------+
+; Slow 1100mV 85C Model Hold Summary ;
++----------+-------+-----------------+
+; Clock ; Slack ; End Point TNS ;
++----------+-------+-----------------+
+; CLOCK_50 ; 0.387 ; 0.000 ;
++----------+-------+-----------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
++----------+-------+--------------------------------+
+; Clock ; Slack ; End Point TNS ;
++----------+-------+--------------------------------+
+; CLOCK_50 ; 8.843 ; 0.000 ;
++----------+-------+--------------------------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary ;
++------------+-----------------+------------+------+
+; Fmax ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 204.08 MHz ; 204.08 MHz ; CLOCK_50 ; ;
++------------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------+
+; Slow 1100mV 0C Model Setup Summary ;
++----------+--------+----------------+
+; Clock ; Slack ; End Point TNS ;
++----------+--------+----------------+
+; CLOCK_50 ; 15.100 ; 0.000 ;
++----------+--------+----------------+
+
+
++-----------------------------------+
+; Slow 1100mV 0C Model Hold Summary ;
++----------+-------+----------------+
+; Clock ; Slack ; End Point TNS ;
++----------+-------+----------------+
+; CLOCK_50 ; 0.386 ; 0.000 ;
++----------+-------+----------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
++----------+-------+-------------------------------+
+; Clock ; Slack ; End Point TNS ;
++----------+-------+-------------------------------+
+; CLOCK_50 ; 8.841 ; 0.000 ;
++----------+-------+-------------------------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------+
+; Fast 1100mV 85C Model Setup Summary ;
++----------+--------+-----------------+
+; Clock ; Slack ; End Point TNS ;
++----------+--------+-----------------+
+; CLOCK_50 ; 17.054 ; 0.000 ;
++----------+--------+-----------------+
+
+
++------------------------------------+
+; Fast 1100mV 85C Model Hold Summary ;
++----------+-------+-----------------+
+; Clock ; Slack ; End Point TNS ;
++----------+-------+-----------------+
+; CLOCK_50 ; 0.204 ; 0.000 ;
++----------+-------+-----------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
++----------+-------+--------------------------------+
+; Clock ; Slack ; End Point TNS ;
++----------+-------+--------------------------------+
+; CLOCK_50 ; 8.791 ; 0.000 ;
++----------+-------+--------------------------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------+
+; Fast 1100mV 0C Model Setup Summary ;
++----------+--------+----------------+
+; Clock ; Slack ; End Point TNS ;
++----------+--------+----------------+
+; CLOCK_50 ; 17.214 ; 0.000 ;
++----------+--------+----------------+
+
+
++-----------------------------------+
+; Fast 1100mV 0C Model Hold Summary ;
++----------+-------+----------------+
+; Clock ; Slack ; End Point TNS ;
++----------+-------+----------------+
+; CLOCK_50 ; 0.194 ; 0.000 ;
++----------+-------+----------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
++----------+-------+-------------------------------+
+; Clock ; Slack ; End Point TNS ;
++----------+-------+-------------------------------+
+; CLOCK_50 ; 8.764 ; 0.000 ;
++----------+-------+-------------------------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary ;
++------------------+--------+-------+----------+---------+---------------------+
+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+--------+-------+----------+---------+---------------------+
+; Worst-case Slack ; 15.100 ; 0.194 ; N/A ; N/A ; 8.764 ;
+; CLOCK_50 ; 15.100 ; 0.194 ; N/A ; N/A ; 8.764 ;
+; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
+; CLOCK_50 ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ;
++------------------+--------+-------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times ;
++----------+--------------+-----------------+-----------------+
+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLOCK_50 ; CLOCK_50 ; 281 ; 0 ; 0 ; 0 ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLOCK_50 ; CLOCK_50 ; 281 ; 0 ; 0 ; 0 ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary ;
++---------------------------------+-------+------+
+; Property ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks ; 0 ; 0 ;
+; Unconstrained Clocks ; 1 ; 1 ;
+; Unconstrained Input Ports ; 2 ; 2 ;
+; Unconstrained Input Port Paths ; 32 ; 32 ;
+; Unconstrained Output Ports ; 35 ; 35 ;
+; Unconstrained Output Port Paths ; 483 ; 483 ;
++---------------------------------+-------+------+
+
+
++----------------------------------------------------------+
+; Clock Status Summary ;
++------------------------+----------+------+---------------+
+; Target ; Clock ; Type ; Status ;
++------------------------+----------+------+---------------+
+; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ;
+; tick_50000:tck|CLK_OUT ; ; Base ; Unconstrained ;
++------------------------+----------+------+---------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+ Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+ Info: Processing started: Sun Dec 11 18:08:37 2016
+Info: Command: quartus_sta ex6 -c ex6
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (332104): Reading SDC File: 'ex6.sdc'
+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
+ Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Info (332146): Worst-case setup slack is 15.240
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 15.240 0.000 CLOCK_50
+Info (332146): Worst-case hold slack is 0.387
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 0.387 0.000 CLOCK_50
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.843
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 8.843 0.000 CLOCK_50
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
+ Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 15.100
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 15.100 0.000 CLOCK_50
+Info (332146): Worst-case hold slack is 0.386
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 0.386 0.000 CLOCK_50
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.841
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 8.841 0.000 CLOCK_50
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
+ Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 17.054
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 17.054 0.000 CLOCK_50
+Info (332146): Worst-case hold slack is 0.204
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 0.204 0.000 CLOCK_50
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.791
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 8.791 0.000 CLOCK_50
+Info: Analyzing Fast 1100mV 0C Model
+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
+ Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 17.214
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 17.214 0.000 CLOCK_50
+Info (332146): Worst-case hold slack is 0.194
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 0.194 0.000 CLOCK_50
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.764
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 8.764 0.000 CLOCK_50
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
+ Info: Peak virtual memory: 1214 megabytes
+ Info: Processing ended: Sun Dec 11 18:08:41 2016
+ Info: Elapsed time: 00:00:04
+ Info: Total CPU time (on all processors): 00:00:05
+
+
diff --git a/part_2/ex6/output_files/ex6.sta.summary b/part_2/ex6/output_files/ex6.sta.summary
index d09b990..01d120f 100755
--- a/part_2/ex6/output_files/ex6.sta.summary
+++ b/part_2/ex6/output_files/ex6.sta.summary
@@ -1,53 +1,53 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : 15.377
-TNS : 0.000
-
-Type : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.388
-TNS : 0.000
-
-Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.900
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : 15.286
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.385
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.899
-TNS : 0.000
-
-Type : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : 17.068
-TNS : 0.000
-
-Type : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.204
-TNS : 0.000
-
-Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.836
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : 17.237
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.194
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.806
-TNS : 0.000
-
-------------------------------------------------------------
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : 15.240
+TNS : 0.000
+
+Type : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.387
+TNS : 0.000
+
+Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.843
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : 15.100
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.386
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.841
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : 17.054
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.204
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.791
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : 17.214
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.194
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.764
+TNS : 0.000
+
+------------------------------------------------------------
diff --git a/part_2/ex8/c5_pin_model_dump.txt b/part_2/ex8/c5_pin_model_dump.txt
index a895a64..31bb72c 100755
--- a/part_2/ex8/c5_pin_model_dump.txt
+++ b/part_2/ex8/c5_pin_model_dump.txt
@@ -1,118 +1,118 @@
-io_4iomodule_c5_index: 55gpio_index: 2
-io_4iomodule_c5_index: 54gpio_index: 465
-io_4iomodule_c5_index: 33gpio_index: 6
-io_4iomodule_c5_index: 51gpio_index: 461
-io_4iomodule_c5_index: 27gpio_index: 10
-io_4iomodule_c5_index: 57gpio_index: 457
-io_4iomodule_c5_index: 34gpio_index: 14
-io_4iomodule_c5_index: 28gpio_index: 453
-io_4iomodule_c5_index: 26gpio_index: 19
-io_4iomodule_c5_index: 47gpio_index: 449
-io_4iomodule_c5_index: 29gpio_index: 22
-io_4iomodule_c5_index: 3gpio_index: 445
-io_4iomodule_c5_index: 16gpio_index: 27
-io_4iomodule_c5_index: 6gpio_index: 441
-io_4iomodule_c5_index: 50gpio_index: 30
-io_4iomodule_c5_index: 35gpio_index: 437
-io_4iomodule_c5_index: 7gpio_index: 35
-io_4iomodule_c5_index: 53gpio_index: 433
-io_4iomodule_c5_index: 12gpio_index: 38
-io_4iomodule_c5_index: 1gpio_index: 429
-io_4iomodule_c5_index: 22gpio_index: 43
-io_4iomodule_c5_index: 8gpio_index: 425
-io_4iomodule_c5_index: 20gpio_index: 46
-io_4iomodule_c5_index: 30gpio_index: 421
-io_4iomodule_c5_index: 2gpio_index: 51
-io_4iomodule_c5_index: 31gpio_index: 417
-io_4iomodule_c5_index: 39gpio_index: 54
-io_4iomodule_c5_index: 18gpio_index: 413
-io_4iomodule_c5_index: 10gpio_index: 59
-io_4iomodule_c5_index: 42gpio_index: 409
-io_4iomodule_c5_index: 5gpio_index: 62
-io_4iomodule_c5_index: 24gpio_index: 405
-io_4iomodule_c5_index: 37gpio_index: 67
-io_4iomodule_c5_index: 13gpio_index: 401
-io_4iomodule_c5_index: 0gpio_index: 70
-io_4iomodule_c5_index: 44gpio_index: 397
-io_4iomodule_c5_index: 38gpio_index: 75
-io_4iomodule_c5_index: 52gpio_index: 393
-io_4iomodule_c5_index: 32gpio_index: 78
-io_4iomodule_c5_index: 56gpio_index: 389
-io_4iomodule_a_index: 13gpio_index: 385
-io_4iomodule_c5_index: 4gpio_index: 83
-io_4iomodule_c5_index: 23gpio_index: 86
-io_4iomodule_a_index: 15gpio_index: 381
-io_4iomodule_a_index: 8gpio_index: 377
-io_4iomodule_c5_index: 46gpio_index: 91
-io_4iomodule_a_index: 5gpio_index: 373
-io_4iomodule_a_index: 11gpio_index: 369
-io_4iomodule_c5_index: 41gpio_index: 94
-io_4iomodule_a_index: 3gpio_index: 365
-io_4iomodule_c5_index: 25gpio_index: 99
-io_4iomodule_a_index: 7gpio_index: 361
-io_4iomodule_c5_index: 9gpio_index: 102
-io_4iomodule_a_index: 0gpio_index: 357
-io_4iomodule_c5_index: 14gpio_index: 107
-io_4iomodule_a_index: 12gpio_index: 353
-io_4iomodule_c5_index: 45gpio_index: 110
-io_4iomodule_c5_index: 17gpio_index: 115
-io_4iomodule_a_index: 4gpio_index: 349
-io_4iomodule_c5_index: 36gpio_index: 118
-io_4iomodule_a_index: 10gpio_index: 345
-io_4iomodule_a_index: 16gpio_index: 341
-io_4iomodule_c5_index: 15gpio_index: 123
-io_4iomodule_a_index: 14gpio_index: 337
-io_4iomodule_c5_index: 43gpio_index: 126
-io_4iomodule_c5_index: 19gpio_index: 131
-io_4iomodule_a_index: 1gpio_index: 333
-io_4iomodule_c5_index: 59gpio_index: 134
-io_4iomodule_a_index: 2gpio_index: 329
-io_4iomodule_a_index: 9gpio_index: 325
-io_4iomodule_c5_index: 48gpio_index: 139
-io_4iomodule_a_index: 6gpio_index: 321
-io_4iomodule_a_index: 17gpio_index: 317
-io_4iomodule_c5_index: 40gpio_index: 142
-io_4iomodule_c5_index: 11gpio_index: 147
-io_4iomodule_c5_index: 58gpio_index: 150
-io_4iomodule_c5_index: 21gpio_index: 155
-io_4iomodule_c5_index: 49gpio_index: 158
-io_4iomodule_h_c5_index: 0gpio_index: 161
-io_4iomodule_h_c5_index: 6gpio_index: 165
-io_4iomodule_h_c5_index: 10gpio_index: 169
-io_4iomodule_h_c5_index: 3gpio_index: 173
-io_4iomodule_h_c5_index: 8gpio_index: 176
-io_4iomodule_h_c5_index: 11gpio_index: 180
-io_4iomodule_h_c5_index: 7gpio_index: 184
-io_4iomodule_h_c5_index: 5gpio_index: 188
-io_4iomodule_h_c5_index: 1gpio_index: 192
-io_4iomodule_h_c5_index: 2gpio_index: 196
-io_4iomodule_h_c5_index: 9gpio_index: 200
-io_4iomodule_h_c5_index: 4gpio_index: 204
-io_4iomodule_h_index: 15gpio_index: 208
-io_4iomodule_h_index: 1gpio_index: 212
-io_4iomodule_h_index: 3gpio_index: 216
-io_4iomodule_h_index: 2gpio_index: 220
-io_4iomodule_h_index: 11gpio_index: 224
-io_4iomodule_vref_h_index: 1gpio_index: 228
-io_4iomodule_h_index: 20gpio_index: 231
-io_4iomodule_h_index: 8gpio_index: 235
-io_4iomodule_h_index: 6gpio_index: 239
-io_4iomodule_h_index: 10gpio_index: 243
-io_4iomodule_h_index: 23gpio_index: 247
-io_4iomodule_h_index: 7gpio_index: 251
-io_4iomodule_h_index: 22gpio_index: 255
-io_4iomodule_h_index: 5gpio_index: 259
-io_4iomodule_h_index: 24gpio_index: 263
-io_4iomodule_h_index: 0gpio_index: 267
-io_4iomodule_h_index: 13gpio_index: 271
-io_4iomodule_h_index: 21gpio_index: 275
-io_4iomodule_h_index: 16gpio_index: 279
-io_4iomodule_vref_h_index: 0gpio_index: 283
-io_4iomodule_h_index: 12gpio_index: 286
-io_4iomodule_h_index: 4gpio_index: 290
-io_4iomodule_h_index: 19gpio_index: 294
-io_4iomodule_h_index: 18gpio_index: 298
-io_4iomodule_h_index: 17gpio_index: 302
-io_4iomodule_h_index: 25gpio_index: 306
-io_4iomodule_h_index: 14gpio_index: 310
-io_4iomodule_h_index: 9gpio_index: 314
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_2/ex8/db/.cmp.kpt b/part_2/ex8/db/.cmp.kpt
index 810fa45..0d971a6 100755
--- a/part_2/ex8/db/.cmp.kpt
+++ b/part_2/ex8/db/.cmp.kpt
Binary files differ
diff --git a/part_2/ex8/db/ex8.(0).cnf.cdb b/part_2/ex8/db/ex8.(0).cnf.cdb
index 5cdd1d4..384ecf4 100755
--- a/part_2/ex8/db/ex8.(0).cnf.cdb
+++ b/part_2/ex8/db/ex8.(0).cnf.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(0).cnf.hdb b/part_2/ex8/db/ex8.(0).cnf.hdb
index 1ffd6a6..ce68447 100755
--- a/part_2/ex8/db/ex8.(0).cnf.hdb
+++ b/part_2/ex8/db/ex8.(0).cnf.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(1).cnf.cdb b/part_2/ex8/db/ex8.(1).cnf.cdb
index 4aa533b..57cfdcd 100755
--- a/part_2/ex8/db/ex8.(1).cnf.cdb
+++ b/part_2/ex8/db/ex8.(1).cnf.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(1).cnf.hdb b/part_2/ex8/db/ex8.(1).cnf.hdb
index 592417b..5f35188 100755
--- a/part_2/ex8/db/ex8.(1).cnf.hdb
+++ b/part_2/ex8/db/ex8.(1).cnf.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(2).cnf.cdb b/part_2/ex8/db/ex8.(2).cnf.cdb
index fa21ea0..f243f2d 100755
--- a/part_2/ex8/db/ex8.(2).cnf.cdb
+++ b/part_2/ex8/db/ex8.(2).cnf.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(2).cnf.hdb b/part_2/ex8/db/ex8.(2).cnf.hdb
index 9b7ef11..5c5a19f 100755
--- a/part_2/ex8/db/ex8.(2).cnf.hdb
+++ b/part_2/ex8/db/ex8.(2).cnf.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(3).cnf.cdb b/part_2/ex8/db/ex8.(3).cnf.cdb
index 64a5fa0..6fc4545 100755
--- a/part_2/ex8/db/ex8.(3).cnf.cdb
+++ b/part_2/ex8/db/ex8.(3).cnf.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(3).cnf.hdb b/part_2/ex8/db/ex8.(3).cnf.hdb
index df64d5f..d9a96e9 100755
--- a/part_2/ex8/db/ex8.(3).cnf.hdb
+++ b/part_2/ex8/db/ex8.(3).cnf.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(4).cnf.cdb b/part_2/ex8/db/ex8.(4).cnf.cdb
index e6a0005..fb6e8f4 100755
--- a/part_2/ex8/db/ex8.(4).cnf.cdb
+++ b/part_2/ex8/db/ex8.(4).cnf.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(4).cnf.hdb b/part_2/ex8/db/ex8.(4).cnf.hdb
index 1aa2860..3e83407 100755
--- a/part_2/ex8/db/ex8.(4).cnf.hdb
+++ b/part_2/ex8/db/ex8.(4).cnf.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(5).cnf.cdb b/part_2/ex8/db/ex8.(5).cnf.cdb
index e02c97b..010f7bf 100755
--- a/part_2/ex8/db/ex8.(5).cnf.cdb
+++ b/part_2/ex8/db/ex8.(5).cnf.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(5).cnf.hdb b/part_2/ex8/db/ex8.(5).cnf.hdb
index 92790f4..57f6d11 100755
--- a/part_2/ex8/db/ex8.(5).cnf.hdb
+++ b/part_2/ex8/db/ex8.(5).cnf.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(6).cnf.cdb b/part_2/ex8/db/ex8.(6).cnf.cdb
index 2ef9091..5e29665 100755
--- a/part_2/ex8/db/ex8.(6).cnf.cdb
+++ b/part_2/ex8/db/ex8.(6).cnf.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(6).cnf.hdb b/part_2/ex8/db/ex8.(6).cnf.hdb
index af5dcd5..b5187a6 100755
--- a/part_2/ex8/db/ex8.(6).cnf.hdb
+++ b/part_2/ex8/db/ex8.(6).cnf.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(7).cnf.cdb b/part_2/ex8/db/ex8.(7).cnf.cdb
index 280aa80..96d06c4 100755
--- a/part_2/ex8/db/ex8.(7).cnf.cdb
+++ b/part_2/ex8/db/ex8.(7).cnf.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(7).cnf.hdb b/part_2/ex8/db/ex8.(7).cnf.hdb
index 42ab8b5..6472597 100755
--- a/part_2/ex8/db/ex8.(7).cnf.hdb
+++ b/part_2/ex8/db/ex8.(7).cnf.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(8).cnf.cdb b/part_2/ex8/db/ex8.(8).cnf.cdb
index 75ea495..21f3e91 100755
--- a/part_2/ex8/db/ex8.(8).cnf.cdb
+++ b/part_2/ex8/db/ex8.(8).cnf.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.(8).cnf.hdb b/part_2/ex8/db/ex8.(8).cnf.hdb
index 1df751e..19237fb 100755
--- a/part_2/ex8/db/ex8.(8).cnf.hdb
+++ b/part_2/ex8/db/ex8.(8).cnf.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.ae.hdb b/part_2/ex8/db/ex8.ae.hdb
deleted file mode 100755
index 58cff3f..0000000
--- a/part_2/ex8/db/ex8.ae.hdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/db/ex8.analyze_file.qmsg b/part_2/ex8/db/ex8.analyze_file.qmsg
deleted file mode 100755
index 34ad0f8..0000000
--- a/part_2/ex8/db/ex8.analyze_file.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479898397112 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 23 10:53:16 2016 " "Processing started: Wed Nov 23 10:53:16 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 --analyze_file=\"C:/New folder/ex8/verilog_files/formula_fsm.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 --analyze_file=\"C:/New folder/ex8/verilog_files/formula_fsm.v\"" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479898397114 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479898397537 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479898397537 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1 Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "827 " "Peak virtual memory: 827 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 23 10:53:26 2016 " "Processing ended: Wed Nov 23 10:53:26 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479898406239 ""}
diff --git a/part_2/ex8/db/ex8.asm.qmsg b/part_2/ex8/db/ex8.asm.qmsg
index 578d460..fc431f6 100755
--- a/part_2/ex8/db/ex8.asm.qmsg
+++ b/part_2/ex8/db/ex8.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481113330953 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481113330956 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:22:10 2016 " "Processing started: Wed Dec 07 12:22:10 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481113330956 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481113330956 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481113330957 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481113331992 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481113336870 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "891 " "Peak virtual memory: 891 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481113340323 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:22:20 2016 " "Processing ended: Wed Dec 07 12:22:20 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481113340323 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481113340323 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481113340323 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481113340323 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481487937303 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487937309 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:25:37 2016 " "Processing started: Sun Dec 11 20:25:37 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487937309 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481487937309 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481487937310 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481487937932 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481487942927 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "972 " "Peak virtual memory: 972 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487943285 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:25:43 2016 " "Processing ended: Sun Dec 11 20:25:43 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487943285 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487943285 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487943285 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481487943285 ""}
diff --git a/part_2/ex8/db/ex8.asm.rdb b/part_2/ex8/db/ex8.asm.rdb
index a03ad06..17c9d85 100755
--- a/part_2/ex8/db/ex8.asm.rdb
+++ b/part_2/ex8/db/ex8.asm.rdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.cbx.xml b/part_2/ex8/db/ex8.cbx.xml
index 721f2cf..4d64333 100755
--- a/part_2/ex8/db/ex8.cbx.xml
+++ b/part_2/ex8/db/ex8.cbx.xml
@@ -1,5 +1,5 @@
-<?xml version="1.0" ?>
-<LOG_ROOT>
- <PROJECT NAME="ex8">
- </PROJECT>
-</LOG_ROOT>
+<?xml version="1.0" ?>
+<LOG_ROOT>
+ <PROJECT NAME="ex8">
+ </PROJECT>
+</LOG_ROOT>
diff --git a/part_2/ex8/db/ex8.cmp.ammdb b/part_2/ex8/db/ex8.cmp.ammdb
deleted file mode 100755
index bafd7cb..0000000
--- a/part_2/ex8/db/ex8.cmp.ammdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/db/ex8.cmp.bpm b/part_2/ex8/db/ex8.cmp.bpm
index ba5a84b..029c54f 100755
--- a/part_2/ex8/db/ex8.cmp.bpm
+++ b/part_2/ex8/db/ex8.cmp.bpm
Binary files differ
diff --git a/part_2/ex8/db/ex8.cmp.cdb b/part_2/ex8/db/ex8.cmp.cdb
index 3efffc3..ae6fe71 100755
--- a/part_2/ex8/db/ex8.cmp.cdb
+++ b/part_2/ex8/db/ex8.cmp.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.cmp.hdb b/part_2/ex8/db/ex8.cmp.hdb
index e0384e8..88b87e4 100755
--- a/part_2/ex8/db/ex8.cmp.hdb
+++ b/part_2/ex8/db/ex8.cmp.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.cmp.idb b/part_2/ex8/db/ex8.cmp.idb
index 120b989..d39ad21 100755
--- a/part_2/ex8/db/ex8.cmp.idb
+++ b/part_2/ex8/db/ex8.cmp.idb
Binary files differ
diff --git a/part_2/ex8/db/ex8.cmp.logdb b/part_2/ex8/db/ex8.cmp.logdb
index b69cd55..ba5f5be 100755
--- a/part_2/ex8/db/ex8.cmp.logdb
+++ b/part_2/ex8/db/ex8.cmp.logdb
@@ -1,75 +1,75 @@
-v1
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
-IO_RULES_MATRIX,Total Pass,36;0;36;0;0;36;36;0;36;36;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,0;36;0;36;36;0;0;36;0;0;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,28,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
+v1
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000003;IO_000001;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000022;IO_000021;IO_000046;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000047;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
+IO_RULES_MATRIX,Total Pass,0;36;36;0;0;36;36;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;36;36;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,36;0;0;36;36;0;0;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;0;0;36,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,KEY[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,KEY[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_2/ex8/db/ex8.cmp.rdb b/part_2/ex8/db/ex8.cmp.rdb
index 2035ace..59651dc 100755
--- a/part_2/ex8/db/ex8.cmp.rdb
+++ b/part_2/ex8/db/ex8.cmp.rdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.cmp_merge.kpt b/part_2/ex8/db/ex8.cmp_merge.kpt
index 214a1dd..06da287 100755
--- a/part_2/ex8/db/ex8.cmp_merge.kpt
+++ b/part_2/ex8/db/ex8.cmp_merge.kpt
Binary files differ
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd
index 5b115d6..826025e 100755
--- a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd
Binary files differ
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd
index 3a7a497..8ebe269 100755
--- a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd
Binary files differ
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd
index aa473fa..8d531ee 100755
--- a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd
Binary files differ
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd
index dce4f6b..1e5e40e 100755
--- a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd
Binary files differ
diff --git a/part_2/ex8/db/ex8.db_info b/part_2/ex8/db/ex8.db_info
index 5713658..00e5756 100755
--- a/part_2/ex8/db/ex8.db_info
+++ b/part_2/ex8/db/ex8.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Version_Index = 402707200
-Creation_Time = Wed Dec 07 12:09:52 2016
+Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Version_Index = 419480576
+Creation_Time = Sun Dec 11 20:04:49 2016
diff --git a/part_2/ex8/db/ex8.fit.qmsg b/part_2/ex8/db/ex8.fit.qmsg
index 340170b..f77cc3c 100755
--- a/part_2/ex8/db/ex8.fit.qmsg
+++ b/part_2/ex8/db/ex8.fit.qmsg
@@ -1,45 +1,46 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481113289327 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481113289328 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex8 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481113289716 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481113289786 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481113289787 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481113290194 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481113290376 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481113300447 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481113300524 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481113300524 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113300525 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481113300528 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481113300528 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481113300529 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481113300529 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481113300530 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481113300530 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481113301210 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481113301211 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481113301211 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481113301214 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481113301215 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481113301215 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481113301218 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481113301219 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481113301219 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481113301254 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113301261 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481113306208 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481113306410 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113307023 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481113307561 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481113308475 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113308476 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481113309633 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" { } { { "loc" "" { Generic "H:/GitHub/digital_verilog_coursework/part_2/ex8/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481113314203 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481113314203 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481113316533 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481113316533 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Fitter routing operations ending: elapsed time is 00:00:03" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113316537 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.44 " "Total time spent on timing analysis during the Fitter is 0.44 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481113318295 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481113318336 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481113318765 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481113318765 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481113319187 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113321673 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481113321945 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481113322178 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 51 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 51 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2608 " "Peak virtual memory: 2608 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481113325553 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:22:05 2016 " "Processing ended: Wed Dec 07 12:22:05 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481113325553 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Elapsed time: 00:00:38" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481113325553 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:58 " "Total CPU time (on all processors): 00:00:58" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481113325553 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481113325553 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481487904510 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481487904510 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex8 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481487904517 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481487904547 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481487904547 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481487904907 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1481487904925 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481487904980 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481487915708 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481487915784 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481487915784 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487915784 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481487915787 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481487915788 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481487915789 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481487915789 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481487915789 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481487915790 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481487916319 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481487916319 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481487916320 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481487916323 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481487916323 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481487916323 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481487916328 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481487916328 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481487916328 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481487916364 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487916365 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481487920695 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481487920887 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487921404 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481487921908 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481487922990 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487922990 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481487923869 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" { } { { "loc" "" { Generic "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481487928353 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481487928353 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481487931749 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481487931749 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487931751 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.37 " "Total time spent on timing analysis during the Fitter is 0.37 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481487933164 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481487933195 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481487933545 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481487933545 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481487933894 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487935921 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481487936019 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481487936076 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 52 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 52 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2138 " "Peak virtual memory: 2138 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487936446 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:25:36 2016 " "Processing ended: Sun Dec 11 20:25:36 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487936446 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Elapsed time: 00:00:32" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487936446 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:57 " "Total CPU time (on all processors): 00:00:57" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487936446 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481487936446 ""}
diff --git a/part_2/ex8/db/ex8.hier_info b/part_2/ex8/db/ex8.hier_info
index 4fd5199..2996260 100755
--- a/part_2/ex8/db/ex8.hier_info
+++ b/part_2/ex8/db/ex8.hier_info
@@ -1,682 +1,679 @@
-|ex8
-CLOCK_50 => CLOCK_50.IN2
-KEY[0] => ~NO_FANOUT~
-KEY[1] => ~NO_FANOUT~
-KEY[2] => ~NO_FANOUT~
-KEY[3] => _.IN1
-HEX0[0] <= hex_to_7seg:SEG0.port0
-HEX0[1] <= hex_to_7seg:SEG0.port0
-HEX0[2] <= hex_to_7seg:SEG0.port0
-HEX0[3] <= hex_to_7seg:SEG0.port0
-HEX0[4] <= hex_to_7seg:SEG0.port0
-HEX0[5] <= hex_to_7seg:SEG0.port0
-HEX0[6] <= hex_to_7seg:SEG0.port0
-HEX1[0] <= hex_to_7seg:SEG1.port0
-HEX1[1] <= hex_to_7seg:SEG1.port0
-HEX1[2] <= hex_to_7seg:SEG1.port0
-HEX1[3] <= hex_to_7seg:SEG1.port0
-HEX1[4] <= hex_to_7seg:SEG1.port0
-HEX1[5] <= hex_to_7seg:SEG1.port0
-HEX1[6] <= hex_to_7seg:SEG1.port0
-HEX2[0] <= hex_to_7seg:SEG2.port0
-HEX2[1] <= hex_to_7seg:SEG2.port0
-HEX2[2] <= hex_to_7seg:SEG2.port0
-HEX2[3] <= hex_to_7seg:SEG2.port0
-HEX2[4] <= hex_to_7seg:SEG2.port0
-HEX2[5] <= hex_to_7seg:SEG2.port0
-HEX2[6] <= hex_to_7seg:SEG2.port0
-LEDR[0] <= formula_fsm:FSM.port6
-LEDR[1] <= formula_fsm:FSM.port6
-LEDR[2] <= formula_fsm:FSM.port6
-LEDR[3] <= formula_fsm:FSM.port6
-LEDR[4] <= formula_fsm:FSM.port6
-LEDR[5] <= formula_fsm:FSM.port6
-LEDR[6] <= formula_fsm:FSM.port6
-LEDR[7] <= formula_fsm:FSM.port6
-LEDR[8] <= formula_fsm:FSM.port6
-LEDR[9] <= formula_fsm:FSM.port6
-
-
-|ex8|tick_50000:TICK0
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => count[12].CLK
-CLOCK_IN => count[13].CLK
-CLOCK_IN => count[14].CLK
-CLOCK_IN => count[15].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|tick_2500:TICK1
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-en => CLK_OUT.OUTPUTSELECT
-en => count[0].ENA
-en => count[1].ENA
-en => count[2].ENA
-en => count[3].ENA
-en => count[4].ENA
-en => count[5].ENA
-en => count[6].ENA
-en => count[7].ENA
-en => count[8].ENA
-en => count[9].ENA
-en => count[10].ENA
-en => count[11].ENA
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|formula_fsm:FSM
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => count[9].CLK
-clk => count[10].CLK
-clk => count[11].CLK
-clk => ledr[0]~reg0.CLK
-clk => ledr[1]~reg0.CLK
-clk => ledr[2]~reg0.CLK
-clk => ledr[3]~reg0.CLK
-clk => ledr[4]~reg0.CLK
-clk => ledr[5]~reg0.CLK
-clk => ledr[6]~reg0.CLK
-clk => ledr[7]~reg0.CLK
-clk => ledr[8]~reg0.CLK
-clk => ledr[9]~reg0.CLK
-clk => state~3.DATAIN
-tick => ~NO_FANOUT~
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
-start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
-ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|LFSR:LFSR0
-CLK => COUNT[1]~reg0.CLK
-CLK => COUNT[2]~reg0.CLK
-CLK => COUNT[3]~reg0.CLK
-CLK => COUNT[4]~reg0.CLK
-CLK => COUNT[5]~reg0.CLK
-CLK => COUNT[6]~reg0.CLK
-CLK => COUNT[7]~reg0.CLK
-en => COUNT[1]~reg0.ENA
-en => COUNT[2]~reg0.ENA
-en => COUNT[3]~reg0.ENA
-en => COUNT[4]~reg0.ENA
-en => COUNT[5]~reg0.ENA
-en => COUNT[6]~reg0.ENA
-en => COUNT[7]~reg0.ENA
-COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|delay:DEL0
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => count[9].CLK
-clk => count[10].CLK
-clk => count[11].CLK
-clk => count[12].CLK
-clk => count[13].CLK
-clk => state~4.DATAIN
-N[0] => count.DATAB
-N[1] => count.DATAB
-N[2] => count.DATAB
-N[3] => count.DATAB
-N[4] => count.DATAB
-N[5] => count.DATAB
-N[6] => count.DATAB
-N[7] => ~NO_FANOUT~
-N[8] => ~NO_FANOUT~
-N[9] => ~NO_FANOUT~
-N[10] => ~NO_FANOUT~
-N[11] => ~NO_FANOUT~
-N[12] => ~NO_FANOUT~
-N[13] => ~NO_FANOUT~
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector17.IN3
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector14.IN2
-time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD
-B[0] => BCD_0[0].DATAIN
-B[1] => w35[0].IN1
-B[2] => w30[0].IN1
-B[3] => w26[0].IN1
-B[4] => w22[0].IN1
-B[5] => w18[0].IN1
-B[6] => w15[0].IN1
-B[7] => w12[0].IN1
-B[8] => w9[0].IN1
-B[9] => w7[0].IN1
-B[10] => w5[0].IN1
-B[11] => w3[0].IN1
-B[12] => w2[0].IN1
-B[13] => w1[0].IN1
-B[14] => w1[1].IN1
-B[15] => w1[2].IN1
-BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
-BCD_0[1] <= add3_ge5:A35.port1
-BCD_0[2] <= add3_ge5:A35.port1
-BCD_0[3] <= add3_ge5:A35.port1
-BCD_1[0] <= add3_ge5:A35.port1
-BCD_1[1] <= add3_ge5:A34.port1
-BCD_1[2] <= add3_ge5:A34.port1
-BCD_1[3] <= add3_ge5:A34.port1
-BCD_2[0] <= add3_ge5:A34.port1
-BCD_2[1] <= add3_ge5:A33.port1
-BCD_2[2] <= add3_ge5:A33.port1
-BCD_2[3] <= add3_ge5:A33.port1
-BCD_3[0] <= add3_ge5:A33.port1
-BCD_3[1] <= add3_ge5:A32.port1
-BCD_3[2] <= add3_ge5:A32.port1
-BCD_3[3] <= add3_ge5:A32.port1
-BCD_4[0] <= add3_ge5:A32.port1
-BCD_4[1] <= add3_ge5:A31.port1
-BCD_4[2] <= add3_ge5:A31.port1
-BCD_4[3] <= add3_ge5:A31.port1
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A1
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A2
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A3
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A4
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A5
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A6
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A7
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A8
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A9
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A10
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A11
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A12
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A13
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A14
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A15
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A16
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A17
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A18
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A19
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A20
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A21
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A22
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A23
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A24
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A25
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A26
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A27
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A28
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A29
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A30
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A31
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A32
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A33
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A34
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A35
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|hex_to_7seg:SEG0
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex8|hex_to_7seg:SEG1
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex8|hex_to_7seg:SEG2
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
+|ex8
+CLOCK_50 => CLOCK_50.IN2
+KEY[0] => ~NO_FANOUT~
+KEY[1] => ~NO_FANOUT~
+KEY[2] => ~NO_FANOUT~
+KEY[3] => _.IN1
+HEX0[0] << hex_to_7seg:SEG0.port0
+HEX0[1] << hex_to_7seg:SEG0.port0
+HEX0[2] << hex_to_7seg:SEG0.port0
+HEX0[3] << hex_to_7seg:SEG0.port0
+HEX0[4] << hex_to_7seg:SEG0.port0
+HEX0[5] << hex_to_7seg:SEG0.port0
+HEX0[6] << hex_to_7seg:SEG0.port0
+HEX1[0] << hex_to_7seg:SEG1.port0
+HEX1[1] << hex_to_7seg:SEG1.port0
+HEX1[2] << hex_to_7seg:SEG1.port0
+HEX1[3] << hex_to_7seg:SEG1.port0
+HEX1[4] << hex_to_7seg:SEG1.port0
+HEX1[5] << hex_to_7seg:SEG1.port0
+HEX1[6] << hex_to_7seg:SEG1.port0
+HEX2[0] << hex_to_7seg:SEG2.port0
+HEX2[1] << hex_to_7seg:SEG2.port0
+HEX2[2] << hex_to_7seg:SEG2.port0
+HEX2[3] << hex_to_7seg:SEG2.port0
+HEX2[4] << hex_to_7seg:SEG2.port0
+HEX2[5] << hex_to_7seg:SEG2.port0
+HEX2[6] << hex_to_7seg:SEG2.port0
+LEDR[0] << formula_fsm:FSM.port6
+LEDR[1] << formula_fsm:FSM.port6
+LEDR[2] << formula_fsm:FSM.port6
+LEDR[3] << formula_fsm:FSM.port6
+LEDR[4] << formula_fsm:FSM.port6
+LEDR[5] << formula_fsm:FSM.port6
+LEDR[6] << formula_fsm:FSM.port6
+LEDR[7] << formula_fsm:FSM.port6
+LEDR[8] << formula_fsm:FSM.port6
+LEDR[9] << formula_fsm:FSM.port6
+
+
+|ex8|tick_50000:TICK0
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => count[12].CLK
+CLOCK_IN => count[13].CLK
+CLOCK_IN => count[14].CLK
+CLOCK_IN => count[15].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|tick_2500:TICK1
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+en => CLK_OUT.OUTPUTSELECT
+en => count[0].ENA
+en => count[1].ENA
+en => count[2].ENA
+en => count[3].ENA
+en => count[4].ENA
+en => count[5].ENA
+en => count[6].ENA
+en => count[7].ENA
+en => count[8].ENA
+en => count[9].ENA
+en => count[10].ENA
+en => count[11].ENA
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|formula_fsm:FSM
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => ledr[0]~reg0.CLK
+clk => ledr[1]~reg0.CLK
+clk => ledr[2]~reg0.CLK
+clk => ledr[3]~reg0.CLK
+clk => ledr[4]~reg0.CLK
+clk => ledr[5]~reg0.CLK
+clk => ledr[6]~reg0.CLK
+clk => ledr[7]~reg0.CLK
+clk => ledr[8]~reg0.CLK
+clk => ledr[9]~reg0.CLK
+clk => state~3.DATAIN
+tick => ~NO_FANOUT~
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
+start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
+ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|LFSR:LFSR0
+CLK => COUNT[1]~reg0.CLK
+CLK => COUNT[2]~reg0.CLK
+CLK => COUNT[3]~reg0.CLK
+CLK => COUNT[4]~reg0.CLK
+CLK => COUNT[5]~reg0.CLK
+CLK => COUNT[6]~reg0.CLK
+CLK => COUNT[7]~reg0.CLK
+en => COUNT[1]~reg0.ENA
+en => COUNT[2]~reg0.ENA
+en => COUNT[3]~reg0.ENA
+en => COUNT[4]~reg0.ENA
+en => COUNT[5]~reg0.ENA
+en => COUNT[6]~reg0.ENA
+en => COUNT[7]~reg0.ENA
+COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|delay:DEL0
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => count[10].CLK
+clk => count[11].CLK
+clk => count[12].CLK
+clk => count[13].CLK
+clk => state~4.DATAIN
+N[0] => count.DATAB
+N[1] => count.DATAB
+N[2] => count.DATAB
+N[3] => count.DATAB
+N[4] => count.DATAB
+N[5] => count.DATAB
+N[6] => count.DATAB
+N[7] => ~NO_FANOUT~
+N[8] => ~NO_FANOUT~
+N[9] => ~NO_FANOUT~
+N[10] => ~NO_FANOUT~
+N[11] => ~NO_FANOUT~
+N[12] => ~NO_FANOUT~
+N[13] => ~NO_FANOUT~
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => Selector17.IN3
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => Selector14.IN2
+time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD
+B[0] => BCD_0[0].DATAIN
+B[1] => w35[0].IN1
+B[2] => w30[0].IN1
+B[3] => w26[0].IN1
+B[4] => w22[0].IN1
+B[5] => w18[0].IN1
+B[6] => w15[0].IN1
+B[7] => w12[0].IN1
+B[8] => w9[0].IN1
+B[9] => w7[0].IN1
+B[10] => w5[0].IN1
+B[11] => w3[0].IN1
+B[12] => w2[0].IN1
+B[13] => w1[0].IN1
+B[14] => w1[1].IN1
+B[15] => w1[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A35.port1
+BCD_0[2] <= add3_ge5:A35.port1
+BCD_0[3] <= add3_ge5:A35.port1
+BCD_1[0] <= add3_ge5:A35.port1
+BCD_1[1] <= add3_ge5:A34.port1
+BCD_1[2] <= add3_ge5:A34.port1
+BCD_1[3] <= add3_ge5:A34.port1
+BCD_2[0] <= add3_ge5:A34.port1
+BCD_2[1] <= add3_ge5:A33.port1
+BCD_2[2] <= add3_ge5:A33.port1
+BCD_2[3] <= add3_ge5:A33.port1
+BCD_3[0] <= add3_ge5:A33.port1
+BCD_3[1] <= add3_ge5:A32.port1
+BCD_3[2] <= add3_ge5:A32.port1
+BCD_3[3] <= add3_ge5:A32.port1
+BCD_4[0] <= add3_ge5:A32.port1
+BCD_4[1] <= add3_ge5:A31.port1
+BCD_4[2] <= add3_ge5:A31.port1
+BCD_4[3] <= add3_ge5:A31.port1
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A1
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A2
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A3
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A4
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A5
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A6
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A7
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A8
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A9
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A10
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A11
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A12
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A13
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A14
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A15
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A16
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A17
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A18
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A19
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A20
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A21
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A22
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A23
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A24
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A25
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A26
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A27
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A28
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A29
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A30
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A31
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A32
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A33
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A34
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A35
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex8|hex_to_7seg:SEG1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex8|hex_to_7seg:SEG2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_2/ex8/db/ex8.hif b/part_2/ex8/db/ex8.hif
index e8d44fd..4e2955c 100755
--- a/part_2/ex8/db/ex8.hif
+++ b/part_2/ex8/db/ex8.hif
Binary files differ
diff --git a/part_2/ex8/db/ex8.lpc.html b/part_2/ex8/db/ex8.lpc.html
index deaeb7d..ca68812 100755
--- a/part_2/ex8/db/ex8.lpc.html
+++ b/part_2/ex8/db/ex8.lpc.html
@@ -1,722 +1,722 @@
-<TABLE>
-<TR bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-<TR >
-<TD >SEG2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG1</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A35</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A34</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A33</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A32</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A31</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A30</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A29</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A28</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A27</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A26</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A25</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A24</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A23</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A22</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A21</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A20</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A19</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A18</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A17</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A16</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A15</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A14</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A13</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A12</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A11</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A10</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A9</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A8</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A7</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A6</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A5</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A4</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A3</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD</TD>
-<TD >16</TD>
-<TD >9</TD>
-<TD >0</TD>
-<TD >9</TD>
-<TD >20</TD>
-<TD >9</TD>
-<TD >9</TD>
-<TD >9</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >DEL0</TD>
-<TD >16</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >1</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >LFSR0</TD>
-<TD >2</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >FSM</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >12</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >TICK1</TD>
-<TD >2</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >TICK0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-</TABLE>
+<TABLE>
+<TR bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A35</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A34</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A33</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A32</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A31</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A30</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A29</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A28</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A27</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A26</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A25</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A24</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A23</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A22</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A21</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A20</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A19</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A18</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A17</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A16</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A15</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A14</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A13</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A12</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A11</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A10</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A9</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A4</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD</TD>
+<TD >16</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >9</TD>
+<TD >20</TD>
+<TD >9</TD>
+<TD >9</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >DEL0</TD>
+<TD >16</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >1</TD>
+<TD >7</TD>
+<TD >7</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >LFSR0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >FSM</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >TICK1</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >TICK0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_2/ex8/db/ex8.lpc.rdb b/part_2/ex8/db/ex8.lpc.rdb
index c015e5f..99d82ad 100755
--- a/part_2/ex8/db/ex8.lpc.rdb
+++ b/part_2/ex8/db/ex8.lpc.rdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.lpc.txt b/part_2/ex8/db/ex8.lpc.txt
index 1eae4bb..c5b5022 100755
--- a/part_2/ex8/db/ex8.lpc.txt
+++ b/part_2/ex8/db/ex8.lpc.txt
@@ -1,50 +1,50 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; SEG2 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; SEG1 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; SEG0 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A35 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A34 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A33 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A32 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A31 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A30 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A29 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A28 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A27 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A26 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A25 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A24 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A23 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A22 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A21 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A20 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A19 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A18 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A17 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A16 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A15 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A14 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A13 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A12 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A11 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A10 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A9 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A8 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A7 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A6 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A5 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A4 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A3 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A2 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A1 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD ; 16 ; 9 ; 0 ; 9 ; 20 ; 9 ; 9 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; DEL0 ; 16 ; 7 ; 0 ; 7 ; 1 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LFSR0 ; 2 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; FSM ; 4 ; 0 ; 1 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; TICK1 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; TICK0 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG2 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG1 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG0 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A35 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A34 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A33 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A32 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A31 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A30 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A29 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A28 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A27 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A26 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A25 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A24 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A23 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A22 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A21 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A20 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A19 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A18 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A17 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A16 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A15 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A14 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A13 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A12 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A11 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A10 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A9 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A8 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A7 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A6 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A5 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A4 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A3 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A2 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A1 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD ; 16 ; 9 ; 0 ; 9 ; 20 ; 9 ; 9 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; DEL0 ; 16 ; 7 ; 0 ; 7 ; 1 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; LFSR0 ; 2 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; FSM ; 4 ; 0 ; 1 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; TICK1 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; TICK0 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_2/ex8/db/ex8.map.ammdb b/part_2/ex8/db/ex8.map.ammdb
index 174eb00..a4afc79 100755
--- a/part_2/ex8/db/ex8.map.ammdb
+++ b/part_2/ex8/db/ex8.map.ammdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.map.bpm b/part_2/ex8/db/ex8.map.bpm
index 909f07b..fcdf140 100755
--- a/part_2/ex8/db/ex8.map.bpm
+++ b/part_2/ex8/db/ex8.map.bpm
Binary files differ
diff --git a/part_2/ex8/db/ex8.map.cdb b/part_2/ex8/db/ex8.map.cdb
index 1e91d4a..417692e 100755
--- a/part_2/ex8/db/ex8.map.cdb
+++ b/part_2/ex8/db/ex8.map.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.map.hdb b/part_2/ex8/db/ex8.map.hdb
index 68c0470..51bd19b 100755
--- a/part_2/ex8/db/ex8.map.hdb
+++ b/part_2/ex8/db/ex8.map.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.map.kpt b/part_2/ex8/db/ex8.map.kpt
index 6dedea4..bd5a8c6 100755
--- a/part_2/ex8/db/ex8.map.kpt
+++ b/part_2/ex8/db/ex8.map.kpt
Binary files differ
diff --git a/part_2/ex8/db/ex8.map.logdb b/part_2/ex8/db/ex8.map.logdb
index d45424f..626799f 100755
--- a/part_2/ex8/db/ex8.map.logdb
+++ b/part_2/ex8/db/ex8.map.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex8/db/ex8.map.qmsg b/part_2/ex8/db/ex8.map.qmsg
index 687e014..ff3a9e9 100755
--- a/part_2/ex8/db/ex8.map.qmsg
+++ b/part_2/ex8/db/ex8.map.qmsg
@@ -1,74 +1,74 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481113272271 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481113272275 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:21:11 2016 " "Processing started: Wed Dec 07 12:21:11 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481113272275 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113272275 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113272275 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481113272802 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481113272803 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" { } { { "verilog_files/tick_50000.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281367 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281367 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" { } { { "verilog_files/LFSR.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281372 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281372 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281377 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281377 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" { } { { "verilog_files/counter_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281382 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281382 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281399 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281399 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281399 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281400 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281400 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281400 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281400 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281400 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281402 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281403 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281403 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281403 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281403 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281403 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281408 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281408 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 38 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481113281419 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281420 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" { } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281425 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" { } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281425 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281425 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" { } { { "verilog_files/tick_2500.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281433 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281433 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" { } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281437 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281437 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex8 " "Elaborating entity \"ex8\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481113281536 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" { } { { "verilog_files/ex8.v" "TICK0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281573 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:TICK1 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:TICK1\"" { } { { "verilog_files/ex8.v" "TICK1" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281579 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" { } { { "verilog_files/ex8.v" "FSM" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 15 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281584 ""}
-{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 39 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481113281586 "|ex8|formula_fsm:FSM"}
-{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481113281586 "|ex8|formula_fsm:FSM"}
-{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281586 "|ex8|formula_fsm:FSM"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" { } { { "verilog_files/ex8.v" "LFSR0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 16 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281616 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" { } { { "verilog_files/ex8.v" "DEL0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 17 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281621 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" { } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481113281626 "|ex8|delay:comb_8"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" { } { { "verilog_files/ex8.v" "BCD" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281627 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_16.v" "A1" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281633 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "verilog_files/ex8.v" "SEG0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 19 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281642 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481113282426 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" { } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481113282524 "|ex8|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] GND " "Pin \"HEX2\[2\]\" is stuck at GND" { } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481113282524 "|ex8|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[6\] VCC " "Pin \"HEX2\[6\]\" is stuck at VCC" { } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481113282524 "|ex8|HEX2[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481113282524 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481113282602 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481113282980 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113283089 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481113283663 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113283663 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481113284041 "|ex8|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" { } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481113284041 "|ex8|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" { } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481113284041 "|ex8|KEY[2]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481113284041 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "184 " "Implemented 184 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481113284046 ""} { "Info" "ICUT_CUT_TM_OPINS" "31 " "Implemented 31 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481113284046 ""} { "Info" "ICUT_CUT_TM_LCELLS" "148 " "Implemented 148 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481113284046 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481113284046 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "895 " "Peak virtual memory: 895 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481113284242 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:21:24 2016 " "Processing ended: Wed Dec 07 12:21:24 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481113284242 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481113284242 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481113284242 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113284242 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481487894025 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487894033 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:24:53 2016 " "Processing started: Sun Dec 11 20:24:53 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487894033 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487894033 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487894033 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481487894281 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481487894281 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" { } { { "verilog_files/tick_50000.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902862 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902862 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/LFSR.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/LFSR.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" { } { { "verilog_files/LFSR.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902863 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902863 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902864 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902864 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" { } { { "verilog_files/counter_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902864 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902864 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902865 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902865 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 38 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481487902868 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902868 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902868 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" { } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902869 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" { } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902869 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902869 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" { } { { "verilog_files/tick_2500.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902870 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902870 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902870 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902870 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex8 " "Elaborating entity \"ex8\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481487902915 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" { } { { "verilog_files/ex8.v" "TICK0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902917 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:TICK1 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:TICK1\"" { } { { "verilog_files/ex8.v" "TICK1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902918 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" { } { { "verilog_files/ex8.v" "FSM" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 15 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902919 ""}
+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 39 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481487902920 "|ex8|formula_fsm:FSM"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481487902920 "|ex8|formula_fsm:FSM"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902921 "|ex8|formula_fsm:FSM"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" { } { { "verilog_files/ex8.v" "LFSR0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 16 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902928 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" { } { { "verilog_files/ex8.v" "DEL0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 17 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902929 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" { } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481487902929 "|ex8|delay:DEL0"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" { } { { "verilog_files/ex8.v" "BCD" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902930 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_16.v" "A1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902931 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "verilog_files/ex8.v" "SEG0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 19 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902939 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481487903244 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487903286 "|ex8|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] GND " "Pin \"HEX2\[2\]\" is stuck at GND" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487903286 "|ex8|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[6\] VCC " "Pin \"HEX2\[6\]\" is stuck at VCC" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487903286 "|ex8|HEX2[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481487903286 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481487903337 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481487903471 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487903489 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481487903556 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487903556 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487903594 "|ex8|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487903594 "|ex8|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487903594 "|ex8|KEY[2]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481487903594 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "178 " "Implemented 178 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481487903595 ""} { "Info" "ICUT_CUT_TM_OPINS" "31 " "Implemented 31 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481487903595 ""} { "Info" "ICUT_CUT_TM_LCELLS" "142 " "Implemented 142 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481487903595 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481487903595 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1054 " "Peak virtual memory: 1054 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487903602 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:25:03 2016 " "Processing ended: Sun Dec 11 20:25:03 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487903602 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487903602 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487903602 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487903602 ""}
diff --git a/part_2/ex8/db/ex8.map.rdb b/part_2/ex8/db/ex8.map.rdb
index 95ea26b..c16f519 100755
--- a/part_2/ex8/db/ex8.map.rdb
+++ b/part_2/ex8/db/ex8.map.rdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.map_bb.cdb b/part_2/ex8/db/ex8.map_bb.cdb
index 7530825..7d8d82c 100755
--- a/part_2/ex8/db/ex8.map_bb.cdb
+++ b/part_2/ex8/db/ex8.map_bb.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.map_bb.hdb b/part_2/ex8/db/ex8.map_bb.hdb
index f30501a..63b4a90 100755
--- a/part_2/ex8/db/ex8.map_bb.hdb
+++ b/part_2/ex8/db/ex8.map_bb.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.map_bb.logdb b/part_2/ex8/db/ex8.map_bb.logdb
index d45424f..626799f 100755
--- a/part_2/ex8/db/ex8.map_bb.logdb
+++ b/part_2/ex8/db/ex8.map_bb.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex8/db/ex8.pre_map.cdb b/part_2/ex8/db/ex8.pre_map.cdb
deleted file mode 100755
index 7e3e287..0000000
--- a/part_2/ex8/db/ex8.pre_map.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/db/ex8.pre_map.hdb b/part_2/ex8/db/ex8.pre_map.hdb
index caf9ee5..d0a76ab 100755
--- a/part_2/ex8/db/ex8.pre_map.hdb
+++ b/part_2/ex8/db/ex8.pre_map.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb b/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb
index 8818b3a..7a1d4da 100755
--- a/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb
+++ b/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.routing.rdb b/part_2/ex8/db/ex8.routing.rdb
index 6bc3097..f425873 100755
--- a/part_2/ex8/db/ex8.routing.rdb
+++ b/part_2/ex8/db/ex8.routing.rdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.rtlv.hdb b/part_2/ex8/db/ex8.rtlv.hdb
index ba43d17..724866d 100755
--- a/part_2/ex8/db/ex8.rtlv.hdb
+++ b/part_2/ex8/db/ex8.rtlv.hdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.rtlv_sg.cdb b/part_2/ex8/db/ex8.rtlv_sg.cdb
index 0ee2c0b..7d4f463 100755
--- a/part_2/ex8/db/ex8.rtlv_sg.cdb
+++ b/part_2/ex8/db/ex8.rtlv_sg.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.rtlv_sg_swap.cdb b/part_2/ex8/db/ex8.rtlv_sg_swap.cdb
index ed8d69c..e5bd34b 100755
--- a/part_2/ex8/db/ex8.rtlv_sg_swap.cdb
+++ b/part_2/ex8/db/ex8.rtlv_sg_swap.cdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.sld_design_entry.sci b/part_2/ex8/db/ex8.sld_design_entry.sci
index 92c1102..03eacdc 100755
--- a/part_2/ex8/db/ex8.sld_design_entry.sci
+++ b/part_2/ex8/db/ex8.sld_design_entry.sci
Binary files differ
diff --git a/part_2/ex8/db/ex8.sld_design_entry_dsc.sci b/part_2/ex8/db/ex8.sld_design_entry_dsc.sci
index 92c1102..03eacdc 100755
--- a/part_2/ex8/db/ex8.sld_design_entry_dsc.sci
+++ b/part_2/ex8/db/ex8.sld_design_entry_dsc.sci
Binary files differ
diff --git a/part_2/ex8/db/ex8.smart_action.txt b/part_2/ex8/db/ex8.smart_action.txt
index 437a63e..c8e8a13 100755
--- a/part_2/ex8/db/ex8.smart_action.txt
+++ b/part_2/ex8/db/ex8.smart_action.txt
@@ -1 +1 @@
-DONE
+DONE
diff --git a/part_2/ex8/db/ex8.smp_dump.txt b/part_2/ex8/db/ex8.smp_dump.txt
index 04f2111..05f4abe 100755
--- a/part_2/ex8/db/ex8.smp_dump.txt
+++ b/part_2/ex8/db/ex8.smp_dump.txt
@@ -1,13 +1,13 @@
-
-State Machine - |ex8|delay:DEL0|state
-Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE
-state.IDLE 0 0 0 0
-state.COUNTING 0 0 1 1
-state.TIME_OUT 0 1 0 1
-state.WAIT_LOW 1 0 0 1
-
-State Machine - |ex8|formula_fsm:FSM|state
-Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS
-state.WAIT_TRIGGER 0 0 0
-state.LIGHT_UP_LEDS 1 0 1
-state.WAIT_FOR_TIMEOUT 1 1 0
+
+State Machine - |ex8|delay:DEL0|state
+Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE
+state.IDLE 0 0 0 0
+state.COUNTING 0 0 1 1
+state.TIME_OUT 0 1 0 1
+state.WAIT_LOW 1 0 0 1
+
+State Machine - |ex8|formula_fsm:FSM|state
+Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS
+state.WAIT_TRIGGER 0 0 0
+state.LIGHT_UP_LEDS 1 0 1
+state.WAIT_FOR_TIMEOUT 1 1 0
diff --git a/part_2/ex8/db/ex8.sta.qmsg b/part_2/ex8/db/ex8.sta.qmsg
index b2592ab..2d589df 100755
--- a/part_2/ex8/db/ex8.sta.qmsg
+++ b/part_2/ex8/db/ex8.sta.qmsg
@@ -1,53 +1,53 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481113342093 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481113342095 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:22:21 2016 " "Processing started: Wed Dec 07 12:22:21 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481113342095 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113342095 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex8 -c ex8 " "Command: quartus_sta ex8 -c ex8" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113342095 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113342229 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113342955 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113342955 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343007 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343007 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343557 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343669 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343670 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481113343672 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481113343672 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481113343672 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343672 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343678 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343697 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113343698 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113343778 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481113343812 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343812 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.351 " "Worst-case setup slack is -3.351" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343838 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343838 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.351 -141.123 tick_50000:TICK0\|CLK_OUT " " -3.351 -141.123 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343838 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.370 -46.721 CLOCK_50 " " -2.370 -46.721 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343838 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.669 -1.669 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -1.669 -1.669 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343838 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343838 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.287 " "Worst-case hold slack is 0.287" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.287 0.000 tick_50000:TICK0\|CLK_OUT " " 0.287 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.375 0.000 CLOCK_50 " " 0.375 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.603 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.603 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343875 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343875 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343922 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343945 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.655 " "Worst-case minimum pulse width slack is -0.655" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.655 -20.255 CLOCK_50 " " -0.655 -20.255 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.394 -31.614 tick_50000:TICK0\|CLK_OUT " " -0.394 -31.614 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.435 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.435 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343968 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343968 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113344049 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113344098 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345078 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345313 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481113345356 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345356 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.267 " "Worst-case setup slack is -3.267" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345389 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345389 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.267 -138.732 tick_50000:TICK0\|CLK_OUT " " -3.267 -138.732 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345389 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.588 -48.020 CLOCK_50 " " -2.588 -48.020 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345389 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.583 -1.583 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -1.583 -1.583 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345389 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345389 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.289 " "Worst-case hold slack is 0.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345410 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345410 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.289 0.000 tick_50000:TICK0\|CLK_OUT " " 0.289 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345410 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.391 0.000 CLOCK_50 " " 0.391 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345410 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.463 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.463 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345410 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345410 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345427 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345446 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.714 " "Worst-case minimum pulse width slack is -0.714" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.714 -18.725 CLOCK_50 " " -0.714 -18.725 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.394 -30.708 tick_50000:TICK0\|CLK_OUT " " -0.394 -30.708 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.391 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.391 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345465 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345465 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113345570 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345953 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113346861 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113346985 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481113346987 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113346987 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.909 " "Worst-case setup slack is -1.909" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.909 -72.643 tick_50000:TICK0\|CLK_OUT " " -1.909 -72.643 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.138 -16.318 CLOCK_50 " " -1.138 -16.318 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.609 -0.609 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -0.609 -0.609 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347001 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347001 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.048 " "Worst-case hold slack is 0.048" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.048 0.000 tick_50000:TICK0\|CLK_OUT " " 0.048 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.181 0.000 CLOCK_50 " " 0.181 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.219 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.219 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347016 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347016 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347032 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347053 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.779 " "Worst-case minimum pulse width slack is -0.779" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347115 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347115 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.779 -14.378 CLOCK_50 " " -0.779 -14.378 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347115 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.014 -0.134 tick_50000:TICK0\|CLK_OUT " " -0.014 -0.134 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347115 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.468 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.468 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347115 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347115 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113347179 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347594 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481113347597 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347597 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.657 " "Worst-case setup slack is -1.657" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.657 -63.529 tick_50000:TICK0\|CLK_OUT " " -1.657 -63.529 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.092 -13.791 CLOCK_50 " " -1.092 -13.791 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.488 -0.488 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -0.488 -0.488 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347648 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347648 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.013 " "Worst-case hold slack is 0.013" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347667 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347667 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.013 0.000 tick_50000:TICK0\|CLK_OUT " " 0.013 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347667 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.128 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.128 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347667 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.171 0.000 CLOCK_50 " " 0.171 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347667 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347667 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347684 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347701 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.829 " "Worst-case minimum pulse width slack is -0.829" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.829 -17.064 CLOCK_50 " " -0.829 -17.064 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.025 0.000 tick_50000:TICK0\|CLK_OUT " " 0.025 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.460 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.460 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347717 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347717 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113350193 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113350195 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1209 " "Peak virtual memory: 1209 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481113350528 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:22:30 2016 " "Processing ended: Wed Dec 07 12:22:30 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481113350528 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481113350528 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481113350528 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113350528 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481487944063 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487944068 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:25:43 2016 " "Processing started: Sun Dec 11 20:25:43 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487944068 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944068 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex8 -c ex8 " "Command: quartus_sta ex8 -c ex8" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944069 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487944110 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944645 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944645 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944673 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944674 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945136 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945151 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945152 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487945153 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487945153 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487945153 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945153 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945154 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945159 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487945159 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487945164 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487945179 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945179 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.968 " "Worst-case setup slack is -2.968" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.968 -107.976 tick_50000:TICK0\|CLK_OUT " " -2.968 -107.976 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.534 -41.925 CLOCK_50 " " -2.534 -41.925 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.603 -1.603 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -1.603 -1.603 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945180 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945180 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.203 " "Worst-case hold slack is 0.203" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.203 0.000 tick_50000:TICK0\|CLK_OUT " " 0.203 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.384 0.000 CLOCK_50 " " 0.384 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.419 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.419 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945181 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945181 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945182 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945182 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.643 " "Worst-case minimum pulse width slack is -0.643" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.643 -16.740 CLOCK_50 " " -0.643 -16.740 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.394 -26.810 tick_50000:TICK0\|CLK_OUT " " -0.394 -26.810 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.357 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945183 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945183 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487945189 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945217 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945990 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946064 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487946069 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946069 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.963 " "Worst-case setup slack is -2.963" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946069 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946069 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.963 -106.734 tick_50000:TICK0\|CLK_OUT " " -2.963 -106.734 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946069 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.784 -42.820 CLOCK_50 " " -2.784 -42.820 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946069 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.493 -1.493 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -1.493 -1.493 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946069 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946069 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.233 " "Worst-case hold slack is 0.233" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946071 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946071 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.233 0.000 tick_50000:TICK0\|CLK_OUT " " 0.233 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946071 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.302 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.302 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946071 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.406 0.000 CLOCK_50 " " 0.406 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946071 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946071 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946072 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946072 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.717 " "Worst-case minimum pulse width slack is -0.717" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.717 -15.605 CLOCK_50 " " -0.717 -15.605 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.394 -26.816 tick_50000:TICK0\|CLK_OUT " " -0.394 -26.816 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.396 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.396 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946073 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946073 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487946079 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946211 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946858 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946927 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487946928 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946928 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.503 " "Worst-case setup slack is -1.503" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.503 -52.250 tick_50000:TICK0\|CLK_OUT " " -1.503 -52.250 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.304 -15.219 CLOCK_50 " " -1.304 -15.219 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.568 -0.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -0.568 -0.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946929 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946929 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.034 " "Worst-case hold slack is -0.034" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.034 -0.067 tick_50000:TICK0\|CLK_OUT " " -0.034 -0.067 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.057 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.057 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.185 0.000 CLOCK_50 " " 0.185 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946931 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946931 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946933 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946934 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.786 " "Worst-case minimum pulse width slack is -0.786" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.786 -12.110 CLOCK_50 " " -0.786 -12.110 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.065 0.000 tick_50000:TICK0\|CLK_OUT " " 0.065 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.369 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.369 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946934 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946934 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487946941 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947080 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487947081 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947081 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.311 " "Worst-case setup slack is -1.311" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.311 -45.679 tick_50000:TICK0\|CLK_OUT " " -1.311 -45.679 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.229 -13.104 CLOCK_50 " " -1.229 -13.104 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.445 -0.445 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -0.445 -0.445 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947082 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947082 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.034 " "Worst-case hold slack is -0.034" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947083 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947083 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.034 -0.067 tick_50000:TICK0\|CLK_OUT " " -0.034 -0.067 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947083 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.014 -0.014 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -0.014 -0.014 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947083 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 CLOCK_50 " " 0.177 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947083 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947083 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947084 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947085 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.844 " "Worst-case minimum pulse width slack is -0.844" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947085 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947085 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.844 -14.423 CLOCK_50 " " -0.844 -14.423 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947085 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.081 0.000 tick_50000:TICK0\|CLK_OUT " " 0.081 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947085 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.396 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.396 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947085 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947085 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487948344 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487948344 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1214 " "Peak virtual memory: 1214 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487948372 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:25:48 2016 " "Processing ended: Sun Dec 11 20:25:48 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487948372 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487948372 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487948372 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487948372 ""}
diff --git a/part_2/ex8/db/ex8.sta.rdb b/part_2/ex8/db/ex8.sta.rdb
index 97d602f..259c48b 100755
--- a/part_2/ex8/db/ex8.sta.rdb
+++ b/part_2/ex8/db/ex8.sta.rdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb
index e20c7c2..eaaa80a 100755
--- a/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb
+++ b/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb
Binary files differ
diff --git a/part_2/ex8/db/ex8.tis_db_list.ddb b/part_2/ex8/db/ex8.tis_db_list.ddb
index 88225e8..2df45d7 100755
--- a/part_2/ex8/db/ex8.tis_db_list.ddb
+++ b/part_2/ex8/db/ex8.tis_db_list.ddb
Binary files differ
diff --git a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb
index 3485514..6f4c35a 100755
--- a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb
+++ b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb
Binary files differ
diff --git a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb
index e7e3c75..06bb7a7 100755
--- a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb
+++ b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb
Binary files differ
diff --git a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb
index 4c6cdc1..77e6657 100755
--- a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb
+++ b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb
Binary files differ
diff --git a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb
index 0f83314..e4e6026 100755
--- a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb
+++ b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb
Binary files differ
diff --git a/part_2/ex8/db/ex8.tmw_info b/part_2/ex8/db/ex8.tmw_info
index 9b49b2f..7c14f97 100755
--- a/part_2/ex8/db/ex8.tmw_info
+++ b/part_2/ex8/db/ex8.tmw_info
@@ -1,6 +1,6 @@
-start_full_compilation:s:00:01:22
-start_analysis_synthesis:s:00:00:17-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:43-start_full_compilation
-start_assembler:s:00:00:11-start_full_compilation
-start_timing_analyzer:s:00:00:11-start_full_compilation
+start_full_compilation:s:00:00:55
+start_analysis_synthesis:s:00:00:10-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:33-start_full_compilation
+start_assembler:s:00:00:07-start_full_compilation
+start_timing_analyzer:s:00:00:05-start_full_compilation
diff --git a/part_2/ex8/db/ex8.vpr.ammdb b/part_2/ex8/db/ex8.vpr.ammdb
index 7636fff..1232dc3 100755
--- a/part_2/ex8/db/ex8.vpr.ammdb
+++ b/part_2/ex8/db/ex8.vpr.ammdb
Binary files differ
diff --git a/part_2/ex8/db/ex8_partition_pins.json b/part_2/ex8/db/ex8_partition_pins.json
index ad28bfb..677a906 100755
--- a/part_2/ex8/db/ex8_partition_pins.json
+++ b/part_2/ex8/db/ex8_partition_pins.json
@@ -1,129 +1,129 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "HEX0[0]",
- "strict" : false
- },
- {
- "name" : "HEX0[1]",
- "strict" : false
- },
- {
- "name" : "HEX0[2]",
- "strict" : false
- },
- {
- "name" : "HEX0[3]",
- "strict" : false
- },
- {
- "name" : "HEX0[4]",
- "strict" : false
- },
- {
- "name" : "HEX0[5]",
- "strict" : false
- },
- {
- "name" : "HEX0[6]",
- "strict" : false
- },
- {
- "name" : "HEX1[0]",
- "strict" : false
- },
- {
- "name" : "HEX1[1]",
- "strict" : false
- },
- {
- "name" : "HEX1[2]",
- "strict" : false
- },
- {
- "name" : "HEX1[3]",
- "strict" : false
- },
- {
- "name" : "HEX1[4]",
- "strict" : false
- },
- {
- "name" : "HEX1[5]",
- "strict" : false
- },
- {
- "name" : "HEX1[6]",
- "strict" : false
- },
- {
- "name" : "HEX2[0]",
- "strict" : false
- },
- {
- "name" : "HEX2[3]",
- "strict" : false
- },
- {
- "name" : "HEX2[4]",
- "strict" : false
- },
- {
- "name" : "HEX2[5]",
- "strict" : false
- },
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "LEDR[1]",
- "strict" : false
- },
- {
- "name" : "LEDR[2]",
- "strict" : false
- },
- {
- "name" : "LEDR[3]",
- "strict" : false
- },
- {
- "name" : "LEDR[4]",
- "strict" : false
- },
- {
- "name" : "LEDR[5]",
- "strict" : false
- },
- {
- "name" : "LEDR[6]",
- "strict" : false
- },
- {
- "name" : "LEDR[7]",
- "strict" : false
- },
- {
- "name" : "LEDR[8]",
- "strict" : false
- },
- {
- "name" : "LEDR[9]",
- "strict" : false
- },
- {
- "name" : "KEY[3]",
- "strict" : false
- },
- {
- "name" : "CLOCK_50",
- "strict" : false
- }
- ]
- }
- ]
+{
+ "partitions" : [
+ {
+ "name" : "Top",
+ "pins" : [
+ {
+ "name" : "HEX0[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[5]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[0]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[1]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[2]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[3]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[4]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[5]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[6]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[7]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[8]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[9]",
+ "strict" : false
+ },
+ {
+ "name" : "KEY[3]",
+ "strict" : false
+ },
+ {
+ "name" : "CLOCK_50",
+ "strict" : false
+ }
+ ]
+ }
+ ]
} \ No newline at end of file
diff --git a/part_2/ex8/db/prev_cmp_ex8.qmsg b/part_2/ex8/db/prev_cmp_ex8.qmsg
index 7ea8680..08aed7e 100755
--- a/part_2/ex8/db/prev_cmp_ex8.qmsg
+++ b/part_2/ex8/db/prev_cmp_ex8.qmsg
@@ -1,59 +1,189 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481113236662 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481113236665 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:20:36 2016 " "Processing started: Wed Dec 07 12:20:36 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481113236665 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113236665 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113236665 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481113237277 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481113237277 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" { } { { "verilog_files/tick_50000.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245775 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245775 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" { } { { "verilog_files/LFSR.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245781 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245781 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245785 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245785 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" { } { { "verilog_files/counter_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245790 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245790 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245795 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245795 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245795 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245795 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245796 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245796 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245796 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245796 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245799 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245799 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245799 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245800 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245800 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245800 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245800 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245800 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245801 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245801 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245801 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245801 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245801 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245801 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245806 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245806 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(36) " "Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 36 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481113245821 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245822 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245822 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" { } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245828 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" { } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245828 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245828 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" { } { { "verilog_files/tick_2500.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245833 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245833 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" { } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245837 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245837 ""}
-{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "count formula_fsm.v(42) " "Verilog HDL error at formula_fsm.v(42): object \"count\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 42 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1481113245838 ""}
-{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "count formula_fsm.v(45) " "Verilog HDL error at formula_fsm.v(45): object \"count\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 45 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1481113245838 ""}
-{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "count formula_fsm.v(49) " "Verilog HDL error at formula_fsm.v(49): object \"count\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 49 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1481113245839 ""}
-{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "count formula_fsm.v(52) " "Verilog HDL error at formula_fsm.v(52): object \"count\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 52 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1481113245839 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245876 ""}
-{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 4 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 4 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "830 " "Peak virtual memory: 830 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481113246053 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Dec 07 12:20:46 2016 " "Processing ended: Wed Dec 07 12:20:46 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481113246053 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481113246053 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481113246053 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113246053 ""}
-{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 6 s 1 " "Quartus Prime Full Compilation was unsuccessful. 6 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113247275 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481487062604 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487062611 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:11:02 2016 " "Processing started: Sun Dec 11 20:11:02 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487062611 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487062611 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487062612 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481487062858 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481487062858 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" { } { { "verilog_files/tick_50000.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071574 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071574 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/LFSR.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/LFSR.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" { } { { "verilog_files/LFSR.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071575 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071575 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071575 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071575 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" { } { { "verilog_files/counter_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071576 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071576 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071579 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071579 ""}
+{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "8 formula_fsm.v(47) " "Verilog HDL Expression warning at formula_fsm.v(47): truncated literal to match 8 bits" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 47 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1481487071579 ""}
+{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "8 formula_fsm.v(54) " "Verilog HDL Expression warning at formula_fsm.v(54): truncated literal to match 8 bits" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 54 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1481487071579 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 38 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481487071579 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071580 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071580 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" { } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071580 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" { } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071580 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071580 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" { } { { "verilog_files/tick_2500.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071581 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071581 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071582 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071582 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex8 " "Elaborating entity \"ex8\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481487071635 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" { } { { "verilog_files/ex8.v" "TICK0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071637 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:TICK1 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:TICK1\"" { } { { "verilog_files/ex8.v" "TICK1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071638 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" { } { { "verilog_files/ex8.v" "FSM" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 15 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071639 ""}
+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 39 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481487071640 "|ex8|formula_fsm:FSM"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481487071640 "|ex8|formula_fsm:FSM"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071641 "|ex8|formula_fsm:FSM"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" { } { { "verilog_files/ex8.v" "LFSR0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 16 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071648 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" { } { { "verilog_files/ex8.v" "DEL0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 17 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071649 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" { } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481487071650 "|ex8|delay:DEL0"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" { } { { "verilog_files/ex8.v" "BCD" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071650 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_16.v" "A1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071651 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "verilog_files/ex8.v" "SEG0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 19 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071659 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481487071976 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487072030 "|ex8|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] GND " "Pin \"HEX2\[2\]\" is stuck at GND" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487072030 "|ex8|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[6\] VCC " "Pin \"HEX2\[6\]\" is stuck at VCC" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487072030 "|ex8|HEX2[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481487072030 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481487072086 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481487072222 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487072241 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481487072309 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487072309 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487072347 "|ex8|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487072347 "|ex8|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" { } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487072347 "|ex8|KEY[2]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481487072347 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "176 " "Implemented 176 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481487072348 ""} { "Info" "ICUT_CUT_TM_OPINS" "31 " "Implemented 31 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481487072348 ""} { "Info" "ICUT_CUT_TM_LCELLS" "140 " "Implemented 140 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481487072348 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481487072348 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1050 " "Peak virtual memory: 1050 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487072355 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:11:12 2016 " "Processing ended: Sun Dec 11 20:11:12 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487072355 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487072355 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487072355 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487072355 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1481487073099 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487073104 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:11:12 2016 " "Processing started: Sun Dec 11 20:11:12 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487073104 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1481487073104 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1481487073105 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1481487073150 ""}
+{ "Info" "0" "" "Project = ex8" { } { } 0 0 "Project = ex8" 0 0 "Fitter" 0 0 1481487073151 ""}
+{ "Info" "0" "" "Revision = ex8" { } { } 0 0 "Revision = ex8" 0 0 "Fitter" 0 0 1481487073151 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481487073247 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481487073247 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex8 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481487073251 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481487073277 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481487073277 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481487073638 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1481487073655 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481487073712 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481487084449 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481487084525 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481487084525 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487084525 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481487084528 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481487084528 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481487084529 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481487084530 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481487084530 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481487084530 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481487085060 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481487085061 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481487085061 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481487085064 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481487085064 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481487085065 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481487085069 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481487085070 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481487085070 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481487085106 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487085108 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481487089399 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481487089589 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487090058 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481487090520 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481487091660 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487091660 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481487092540 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" { } { { "loc" "" { Generic "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481487097058 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481487097058 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481487098971 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481487098971 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487098973 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.36 " "Total time spent on timing analysis during the Fitter is 0.36 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481487100387 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481487100421 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481487100765 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481487100765 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481487101119 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487103102 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481487103203 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481487103258 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 52 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 52 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2132 " "Peak virtual memory: 2132 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487103623 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:11:43 2016 " "Processing ended: Sun Dec 11 20:11:43 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487103623 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Elapsed time: 00:00:31" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487103623 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:51 " "Total CPU time (on all processors): 00:00:51" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487103623 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481487103623 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1481487104690 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487104697 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:11:44 2016 " "Processing started: Sun Dec 11 20:11:44 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487104697 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481487104697 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481487104697 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481487105322 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481487110230 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "977 " "Peak virtual memory: 977 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487110573 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:11:50 2016 " "Processing ended: Sun Dec 11 20:11:50 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487110573 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487110573 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487110573 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481487110573 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1481487110702 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1481487111307 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487111312 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:11:51 2016 " "Processing started: Sun Dec 11 20:11:51 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487111312 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111312 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex8 -c ex8 " "Command: quartus_sta ex8 -c ex8" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111312 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487111354 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111864 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111864 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111891 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111891 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112389 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112406 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112406 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487112408 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487112408 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487112408 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112408 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112409 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112414 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487112415 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487112419 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487112433 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112433 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.776 " "Worst-case setup slack is -2.776" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.776 -103.897 tick_50000:TICK0\|CLK_OUT " " -2.776 -103.897 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.523 -37.773 CLOCK_50 " " -2.523 -37.773 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.483 -1.483 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -1.483 -1.483 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112434 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112434 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.279 " "Worst-case hold slack is 0.279" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.279 0.000 tick_50000:TICK0\|CLK_OUT " " 0.279 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.382 0.000 CLOCK_50 " " 0.382 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.405 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.405 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112436 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112436 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112436 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112437 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.630 " "Worst-case minimum pulse width slack is -0.630" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.630 -15.485 CLOCK_50 " " -0.630 -15.485 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.394 -26.353 tick_50000:TICK0\|CLK_OUT " " -0.394 -26.353 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.450 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.450 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112437 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112437 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487112444 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112471 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113253 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113316 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487113320 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113320 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.772 " "Worst-case setup slack is -2.772" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113321 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113321 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.772 -102.400 tick_50000:TICK0\|CLK_OUT " " -2.772 -102.400 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113321 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.763 -38.066 CLOCK_50 " " -2.763 -38.066 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113321 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.393 -1.393 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -1.393 -1.393 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113321 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113321 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.281 " "Worst-case hold slack is 0.281" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.281 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.281 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.281 0.000 tick_50000:TICK0\|CLK_OUT " " 0.281 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.404 0.000 CLOCK_50 " " 0.404 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113322 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113322 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113323 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113323 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.709 " "Worst-case minimum pulse width slack is -0.709" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113324 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113324 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.709 -14.425 CLOCK_50 " " -0.709 -14.425 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113324 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.394 -26.143 tick_50000:TICK0\|CLK_OUT " " -0.394 -26.143 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113324 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.456 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.456 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113324 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113324 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487113330 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113471 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114155 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114222 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487114224 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114224 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.423 " "Worst-case setup slack is -1.423" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.423 -50.727 tick_50000:TICK0\|CLK_OUT " " -1.423 -50.727 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.177 -13.311 CLOCK_50 " " -1.177 -13.311 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.511 -0.511 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -0.511 -0.511 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114224 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114224 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.068 " "Worst-case hold slack is 0.068" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.068 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.068 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.076 0.000 tick_50000:TICK0\|CLK_OUT " " 0.076 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.184 0.000 CLOCK_50 " " 0.184 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114226 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114226 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114227 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114228 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.786 " "Worst-case minimum pulse width slack is -0.786" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.786 -11.293 CLOCK_50 " " -0.786 -11.293 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.059 0.000 tick_50000:TICK0\|CLK_OUT " " 0.059 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.431 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.431 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114229 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114229 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487114235 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114378 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487114379 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114379 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.279 " "Worst-case setup slack is -1.279" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.279 -44.144 tick_50000:TICK0\|CLK_OUT " " -1.279 -44.144 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.143 -11.225 CLOCK_50 " " -1.143 -11.225 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -0.396 -0.396 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114380 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114380 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.000 " "Worst-case hold slack is 0.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.000 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.000 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.045 0.000 tick_50000:TICK0\|CLK_OUT " " 0.045 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.176 0.000 CLOCK_50 " " 0.176 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114381 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114381 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114382 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114383 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.844 " "Worst-case minimum pulse width slack is -0.844" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114383 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114383 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.844 -13.411 CLOCK_50 " " -0.844 -13.411 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114383 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.077 0.000 tick_50000:TICK0\|CLK_OUT " " 0.077 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114383 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.444 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.444 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114383 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114383 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487115666 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487115667 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1217 " "Peak virtual memory: 1217 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487115694 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:11:55 2016 " "Processing ended: Sun Dec 11 20:11:55 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487115694 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487115694 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487115694 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487115694 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 74 s " "Quartus Prime Full Compilation was successful. 0 errors, 74 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487115852 ""}
diff --git a/part_2/ex8/ex8.qsf b/part_2/ex8/ex8.qsf
index b806fc9..9d2c16a 100755
--- a/part_2/ex8/ex8.qsf
+++ b/part_2/ex8/ex8.qsf
@@ -252,7 +252,7 @@ set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY ex8
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:21:41 NOVEMBER 23, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
diff --git a/part_2/ex8/ex8.qws b/part_2/ex8/ex8.qws
index b770ba8..b5716f0 100755
--- a/part_2/ex8/ex8.qws
+++ b/part_2/ex8/ex8.qws
Binary files differ
diff --git a/part_2/ex8/ex8_assignment_defaults.qdf b/part_2/ex8/ex8_assignment_defaults.qdf
new file mode 100644
index 0000000..3dade63
--- /dev/null
+++ b/part_2/ex8/ex8_assignment_defaults.qdf
@@ -0,0 +1,795 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2016 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Intel and sold by Intel or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+# Date created = 20:04:49 December 11, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+# automatically by the Quartus Prime software and is used
+# to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL -value OFF
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
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+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.db_info b/part_2/ex8/incremental_db/compiled_partitions/ex8.db_info
index 2914929..00e5756 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.db_info
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Version_Index = 402707200
-Creation_Time = Wed Nov 23 10:30:54 2016
+Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Version_Index = 419480576
+Creation_Time = Sun Dec 11 20:04:49 2016
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdb
index ba81eb9..93bee56 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdb
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdb
index ac6620f..e0f1bca 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdb
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdb
index a677ce0..88f54a4 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdb
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdb
index dfc8697..7f5d0fc 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdb
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdb
index 4335c17..d51f8f2 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdb
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb
index d45424f..626799f 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdb
index 6d87d95..9c7dd08 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdb
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdb
index d523670..8e88130 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdb
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpi b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpi
index dbcb729..a8f9221 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpi
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpi
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdb
index 22dbf8c..f39023f 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdb
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdb
index 8339a7a..4f448b3 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdb
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdb
index 75f106f..f3d911b 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdb
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kpt b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kpt
index cc179b3..4b9feaa 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kpt
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kpt
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olf.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olf.cdb
deleted file mode 100755
index 0c49a16..0000000
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olf.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olm.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olm.cdb
deleted file mode 100755
index ae4b3c7..0000000
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olm.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.oln.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.oln.cdb
deleted file mode 100755
index 64265ec..0000000
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.oln.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.opi b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.opi
deleted file mode 100755
index 56a6051..0000000
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.opi
+++ /dev/null
@@ -1 +0,0 @@
-1 \ No newline at end of file
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orf.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orf.cdb
deleted file mode 100755
index cc61be4..0000000
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orf.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orm.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orm.cdb
deleted file mode 100755
index 9ad923c..0000000
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orm.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orn.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orn.cdb
deleted file mode 100755
index 5f1bbfa..0000000
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orn.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.cdb
deleted file mode 100755
index d523670..0000000
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.cdb
deleted file mode 100755
index 22dbf8c..0000000
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.hdb
deleted file mode 100755
index 8339a7a..0000000
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.hdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hdb
deleted file mode 100755
index 75f106f..0000000
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdb
index db11b7c..b5cb404 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdb
Binary files differ
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdb
index 7d10985..fab13d7 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdb
Binary files differ
diff --git a/part_2/ex8/output_files/ex8.asm.rpt b/part_2/ex8/output_files/ex8.asm.rpt
index cdabd79..8aaf367 100755
--- a/part_2/ex8/output_files/ex8.asm.rpt
+++ b/part_2/ex8/output_files/ex8.asm.rpt
@@ -1,92 +1,92 @@
-Assembler report for ex8
-Wed Dec 07 12:22:20 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Wed Dec 07 12:22:20 2016 ;
-; Revision Name ; ex8 ;
-; Top-level Entity Name ; ex8 ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+----------------------------------------------------------------------+
-; Assembler Generated Files ;
-+----------------------------------------------------------------------+
-; File Name ;
-+----------------------------------------------------------------------+
-; H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.sof ;
-+----------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.sof ;
-+----------------+-------------------------------------------------------------------------------+
-; Option ; Setting ;
-+----------------+-------------------------------------------------------------------------------+
-; Device ; 5CSEMA5F31C6 ;
-; JTAG usercode ; 0x00B23777 ;
-; Checksum ; 0x00B23777 ;
-+----------------+-------------------------------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
- Info: Processing started: Wed Dec 07 12:22:10 2016
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 891 megabytes
- Info: Processing ended: Wed Dec 07 12:22:20 2016
- Info: Elapsed time: 00:00:10
- Info: Total CPU time (on all processors): 00:00:06
-
-
+Assembler report for ex8
+Sun Dec 11 20:25:43 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: ex8.sof
+ 6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Sun Dec 11 20:25:43 2016 ;
+; Revision Name ; ex8 ;
+; Top-level Entity Name ; ex8 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++---------------------------+
+; Assembler Generated Files ;
++---------------------------+
+; File Name ;
++---------------------------+
+; ex8.sof ;
++---------------------------+
+
+
++-----------------------------------+
+; Assembler Device Options: ex8.sof ;
++----------------+------------------+
+; Option ; Setting ;
++----------------+------------------+
+; Device ; 5CSEMA5F31C6 ;
+; JTAG usercode ; 0x00B2101D ;
+; Checksum ; 0x00B2101D ;
++----------------+------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+ Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+ Info: Processing started: Sun Dec 11 20:25:37 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 972 megabytes
+ Info: Processing ended: Sun Dec 11 20:25:43 2016
+ Info: Elapsed time: 00:00:06
+ Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_2/ex8/output_files/ex8.done b/part_2/ex8/output_files/ex8.done
index 3ad0054..2600f85 100755
--- a/part_2/ex8/output_files/ex8.done
+++ b/part_2/ex8/output_files/ex8.done
@@ -1 +1 @@
-Wed Dec 07 12:22:33 2016
+Sun Dec 11 20:25:48 2016
diff --git a/part_2/ex8/output_files/ex8.fit.rpt b/part_2/ex8/output_files/ex8.fit.rpt
index 6167809..06f6aa9 100755
--- a/part_2/ex8/output_files/ex8.fit.rpt
+++ b/part_2/ex8/output_files/ex8.fit.rpt
@@ -1,2060 +1,2053 @@
-Fitter report for ex8
-Wed Dec 07 12:22:02 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. I/O Assignment Warnings
- 6. Fitter Netlist Optimizations
- 7. Ignored Assignments
- 8. Incremental Compilation Preservation Summary
- 9. Incremental Compilation Partition Settings
- 10. Incremental Compilation Placement Preservation
- 11. Pin-Out File
- 12. Fitter Resource Usage Summary
- 13. Fitter Partition Statistics
- 14. Input Pins
- 15. Output Pins
- 16. I/O Bank Usage
- 17. All Package Pins
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Global & Other Fast Signals
- 23. Routing Usage Summary
- 24. I/O Rules Summary
- 25. I/O Rules Details
- 26. I/O Rules Matrix
- 27. Fitter Device Options
- 28. Operating Settings and Conditions
- 29. Estimated Delay Added for Hold Timing Summary
- 30. Estimated Delay Added for Hold Timing Details
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+---------------------------------+-------------------------------------------------+
-; Fitter Status ; Successful - Wed Dec 07 12:22:02 2016 ;
-; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name ; ex8 ;
-; Top-level Entity Name ; ex8 ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Logic utilization (in ALMs) ; 79 / 32,070 ( < 1 % ) ;
-; Total registers ; 84 ;
-; Total pins ; 36 / 457 ( 8 % ) ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
-; Total RAM Blocks ; 0 / 397 ( 0 % ) ;
-; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 / 6 ( 0 % ) ;
-; Total DLLs ; 0 / 4 ( 0 % ) ;
-+---------------------------------+-------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; 5CSEMA5F31C6 ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Auto RAM to MLAB Conversion ; On ; On ;
-; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
-; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
-; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Clamping Diode ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-; Advanced Physical Optimization ; On ; On ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.02 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.6% ;
-; Processor 3 ; 0.5% ;
-; Processor 4 ; 0.5% ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+--------------------------------------+
-; Pin Name ; Reason ;
-+----------+--------------------------------------+
-; HEX0[0] ; Missing drive strength and slew rate ;
-; HEX0[1] ; Missing drive strength and slew rate ;
-; HEX0[2] ; Missing drive strength and slew rate ;
-; HEX0[3] ; Missing drive strength and slew rate ;
-; HEX0[4] ; Missing drive strength and slew rate ;
-; HEX0[5] ; Missing drive strength and slew rate ;
-; HEX0[6] ; Missing drive strength and slew rate ;
-; HEX1[0] ; Missing drive strength and slew rate ;
-; HEX1[1] ; Missing drive strength and slew rate ;
-; HEX1[2] ; Missing drive strength and slew rate ;
-; HEX1[3] ; Missing drive strength and slew rate ;
-; HEX1[4] ; Missing drive strength and slew rate ;
-; HEX1[5] ; Missing drive strength and slew rate ;
-; HEX1[6] ; Missing drive strength and slew rate ;
-; HEX2[0] ; Missing drive strength and slew rate ;
-; HEX2[1] ; Missing drive strength and slew rate ;
-; HEX2[2] ; Missing drive strength and slew rate ;
-; HEX2[3] ; Missing drive strength and slew rate ;
-; HEX2[4] ; Missing drive strength and slew rate ;
-; HEX2[5] ; Missing drive strength and slew rate ;
-; HEX2[6] ; Missing drive strength and slew rate ;
-; LEDR[0] ; Missing drive strength and slew rate ;
-; LEDR[1] ; Missing drive strength and slew rate ;
-; LEDR[2] ; Missing drive strength and slew rate ;
-; LEDR[3] ; Missing drive strength and slew rate ;
-; LEDR[4] ; Missing drive strength and slew rate ;
-; LEDR[5] ; Missing drive strength and slew rate ;
-; LEDR[6] ; Missing drive strength and slew rate ;
-; LEDR[7] ; Missing drive strength and slew rate ;
-; LEDR[8] ; Missing drive strength and slew rate ;
-; LEDR[9] ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Netlist Optimizations ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
-; delay:DEL0|state.TIME_OUT ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; delay:DEL0|state.TIME_OUT~DUPLICATE ; ; ;
-; formula_fsm:FSM|count[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; formula_fsm:FSM|count[1]~DUPLICATE ; ; ;
-; formula_fsm:FSM|count[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; formula_fsm:FSM|count[7]~DUPLICATE ; ; ;
-; formula_fsm:FSM|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; formula_fsm:FSM|count[11]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[0]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[1]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[2]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[3]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[4]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[6]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[8]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[9]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[10]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[11]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[12]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[13]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[15]~DUPLICATE ; ; ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Location ; ; ; ADC_CS ; PIN_AG20 ; QSF Assignment ;
-; Location ; ; ; ADC_SCK ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; ADC_SDI ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; ADC_SDO ; PIN_AJ21 ; QSF Assignment ;
-; Location ; ; ; DAC_CS ; PIN_AD20 ; QSF Assignment ;
-; Location ; ; ; DAC_LD ; PIN_AK21 ; QSF Assignment ;
-; Location ; ; ; DAC_SCK ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; DAC_SDI ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; HEX3[0] ; PIN_AD26 ; QSF Assignment ;
-; Location ; ; ; HEX3[1] ; PIN_AC27 ; QSF Assignment ;
-; Location ; ; ; HEX3[2] ; PIN_AD25 ; QSF Assignment ;
-; Location ; ; ; HEX3[3] ; PIN_AC25 ; QSF Assignment ;
-; Location ; ; ; HEX3[4] ; PIN_AB28 ; QSF Assignment ;
-; Location ; ; ; HEX3[5] ; PIN_AB25 ; QSF Assignment ;
-; Location ; ; ; HEX3[6] ; PIN_AB22 ; QSF Assignment ;
-; Location ; ; ; HEX4[0] ; PIN_AA24 ; QSF Assignment ;
-; Location ; ; ; HEX4[1] ; PIN_Y23 ; QSF Assignment ;
-; Location ; ; ; HEX4[2] ; PIN_Y24 ; QSF Assignment ;
-; Location ; ; ; HEX4[3] ; PIN_W22 ; QSF Assignment ;
-; Location ; ; ; HEX4[4] ; PIN_W24 ; QSF Assignment ;
-; Location ; ; ; HEX4[5] ; PIN_V23 ; QSF Assignment ;
-; Location ; ; ; HEX4[6] ; PIN_W25 ; QSF Assignment ;
-; Location ; ; ; HEX5[0] ; PIN_V25 ; QSF Assignment ;
-; Location ; ; ; HEX5[1] ; PIN_AA28 ; QSF Assignment ;
-; Location ; ; ; HEX5[2] ; PIN_Y27 ; QSF Assignment ;
-; Location ; ; ; HEX5[3] ; PIN_AB27 ; QSF Assignment ;
-; Location ; ; ; HEX5[4] ; PIN_AB26 ; QSF Assignment ;
-; Location ; ; ; HEX5[5] ; PIN_AA26 ; QSF Assignment ;
-; Location ; ; ; HEX5[6] ; PIN_AA25 ; QSF Assignment ;
-; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ;
-; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ;
-; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ;
-; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ;
-; Location ; ; ; PWM_OUT ; PIN_AJ20 ; QSF Assignment ;
-; Location ; ; ; SW[0] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; SW[1] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; SW[2] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; SW[3] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AC9 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AE12 ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; ADC_CS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; ADC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; ADC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; ADC_SDO ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; DAC_CS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; DAC_LD ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; DAC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; DAC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX3[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX3[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX3[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX3[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX3[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX3[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX3[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX4[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX4[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX4[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX4[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX4[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX4[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX4[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; PWM_OUT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; SW[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; SW[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; SW[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; SW[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; SW[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; SW[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; SW[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; SW[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; SW[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex8 ; ; SW[9] ; 3.3-V LVTTL ; QSF Assignment ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 282 ) ; 0.00 % ( 0 / 282 ) ; 0.00 % ( 0 / 282 ) ;
-; -- Achieved ; 0.00 % ( 0 / 282 ) ; 0.00 % ( 0 / 282 ) ; 0.00 % ( 0 / 282 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 282 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.pin.
-
-
-+------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+-------------------------------------------------------------+--------------------+-------+
-; Resource ; Usage ; % ;
-+-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 79 / 32,070 ; < 1 % ;
-; ALMs needed [=A-B+C] ; 79 ; ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 82 / 32,070 ; < 1 % ;
-; [a] ALMs used for LUT logic and registers ; 28 ; ;
-; [b] ALMs used for LUT logic ; 48 ; ;
-; [c] ALMs used for registers ; 6 ; ;
-; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
-; [B] Estimate of ALMs recoverable by dense packing ; 3 / 32,070 ; < 1 % ;
-; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ;
-; [a] Due to location constrained logic ; 0 ; ;
-; [b] Due to LAB-wide signal conflicts ; 0 ; ;
-; [c] Due to LAB input limits ; 0 ; ;
-; [d] Due to virtual I/Os ; 0 ; ;
-; ; ; ;
-; Difficulty packing design ; Low ; ;
-; ; ; ;
-; Total LABs: partially or completely used ; 10 / 3,207 ; < 1 % ;
-; -- Logic LABs ; 10 ; ;
-; -- Memory LABs (up to half of total LABs) ; 0 ; ;
-; ; ; ;
-; Combinational ALUT usage for logic ; 142 ; ;
-; -- 7 input functions ; 0 ; ;
-; -- 6 input functions ; 29 ; ;
-; -- 5 input functions ; 5 ; ;
-; -- 4 input functions ; 40 ; ;
-; -- <=3 input functions ; 68 ; ;
-; Combinational ALUT usage for route-throughs ; 1 ; ;
-; Dedicated logic registers ; 84 ; ;
-; -- By type: ; ; ;
-; -- Primary logic registers ; 67 / 64,140 ; < 1 % ;
-; -- Secondary logic registers ; 17 / 64,140 ; < 1 % ;
-; -- By function: ; ; ;
-; -- Design implementation registers ; 67 ; ;
-; -- Routing optimization registers ; 17 ; ;
-; ; ; ;
-; Virtual pins ; 0 ; ;
-; I/O pins ; 36 / 457 ; 8 % ;
-; -- Clock pins ; 2 / 8 ; 25 % ;
-; -- Dedicated input pins ; 0 / 21 ; 0 % ;
-; ; ; ;
-; Hard processor system peripheral utilization ; ; ;
-; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
-; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
-; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
-; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
-; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
-; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
-; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
-; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
-; -- JTAG ; 0 / 1 ( 0 % ) ; ;
-; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
-; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
-; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
-; -- STM event ; 0 / 1 ( 0 % ) ; ;
-; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
-; -- DMA ; 0 / 1 ( 0 % ) ; ;
-; -- CAN ; 0 / 2 ( 0 % ) ; ;
-; -- EMAC ; 0 / 2 ( 0 % ) ; ;
-; -- I2C ; 0 / 4 ( 0 % ) ; ;
-; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
-; -- QSPI ; 0 / 1 ( 0 % ) ; ;
-; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
-; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
-; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
-; -- UART ; 0 / 2 ( 0 % ) ; ;
-; -- USB ; 0 / 2 ( 0 % ) ; ;
-; ; ; ;
-; Global signals ; 1 ; ;
-; M10K blocks ; 0 / 397 ; 0 % ;
-; Total MLAB memory bits ; 0 ; ;
-; Total block memory bits ; 0 / 4,065,280 ; 0 % ;
-; Total block memory implementation bits ; 0 / 4,065,280 ; 0 % ;
-; ; ; ;
-; Total DSP Blocks ; 0 / 87 ; 0 % ;
-; ; ; ;
-; Fractional PLLs ; 0 / 6 ; 0 % ;
-; Global clocks ; 1 / 16 ; 6 % ;
-; Quadrant clocks ; 0 / 66 ; 0 % ;
-; Horizontal periphery clocks ; 0 / 18 ; 0 % ;
-; SERDES Transmitters ; 0 / 100 ; 0 % ;
-; SERDES Receivers ; 0 / 100 ; 0 % ;
-; JTAGs ; 0 / 1 ; 0 % ;
-; ASMI blocks ; 0 / 1 ; 0 % ;
-; CRC blocks ; 0 / 1 ; 0 % ;
-; Remote update blocks ; 0 / 1 ; 0 % ;
-; Oscillator blocks ; 0 / 1 ; 0 % ;
-; Impedance control blocks ; 0 / 4 ; 0 % ;
-; Hard Memory Controllers ; 0 / 2 ; 0 % ;
-; Average interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; ;
-; Peak interconnect usage (total/H/V) ; 2.0% / 2.2% / 1.4% ; ;
-; Maximum fan-out ; 54 ; ;
-; Highest non-global fan-out ; 54 ; ;
-; Total fan-out ; 780 ; ;
-; Average fan-out ; 2.60 ; ;
-+-------------------------------------------------------------+--------------------+-------+
-
-
-+---------------------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+-------------------------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+-------------------------------------------------------------+----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 79 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; ALMs needed [=A-B+C] ; 79 ; 0 ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 82 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; [a] ALMs used for LUT logic and registers ; 28 ; 0 ;
-; [b] ALMs used for LUT logic ; 48 ; 0 ;
-; [c] ALMs used for registers ; 6 ; 0 ;
-; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
-; [B] Estimate of ALMs recoverable by dense packing ; 3 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
-; [a] Due to location constrained logic ; 0 ; 0 ;
-; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
-; [c] Due to LAB input limits ; 0 ; 0 ;
-; [d] Due to virtual I/Os ; 0 ; 0 ;
-; ; ; ;
-; Difficulty packing design ; Low ; Low ;
-; ; ; ;
-; Total LABs: partially or completely used ; 10 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ;
-; -- Logic LABs ; 10 ; 0 ;
-; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
-; ; ; ;
-; Combinational ALUT usage for logic ; 142 ; 0 ;
-; -- 7 input functions ; 0 ; 0 ;
-; -- 6 input functions ; 29 ; 0 ;
-; -- 5 input functions ; 5 ; 0 ;
-; -- 4 input functions ; 40 ; 0 ;
-; -- <=3 input functions ; 68 ; 0 ;
-; Combinational ALUT usage for route-throughs ; 1 ; 0 ;
-; Memory ALUT usage ; 0 ; 0 ;
-; -- 64-address deep ; 0 ; 0 ;
-; -- 32-address deep ; 0 ; 0 ;
-; ; ; ;
-; Dedicated logic registers ; 0 ; 0 ;
-; -- By type: ; ; ;
-; -- Primary logic registers ; 67 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
-; -- Secondary logic registers ; 17 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
-; -- By function: ; ; ;
-; -- Design implementation registers ; 67 ; 0 ;
-; -- Routing optimization registers ; 17 ; 0 ;
-; ; ; ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 36 ; 0 ;
-; I/O registers ; 0 ; 0 ;
-; Total block memory bits ; 0 ; 0 ;
-; Total block memory implementation bits ; 0 ; 0 ;
-; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 780 ; 0 ;
-; -- Registered Connections ; 339 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 5 ; 0 ;
-; -- Output Ports ; 31 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+-------------------------------------------------------------+----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; AF14 ; 3B ; 32 ; 0 ; 0 ; 30 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-; KEY[0] ; AA14 ; 3B ; 36 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-; KEY[1] ; AA15 ; 3B ; 36 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-; KEY[2] ; W15 ; 3B ; 40 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-; KEY[3] ; Y16 ; 3B ; 40 ; 0 ; 17 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[0] ; AJ29 ; 5A ; 89 ; 6 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[1] ; AH29 ; 5A ; 89 ; 6 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[2] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[3] ; AG30 ; 5A ; 89 ; 16 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[4] ; AF29 ; 5A ; 89 ; 15 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[5] ; AF30 ; 5A ; 89 ; 15 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[6] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[0] ; AB23 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[1] ; AE29 ; 5B ; 89 ; 23 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[2] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[3] ; AC28 ; 5B ; 89 ; 20 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[4] ; AD30 ; 5B ; 89 ; 25 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[5] ; AC29 ; 5B ; 89 ; 20 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[6] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[0] ; V16 ; 4A ; 52 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[1] ; W16 ; 4A ; 52 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[2] ; V17 ; 4A ; 60 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[3] ; V18 ; 4A ; 80 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[4] ; W17 ; 4A ; 60 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[5] ; W19 ; 4A ; 80 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[6] ; Y19 ; 4A ; 84 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[7] ; W20 ; 5A ; 89 ; 6 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[8] ; W21 ; 5A ; 89 ; 8 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[9] ; Y21 ; 5A ; 89 ; 6 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+----------------------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+---------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
-+----------+------------------+---------------+--------------+---------------+
-; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
-; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
-; 3A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 3B ; 5 / 48 ( 10 % ) ; 3.3V ; -- ; 3.3V ;
-; 4A ; 7 / 80 ( 9 % ) ; 3.3V ; -- ; 3.3V ;
-; 5A ; 18 / 32 ( 56 % ) ; 3.3V ; -- ; 3.3V ;
-; 5B ; 6 / 16 ( 38 % ) ; 3.3V ; -- ; 3.3V ;
-; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-+----------+------------------+---------------+--------------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
-; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
-; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 122 ; 3B ; KEY[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AA15 ; 120 ; 3B ; KEY[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB12 ; 72 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB14 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 225 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB23 ; 227 ; 5A ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB25 ; 230 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB28 ; 249 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC11 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC12 ; 82 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC21 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AC25 ; 215 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC27 ; 242 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC28 ; 245 ; 5B ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AC29 ; 247 ; 5B ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AC30 ; 259 ; 5B ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD10 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 80 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD26 ; 240 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 222 ; 5A ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD29 ; 255 ; 5B ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD30 ; 257 ; 5B ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE11 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE29 ; 253 ; 5B ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE30 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 67 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 57 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 114 ; 3B ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AF29 ; 237 ; 5A ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AF30 ; 239 ; 5A ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AG30 ; 243 ; 5A ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH16 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AH29 ; 218 ; 5A ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AH30 ; 241 ; 5A ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ29 ; 216 ; 5A ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK10 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK20 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
-; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
-; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
-; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
-; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
-; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
-; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
-; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
-; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
-; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
-; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
-; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
-; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U23 ; ; 5B ; VCCPD5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V16 ; 138 ; 4A ; LEDR[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; V17 ; 154 ; 4A ; LEDR[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; V18 ; 194 ; 4A ; LEDR[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W15 ; 130 ; 3B ; KEY[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; W16 ; 136 ; 4A ; LEDR[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; W17 ; 152 ; 4A ; LEDR[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W19 ; 192 ; 4A ; LEDR[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; W20 ; 217 ; 5A ; LEDR[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; W21 ; 221 ; 5A ; LEDR[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y16 ; 128 ; 3B ; KEY[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y19 ; 202 ; 4A ; LEDR[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y21 ; 219 ; 5A ; LEDR[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y23 ; 232 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex8 ; 78.5 (0.5) ; 81.0 (0.5) ; 2.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 142 (1) ; 84 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 36 ; 0 ; |ex8 ; ex8 ; work ;
-; |LFSR:LFSR0| ; 2.9 (2.9) ; 3.6 (3.6) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|LFSR:LFSR0 ; LFSR ; work ;
-; |bin2bcd_16:BCD| ; 5.4 (0.0) ; 5.6 (0.0) ; 0.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD ; bin2bcd_16 ; work ;
-; |add3_ge5:A22| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5 ; work ;
-; |add3_ge5:A26| ; 1.3 (1.3) ; 1.6 (1.6) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5 ; work ;
-; |add3_ge5:A30| ; 1.7 (1.7) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5 ; work ;
-; |add3_ge5:A35| ; 1.7 (1.7) ; 1.8 (1.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5 ; work ;
-; |delay:DEL0| ; 14.3 (14.3) ; 14.3 (14.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|delay:DEL0 ; delay ; work ;
-; |formula_fsm:FSM| ; 25.6 (25.6) ; 26.5 (26.5) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 43 (43) ; 28 (28) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|formula_fsm:FSM ; formula_fsm ; work ;
-; |hex_to_7seg:SEG0| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG1| ; 7.7 (7.7) ; 8.0 (8.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG2| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
-; |tick_50000:TICK0| ; 18.5 (18.5) ; 19.0 (19.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (36) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|tick_50000:TICK0 ; tick_50000 ; work ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; KEY[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; KEY[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; KEY[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; KEY[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; CLOCK_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+-------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+-------------------------------------------------+-------------------+---------+
-; KEY[0] ; ; ;
-; KEY[1] ; ; ;
-; KEY[2] ; ; ;
-; KEY[3] ; ; ;
-; - formula_fsm:FSM|Selector3~0 ; 0 ; 0 ;
-; - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~0 ; 0 ; 0 ;
-; - formula_fsm:FSM|Selector2~0 ; 0 ; 0 ;
-; CLOCK_50 ; ; ;
-; - tick_50000:TICK0|CLK_OUT ; 0 ; 0 ;
-+-------------------------------------------------+-------------------+---------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 2 ; Clock ; no ; -- ; -- ; -- ;
-; CLOCK_50 ; PIN_AF14 ; 29 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ;
-; delay:DEL0|count[0]~0 ; LABCELL_X80_Y3_N54 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
-; delay:DEL0|state.COUNTING ; FF_X79_Y3_N8 ; 20 ; Sync. load ; no ; -- ; -- ; -- ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X80_Y3_N59 ; 26 ; Clock enable, Latch enable ; no ; -- ; -- ; -- ;
-; formula_fsm:FSM|state.WAIT_TRIGGER ; FF_X78_Y3_N14 ; 18 ; Clock enable ; no ; -- ; -- ; -- ;
-; tick_50000:TICK0|CLK_OUT ; FF_X75_Y3_N50 ; 54 ; Clock ; no ; -- ; -- ; -- ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 29 ; Global Clock ; GCLK6 ; -- ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------+
-; Routing Usage Summary ;
-+---------------------------------------------+-------------------------+
-; Routing Resource Type ; Usage ;
-+---------------------------------------------+-------------------------+
-; Block interconnects ; 243 / 289,320 ( < 1 % ) ;
-; C12 interconnects ; 2 / 13,420 ( < 1 % ) ;
-; C2 interconnects ; 78 / 119,108 ( < 1 % ) ;
-; C4 interconnects ; 45 / 56,300 ( < 1 % ) ;
-; DQS bus muxes ; 0 / 25 ( 0 % ) ;
-; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
-; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
-; Direct links ; 49 / 289,320 ( < 1 % ) ;
-; Global clocks ; 1 / 16 ( 6 % ) ;
-; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
-; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
-; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
-; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
-; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ;
-; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
-; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
-; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
-; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
-; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
-; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ;
-; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
-; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
-; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
-; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
-; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
-; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
-; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
-; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
-; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
-; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
-; Local interconnects ; 72 / 84,580 ( < 1 % ) ;
-; Quadrant clocks ; 0 / 66 ( 0 % ) ;
-; R14 interconnects ; 37 / 12,676 ( < 1 % ) ;
-; R14/C12 interconnect drivers ; 35 / 20,720 ( < 1 % ) ;
-; R3 interconnects ; 127 / 130,992 ( < 1 % ) ;
-; R6 interconnects ; 124 / 266,960 ( < 1 % ) ;
-; Spine clocks ; 1 / 360 ( < 1 % ) ;
-; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
-+---------------------------------------------+-------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 28 ;
-; Number of I/O Rules Passed ; 6 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 22 ;
-+----------------------------------+-------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-; Total Pass ; 36 ; 0 ; 36 ; 0 ; 0 ; 36 ; 36 ; 0 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 0 ; 36 ; 0 ; 36 ; 36 ; 0 ; 0 ; 36 ; 0 ; 0 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; KEY[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+-----------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+-----------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Passive Serial ;
-; Enable Error Detection CRC_ERROR pin ; Off ;
-; Enable CvP_CONFDONE pin ; Off ;
-; Enable open drain on CRC_ERROR pin ; On ;
-; Enable open drain on CvP_CONFDONE pin ; On ;
-; Enable open drain on INIT_DONE pin ; On ;
-; Enable open drain on Partial Reconfiguration pins ; Off ;
-; Enable open drain on nCEO pin ; On ;
-; Enable Partial Reconfiguration pins ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Enable internal scrubbing ; Off ;
-; Active Serial clock source ; 100 MHz Internal Oscillator ;
-; Device initialization clock source ; Internal Oscillator ;
-; Configuration via Protocol ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; Enable nCEO output ; Off ;
-; Data[15..8] ; Unreserved ;
-; Data[7..5] ; Unreserved ;
-; Base pin-out file on sameframe device ; Off ;
-+------------------------------------------------------------------+-----------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.10 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-------------------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 58.9 ;
-; CLOCK_50 ; CLOCK_50 ; 12.7 ;
-; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.8 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.3 ;
-; tick_50000:TICK0|CLK_OUT,I/O ; tick_50000:TICK0|CLK_OUT ; 1.6 ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details ;
-+----------------------------------------+----------------------------------------+-------------------+
-; Source Register ; Destination Register ; Delay Added in ns ;
-+----------------------------------------+----------------------------------------+-------------------+
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|ledr[1] ; 2.039 ;
-; tick_50000:TICK0|count[5] ; tick_50000:TICK0|CLK_OUT ; 1.697 ;
-; tick_50000:TICK0|count[11] ; tick_50000:TICK0|CLK_OUT ; 1.669 ;
-; formula_fsm:FSM|start_delay ; delay:DEL0|state.IDLE ; 1.640 ;
-; tick_50000:TICK0|count[9] ; tick_50000:TICK0|CLK_OUT ; 1.620 ;
-; tick_50000:TICK0|count[8] ; tick_50000:TICK0|CLK_OUT ; 1.620 ;
-; tick_50000:TICK0|count[12] ; tick_50000:TICK0|CLK_OUT ; 1.617 ;
-; tick_50000:TICK0|count[6] ; tick_50000:TICK0|CLK_OUT ; 1.583 ;
-; tick_50000:TICK0|count[13] ; tick_50000:TICK0|CLK_OUT ; 1.577 ;
-; tick_50000:TICK0|count[15] ; tick_50000:TICK0|CLK_OUT ; 1.577 ;
-; tick_50000:TICK0|count[14] ; tick_50000:TICK0|CLK_OUT ; 1.576 ;
-; tick_50000:TICK0|count[2] ; tick_50000:TICK0|CLK_OUT ; 1.573 ;
-; tick_50000:TICK0|count[3] ; tick_50000:TICK0|CLK_OUT ; 1.561 ;
-; tick_50000:TICK0|count[4] ; tick_50000:TICK0|CLK_OUT ; 1.535 ;
-; tick_50000:TICK0|count[7] ; tick_50000:TICK0|CLK_OUT ; 1.534 ;
-; tick_50000:TICK0|count[0] ; tick_50000:TICK0|CLK_OUT ; 1.519 ;
-; tick_50000:TICK0|count[1] ; tick_50000:TICK0|CLK_OUT ; 1.499 ;
-; tick_50000:TICK0|count[10] ; tick_50000:TICK0|CLK_OUT ; 1.470 ;
-; delay:DEL0|count[6] ; delay:DEL0|count[11] ; 1.038 ;
-; delay:DEL0|count[8] ; delay:DEL0|count[11] ; 1.036 ;
-; delay:DEL0|count[13] ; delay:DEL0|count[11] ; 1.008 ;
-; formula_fsm:FSM|count[1] ; formula_fsm:FSM|ledr[0] ; 0.996 ;
-; formula_fsm:FSM|count[6] ; formula_fsm:FSM|ledr[0] ; 0.988 ;
-; formula_fsm:FSM|count[8] ; formula_fsm:FSM|ledr[0] ; 0.985 ;
-; delay:DEL0|count[4] ; delay:DEL0|count[11] ; 0.981 ;
-; LFSR:LFSR0|COUNT[1] ; LFSR:LFSR0|COUNT[2] ; 0.980 ;
-; delay:DEL0|count[10] ; delay:DEL0|count[11] ; 0.980 ;
-; formula_fsm:FSM|count[0] ; formula_fsm:FSM|ledr[0] ; 0.975 ;
-; formula_fsm:FSM|count[7] ; formula_fsm:FSM|ledr[0] ; 0.968 ;
-; delay:DEL0|state.COUNTING ; delay:DEL0|state.IDLE ; 0.923 ;
-; delay:DEL0|count[0] ; delay:DEL0|count[11] ; 0.895 ;
-; delay:DEL0|count[1] ; delay:DEL0|count[11] ; 0.874 ;
-; delay:DEL0|count[7] ; delay:DEL0|count[11] ; 0.872 ;
-; delay:DEL0|count[2] ; delay:DEL0|count[11] ; 0.845 ;
-; delay:DEL0|count[11] ; delay:DEL0|count[11] ; 0.843 ;
-; delay:DEL0|state.IDLE ; delay:DEL0|state.COUNTING ; 0.836 ;
-; delay:DEL0|count[12] ; delay:DEL0|count[11] ; 0.833 ;
-; formula_fsm:FSM|count[11] ; formula_fsm:FSM|ledr[0] ; 0.830 ;
-; delay:DEL0|state.TIME_OUT ; delay:DEL0|state.IDLE ; 0.820 ;
-; delay:DEL0|count[3] ; delay:DEL0|count[11] ; 0.813 ;
-; delay:DEL0|count[9] ; delay:DEL0|count[11] ; 0.801 ;
-; delay:DEL0|count[5] ; delay:DEL0|count[11] ; 0.801 ;
-; formula_fsm:FSM|ledr[1] ; formula_fsm:FSM|ledr[2] ; 0.795 ;
-; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|count[8] ; 0.791 ;
-; formula_fsm:FSM|count[3] ; formula_fsm:FSM|ledr[0] ; 0.768 ;
-; delay:DEL0|state.WAIT_LOW ; delay:DEL0|state.IDLE ; 0.768 ;
-; formula_fsm:FSM|count[2] ; formula_fsm:FSM|ledr[0] ; 0.766 ;
-; formula_fsm:FSM|ledr[0] ; formula_fsm:FSM|ledr[0] ; 0.737 ;
-; formula_fsm:FSM|count[10] ; formula_fsm:FSM|ledr[0] ; 0.737 ;
-; formula_fsm:FSM|count[9] ; formula_fsm:FSM|ledr[0] ; 0.737 ;
-; formula_fsm:FSM|count[4] ; formula_fsm:FSM|ledr[0] ; 0.737 ;
-; formula_fsm:FSM|count[5] ; formula_fsm:FSM|ledr[0] ; 0.737 ;
-; LFSR:LFSR0|COUNT[3] ; LFSR:LFSR0|COUNT[4] ; 0.731 ;
-; formula_fsm:FSM|ledr[8] ; formula_fsm:FSM|ledr[9] ; 0.729 ;
-; formula_fsm:FSM|ledr[9] ; formula_fsm:FSM|ledr[9] ; 0.729 ;
-; LFSR:LFSR0|COUNT[4] ; LFSR:LFSR0|COUNT[5] ; 0.719 ;
-; formula_fsm:FSM|ledr[2] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711 ;
-; formula_fsm:FSM|ledr[3] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711 ;
-; formula_fsm:FSM|ledr[4] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711 ;
-; formula_fsm:FSM|ledr[5] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711 ;
-; formula_fsm:FSM|ledr[6] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711 ;
-; formula_fsm:FSM|ledr[7] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711 ;
-; KEY[3] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711 ;
-; formula_fsm:FSM|state.WAIT_TRIGGER ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711 ;
-; LFSR:LFSR0|COUNT[7] ; LFSR:LFSR0|COUNT[1] ; 0.663 ;
-; LFSR:LFSR0|COUNT[5] ; LFSR:LFSR0|COUNT[6] ; 0.580 ;
-; LFSR:LFSR0|COUNT[6] ; LFSR:LFSR0|COUNT[7] ; 0.570 ;
-; LFSR:LFSR0|COUNT[2] ; LFSR:LFSR0|COUNT[3] ; 0.563 ;
-+----------------------------------------+----------------------------------------+-------------------+
-Note: This table only shows the top 68 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device 5CSEMA5F31C6 for design "ex8"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Info (184020): Starting Fitter periphery placement operations
-Info (11191): Automatically promoted 1 clock (1 global)
- Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
-Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
-Info (176233): Starting register packing
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
-Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11
-Info (170189): Fitter placement preparation operations beginning
-Info (14951): The Fitter is using Advanced Physical Optimization.
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:03
-Info (11888): Total time spent on timing analysis during the Fitter is 0.44 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 51 warnings
- Info: Peak virtual memory: 2608 megabytes
- Info: Processing ended: Wed Dec 07 12:22:05 2016
- Info: Elapsed time: 00:00:38
- Info: Total CPU time (on all processors): 00:00:58
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg.
-
-
+Fitter report for ex8
+Sun Dec 11 20:25:36 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Fitter Netlist Optimizations
+ 6. Ignored Assignments
+ 7. Incremental Compilation Preservation Summary
+ 8. Incremental Compilation Partition Settings
+ 9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. I/O Assignment Warnings
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Routing Usage Summary
+ 24. I/O Rules Summary
+ 25. I/O Rules Details
+ 26. I/O Rules Matrix
+ 27. Fitter Device Options
+ 28. Operating Settings and Conditions
+ 29. Estimated Delay Added for Hold Timing Summary
+ 30. Estimated Delay Added for Hold Timing Details
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-------------------------------------------------------------------------------+
+; Fitter Summary ;
++---------------------------------+---------------------------------------------+
+; Fitter Status ; Successful - Sun Dec 11 20:25:36 2016 ;
+; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Revision Name ; ex8 ;
+; Top-level Entity Name ; ex8 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 76 / 32,070 ( < 1 % ) ;
+; Total registers ; 75 ;
+; Total pins ; 36 / 457 ( 8 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total RAM Blocks ; 0 / 397 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
+; Optimize Hold Timing ; All Paths ; All Paths ;
+; Optimize Multi-Corner Timing ; On ; On ;
+; Auto RAM to MLAB Conversion ; On ; On ;
+; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
+; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
+; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
+; SSN Optimization ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
+; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification ; Auto ; Auto ;
+; Enable Beneficial Skew Optimization ; On ; On ;
+; Optimize Design for Metastability ; On ; On ;
+; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+; Clamping Diode ; Off ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
+; Advanced Physical Optimization ; On ; On ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.02 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.6% ;
+; Processor 3 ; 0.6% ;
+; Processor 4 ; 0.5% ;
++----------------------------+-------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
+; delay:DEL0|state.TIME_OUT ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; delay:DEL0|state.TIME_OUT~DUPLICATE ; ; ;
+; formula_fsm:FSM|count[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; formula_fsm:FSM|count[4]~DUPLICATE ; ; ;
+; formula_fsm:FSM|count[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; formula_fsm:FSM|count[6]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[1]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[5]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[6]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[7]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[10]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[11]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[14]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[15]~DUPLICATE ; ; ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location ; ; ; ADC_CS ; PIN_AG20 ; QSF Assignment ;
+; Location ; ; ; ADC_SCK ; PIN_AF21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDI ; PIN_AG21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDO ; PIN_AJ21 ; QSF Assignment ;
+; Location ; ; ; DAC_CS ; PIN_AD20 ; QSF Assignment ;
+; Location ; ; ; DAC_LD ; PIN_AK21 ; QSF Assignment ;
+; Location ; ; ; DAC_SCK ; PIN_AF20 ; QSF Assignment ;
+; Location ; ; ; DAC_SDI ; PIN_AG18 ; QSF Assignment ;
+; Location ; ; ; HEX3[0] ; PIN_AD26 ; QSF Assignment ;
+; Location ; ; ; HEX3[1] ; PIN_AC27 ; QSF Assignment ;
+; Location ; ; ; HEX3[2] ; PIN_AD25 ; QSF Assignment ;
+; Location ; ; ; HEX3[3] ; PIN_AC25 ; QSF Assignment ;
+; Location ; ; ; HEX3[4] ; PIN_AB28 ; QSF Assignment ;
+; Location ; ; ; HEX3[5] ; PIN_AB25 ; QSF Assignment ;
+; Location ; ; ; HEX3[6] ; PIN_AB22 ; QSF Assignment ;
+; Location ; ; ; HEX4[0] ; PIN_AA24 ; QSF Assignment ;
+; Location ; ; ; HEX4[1] ; PIN_Y23 ; QSF Assignment ;
+; Location ; ; ; HEX4[2] ; PIN_Y24 ; QSF Assignment ;
+; Location ; ; ; HEX4[3] ; PIN_W22 ; QSF Assignment ;
+; Location ; ; ; HEX4[4] ; PIN_W24 ; QSF Assignment ;
+; Location ; ; ; HEX4[5] ; PIN_V23 ; QSF Assignment ;
+; Location ; ; ; HEX4[6] ; PIN_W25 ; QSF Assignment ;
+; Location ; ; ; HEX5[0] ; PIN_V25 ; QSF Assignment ;
+; Location ; ; ; HEX5[1] ; PIN_AA28 ; QSF Assignment ;
+; Location ; ; ; HEX5[2] ; PIN_Y27 ; QSF Assignment ;
+; Location ; ; ; HEX5[3] ; PIN_AB27 ; QSF Assignment ;
+; Location ; ; ; HEX5[4] ; PIN_AB26 ; QSF Assignment ;
+; Location ; ; ; HEX5[5] ; PIN_AA26 ; QSF Assignment ;
+; Location ; ; ; HEX5[6] ; PIN_AA25 ; QSF Assignment ;
+; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ;
+; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ;
+; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ;
+; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ;
+; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ;
+; Location ; ; ; PWM_OUT ; PIN_AJ20 ; QSF Assignment ;
+; Location ; ; ; SW[0] ; PIN_AB12 ; QSF Assignment ;
+; Location ; ; ; SW[1] ; PIN_AC12 ; QSF Assignment ;
+; Location ; ; ; SW[2] ; PIN_AF9 ; QSF Assignment ;
+; Location ; ; ; SW[3] ; PIN_AF10 ; QSF Assignment ;
+; Location ; ; ; SW[4] ; PIN_AD11 ; QSF Assignment ;
+; Location ; ; ; SW[5] ; PIN_AD12 ; QSF Assignment ;
+; Location ; ; ; SW[6] ; PIN_AE11 ; QSF Assignment ;
+; Location ; ; ; SW[7] ; PIN_AC9 ; QSF Assignment ;
+; Location ; ; ; SW[8] ; PIN_AD10 ; QSF Assignment ;
+; Location ; ; ; SW[9] ; PIN_AE12 ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; ADC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; ADC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; ADC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; ADC_SDO ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; DAC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; DAC_LD ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; DAC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; DAC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX3[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX3[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX3[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX3[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX3[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX3[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX3[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX4[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX4[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX4[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX4[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX4[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX4[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX4[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX5[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX5[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX5[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX5[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX5[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX5[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; HEX5[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; PWM_OUT ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; SW[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; SW[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; SW[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; SW[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; SW[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; SW[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; SW[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; SW[7] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; SW[8] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex8 ; ; SW[9] ; 3.3-V LVTTL ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 273 ) ; 0.00 % ( 0 / 273 ) ; 0.00 % ( 0 / 273 ) ;
+; -- Achieved ; 0.00 % ( 0 / 273 ) ; 0.00 % ( 0 / 273 ) ; 0.00 % ( 0 / 273 ) ;
+; ; ; ; ;
+; Routing (by net) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
+; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top ; 0.00 % ( 0 / 273 ) ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource ; Usage ; % ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 76 / 32,070 ; < 1 % ;
+; ALMs needed [=A-B+C] ; 76 ; ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 80 / 32,070 ; < 1 % ;
+; [a] ALMs used for LUT logic and registers ; 27 ; ;
+; [b] ALMs used for LUT logic ; 47 ; ;
+; [c] ALMs used for registers ; 6 ; ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
+; [B] Estimate of ALMs recoverable by dense packing ; 4 / 32,070 ; < 1 % ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ;
+; [a] Due to location constrained logic ; 0 ; ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; ;
+; [c] Due to LAB input limits ; 0 ; ;
+; [d] Due to virtual I/Os ; 0 ; ;
+; ; ; ;
+; Difficulty packing design ; Low ; ;
+; ; ; ;
+; Total LABs: partially or completely used ; 10 / 3,207 ; < 1 % ;
+; -- Logic LABs ; 10 ; ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 136 ; ;
+; -- 7 input functions ; 1 ; ;
+; -- 6 input functions ; 24 ; ;
+; -- 5 input functions ; 5 ; ;
+; -- 4 input functions ; 39 ; ;
+; -- <=3 input functions ; 67 ; ;
+; Combinational ALUT usage for route-throughs ; 4 ; ;
+; ; ; ;
+; Dedicated logic registers ; 75 ; ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 64 / 64,140 ; < 1 % ;
+; -- Secondary logic registers ; 11 / 64,140 ; < 1 % ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 64 ; ;
+; -- Routing optimization registers ; 11 ; ;
+; ; ; ;
+; Virtual pins ; 0 ; ;
+; I/O pins ; 36 / 457 ; 8 % ;
+; -- Clock pins ; 2 / 8 ; 25 % ;
+; -- Dedicated input pins ; 0 / 21 ; 0 % ;
+; ; ; ;
+; Hard processor system peripheral utilization ; ; ;
+; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
+; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
+; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
+; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
+; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
+; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
+; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
+; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
+; -- JTAG ; 0 / 1 ( 0 % ) ; ;
+; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
+; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
+; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
+; -- STM event ; 0 / 1 ( 0 % ) ; ;
+; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
+; -- DMA ; 0 / 1 ( 0 % ) ; ;
+; -- CAN ; 0 / 2 ( 0 % ) ; ;
+; -- EMAC ; 0 / 2 ( 0 % ) ; ;
+; -- I2C ; 0 / 4 ( 0 % ) ; ;
+; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
+; -- QSPI ; 0 / 1 ( 0 % ) ; ;
+; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
+; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
+; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
+; -- UART ; 0 / 2 ( 0 % ) ; ;
+; -- USB ; 0 / 2 ( 0 % ) ; ;
+; ; ; ;
+; M10K blocks ; 0 / 397 ; 0 % ;
+; Total MLAB memory bits ; 0 ; ;
+; Total block memory bits ; 0 / 4,065,280 ; 0 % ;
+; Total block memory implementation bits ; 0 / 4,065,280 ; 0 % ;
+; ; ; ;
+; Total DSP Blocks ; 0 / 87 ; 0 % ;
+; ; ; ;
+; Fractional PLLs ; 0 / 6 ; 0 % ;
+; Global signals ; 1 ; ;
+; -- Global clocks ; 1 / 16 ; 6 % ;
+; -- Quadrant clocks ; 0 / 66 ; 0 % ;
+; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ;
+; SERDES Transmitters ; 0 / 100 ; 0 % ;
+; SERDES Receivers ; 0 / 100 ; 0 % ;
+; JTAGs ; 0 / 1 ; 0 % ;
+; ASMI blocks ; 0 / 1 ; 0 % ;
+; CRC blocks ; 0 / 1 ; 0 % ;
+; Remote update blocks ; 0 / 1 ; 0 % ;
+; Oscillator blocks ; 0 / 1 ; 0 % ;
+; Impedance control blocks ; 0 / 4 ; 0 % ;
+; Hard Memory Controllers ; 0 / 2 ; 0 % ;
+; Average interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; ;
+; Peak interconnect usage (total/H/V) ; 2.5% / 2.5% / 2.2% ; ;
+; Maximum fan-out ; 50 ; ;
+; Highest non-global fan-out ; 50 ; ;
+; Total fan-out ; 737 ; ;
+; Average fan-out ; 2.56 ; ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+; Statistic ; Top ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 76 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; ALMs needed [=A-B+C] ; 76 ; 0 ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 80 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] ALMs used for LUT logic and registers ; 27 ; 0 ;
+; [b] ALMs used for LUT logic ; 47 ; 0 ;
+; [c] ALMs used for registers ; 6 ; 0 ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
+; [B] Estimate of ALMs recoverable by dense packing ; 4 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] Due to location constrained logic ; 0 ; 0 ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
+; [c] Due to LAB input limits ; 0 ; 0 ;
+; [d] Due to virtual I/Os ; 0 ; 0 ;
+; ; ; ;
+; Difficulty packing design ; Low ; Low ;
+; ; ; ;
+; Total LABs: partially or completely used ; 10 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ;
+; -- Logic LABs ; 10 ; 0 ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 136 ; 0 ;
+; -- 7 input functions ; 1 ; 0 ;
+; -- 6 input functions ; 24 ; 0 ;
+; -- 5 input functions ; 5 ; 0 ;
+; -- 4 input functions ; 39 ; 0 ;
+; -- <=3 input functions ; 67 ; 0 ;
+; Combinational ALUT usage for route-throughs ; 4 ; 0 ;
+; Memory ALUT usage ; 0 ; 0 ;
+; -- 64-address deep ; 0 ; 0 ;
+; -- 32-address deep ; 0 ; 0 ;
+; ; ; ;
+; Dedicated logic registers ; 0 ; 0 ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 64 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
+; -- Secondary logic registers ; 11 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 64 ; 0 ;
+; -- Routing optimization registers ; 11 ; 0 ;
+; ; ; ;
+; ; ; ;
+; Virtual pins ; 0 ; 0 ;
+; I/O pins ; 36 ; 0 ;
+; I/O registers ; 0 ; 0 ;
+; Total block memory bits ; 0 ; 0 ;
+; Total block memory implementation bits ; 0 ; 0 ;
+; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ;
+; ; ; ;
+; Connections ; ; ;
+; -- Input Connections ; 0 ; 0 ;
+; -- Registered Input Connections ; 0 ; 0 ;
+; -- Output Connections ; 0 ; 0 ;
+; -- Registered Output Connections ; 0 ; 0 ;
+; ; ; ;
+; Internal Connections ; ; ;
+; -- Total Connections ; 737 ; 0 ;
+; -- Registered Connections ; 318 ; 0 ;
+; ; ; ;
+; External Connections ; ; ;
+; -- Top ; 0 ; 0 ;
+; -- hard_block:auto_generated_inst ; 0 ; 0 ;
+; ; ; ;
+; Partition Interface ; ; ;
+; -- Input Ports ; 5 ; 0 ;
+; -- Output Ports ; 31 ; 0 ;
+; -- Bidir Ports ; 0 ; 0 ;
+; ; ; ;
+; Registered Ports ; ; ;
+; -- Registered Input Ports ; 0 ; 0 ;
+; -- Registered Output Ports ; 0 ; 0 ;
+; ; ; ;
+; Port Connectivity ; ; ;
+; -- Input Ports driven by GND ; 0 ; 0 ;
+; -- Output Ports driven by GND ; 0 ; 0 ;
+; -- Input Ports driven by VCC ; 0 ; 0 ;
+; -- Output Ports driven by VCC ; 0 ; 0 ;
+; -- Input Ports with no Source ; 0 ; 0 ;
+; -- Output Ports with no Source ; 0 ; 0 ;
+; -- Input Ports with no Fanout ; 0 ; 0 ;
+; -- Output Ports with no Fanout ; 0 ; 0 ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; CLOCK_50 ; AF14 ; 3B ; 32 ; 0 ; 0 ; 25 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; KEY[0] ; AA14 ; 3B ; 36 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; KEY[1] ; AA15 ; 3B ; 36 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; KEY[2] ; W15 ; 3B ; 40 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; KEY[3] ; Y16 ; 3B ; 40 ; 0 ; 17 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[0] ; AJ29 ; 5A ; 89 ; 6 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[1] ; AH29 ; 5A ; 89 ; 6 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[2] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[3] ; AG30 ; 5A ; 89 ; 16 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[4] ; AF29 ; 5A ; 89 ; 15 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[5] ; AF30 ; 5A ; 89 ; 15 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[6] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[0] ; AB23 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[1] ; AE29 ; 5B ; 89 ; 23 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[2] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[3] ; AC28 ; 5B ; 89 ; 20 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[4] ; AD30 ; 5B ; 89 ; 25 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[5] ; AC29 ; 5B ; 89 ; 20 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[6] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[0] ; V16 ; 4A ; 52 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[1] ; W16 ; 4A ; 52 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[2] ; V17 ; 4A ; 60 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[3] ; V18 ; 4A ; 80 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[4] ; W17 ; 4A ; 60 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[5] ; W19 ; 4A ; 80 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[6] ; Y19 ; 4A ; 84 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[7] ; W20 ; 5A ; 89 ; 6 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[8] ; W21 ; 5A ; 89 ; 8 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[9] ; Y21 ; 5A ; 89 ; 6 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; 3A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 3B ; 5 / 48 ( 10 % ) ; 3.3V ; -- ; 3.3V ;
+; 4A ; 7 / 80 ( 9 % ) ; 3.3V ; -- ; 3.3V ;
+; 5A ; 18 / 32 ( 56 % ) ; 3.3V ; -- ; 3.3V ;
+; 5B ; 6 / 16 ( 38 % ) ; 3.3V ; -- ; 3.3V ;
+; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
+; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
+; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA14 ; 122 ; 3B ; KEY[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA15 ; 120 ; 3B ; KEY[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA17 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA27 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB12 ; 72 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB14 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB22 ; 225 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB23 ; 227 ; 5A ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB25 ; 230 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB27 ; 254 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB28 ; 249 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC11 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC12 ; 82 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC21 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AC25 ; 215 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC27 ; 242 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC28 ; 245 ; 5B ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC29 ; 247 ; 5B ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC30 ; 259 ; 5B ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD8 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD10 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD11 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD12 ; 80 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD18 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD25 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD26 ; 240 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD27 ; 222 ; 5A ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD29 ; 255 ; 5B ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD30 ; 257 ; 5B ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE11 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE12 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE15 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE25 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE29 ; 253 ; 5B ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE30 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF9 ; 67 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF10 ; 57 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF14 ; 114 ; 3B ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF22 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AF29 ; 237 ; 5A ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AF30 ; 239 ; 5A ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG4 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG19 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG30 ; 243 ; 5A ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH16 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH26 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH29 ; 218 ; 5A ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH30 ; 241 ; 5A ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ29 ; 216 ; 5A ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK10 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK20 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
+; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
+; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
+; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
+; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
+; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
+; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
+; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
+; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
+; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
+; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
+; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
+; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
+; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
+; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
+; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U23 ; ; 5B ; VCCPD5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V16 ; 138 ; 4A ; LEDR[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V17 ; 154 ; 4A ; LEDR[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V18 ; 194 ; 4A ; LEDR[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W15 ; 130 ; 3B ; KEY[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W16 ; 136 ; 4A ; LEDR[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W17 ; 152 ; 4A ; LEDR[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W19 ; 192 ; 4A ; LEDR[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W20 ; 217 ; 5A ; LEDR[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W21 ; 221 ; 5A ; LEDR[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y16 ; 128 ; 3B ; KEY[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y19 ; 202 ; 4A ; LEDR[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y21 ; 219 ; 5A ; LEDR[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; Y23 ; 232 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y27 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings ;
++----------+--------------------------------------+
+; Pin Name ; Reason ;
++----------+--------------------------------------+
+; HEX0[0] ; Missing drive strength and slew rate ;
+; HEX0[1] ; Missing drive strength and slew rate ;
+; HEX0[2] ; Missing drive strength and slew rate ;
+; HEX0[3] ; Missing drive strength and slew rate ;
+; HEX0[4] ; Missing drive strength and slew rate ;
+; HEX0[5] ; Missing drive strength and slew rate ;
+; HEX0[6] ; Missing drive strength and slew rate ;
+; HEX1[0] ; Missing drive strength and slew rate ;
+; HEX1[1] ; Missing drive strength and slew rate ;
+; HEX1[2] ; Missing drive strength and slew rate ;
+; HEX1[3] ; Missing drive strength and slew rate ;
+; HEX1[4] ; Missing drive strength and slew rate ;
+; HEX1[5] ; Missing drive strength and slew rate ;
+; HEX1[6] ; Missing drive strength and slew rate ;
+; HEX2[0] ; Missing drive strength and slew rate ;
+; HEX2[1] ; Missing drive strength and slew rate ;
+; HEX2[2] ; Missing drive strength and slew rate ;
+; HEX2[3] ; Missing drive strength and slew rate ;
+; HEX2[4] ; Missing drive strength and slew rate ;
+; HEX2[5] ; Missing drive strength and slew rate ;
+; HEX2[6] ; Missing drive strength and slew rate ;
+; LEDR[0] ; Missing drive strength and slew rate ;
+; LEDR[1] ; Missing drive strength and slew rate ;
+; LEDR[2] ; Missing drive strength and slew rate ;
+; LEDR[3] ; Missing drive strength and slew rate ;
+; LEDR[4] ; Missing drive strength and slew rate ;
+; LEDR[5] ; Missing drive strength and slew rate ;
+; LEDR[6] ; Missing drive strength and slew rate ;
+; LEDR[7] ; Missing drive strength and slew rate ;
+; LEDR[8] ; Missing drive strength and slew rate ;
+; LEDR[9] ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+; |ex8 ; 75.5 (0.5) ; 78.5 (0.5) ; 3.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 136 (1) ; 75 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 36 ; 0 ; |ex8 ; ex8 ; work ;
+; |LFSR:LFSR0| ; 2.9 (2.9) ; 4.3 (4.3) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|LFSR:LFSR0 ; LFSR ; work ;
+; |bin2bcd_16:BCD| ; 6.1 (0.0) ; 6.7 (0.0) ; 0.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD ; bin2bcd_16 ; work ;
+; |add3_ge5:A22| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5 ; work ;
+; |add3_ge5:A26| ; 1.2 (1.2) ; 1.7 (1.7) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5 ; work ;
+; |add3_ge5:A30| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5 ; work ;
+; |add3_ge5:A34| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5 ; work ;
+; |add3_ge5:A35| ; 1.8 (1.8) ; 2.0 (2.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5 ; work ;
+; |delay:DEL0| ; 14.6 (14.6) ; 15.7 (15.7) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|delay:DEL0 ; delay ; work ;
+; |formula_fsm:FSM| ; 21.3 (21.3) ; 21.3 (21.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (37) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|formula_fsm:FSM ; formula_fsm ; work ;
+; |hex_to_7seg:SEG0| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG1| ; 7.2 (7.2) ; 7.5 (7.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
+; |tick_50000:TICK0| ; 18.5 (18.5) ; 19.0 (19.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (36) ; 25 (25) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex8|tick_50000:TICK0 ; tick_50000 ; work ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; KEY[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; KEY[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; KEY[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; KEY[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; CLOCK_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++-------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++-------------------------------------------------+-------------------+---------+
+; KEY[0] ; ; ;
+; KEY[1] ; ; ;
+; KEY[2] ; ; ;
+; KEY[3] ; ; ;
+; - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~1 ; 0 ; 0 ;
+; - formula_fsm:FSM|Selector2~0 ; 0 ; 0 ;
+; - formula_fsm:FSM|Selector3~0 ; 0 ; 0 ;
+; CLOCK_50 ; ; ;
+; - tick_50000:TICK0|CLK_OUT ; 0 ; 0 ;
++-------------------------------------------------+-------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 2 ; Clock ; no ; -- ; -- ; -- ;
+; CLOCK_50 ; PIN_AF14 ; 24 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ;
+; delay:DEL0|count[6]~0 ; LABCELL_X81_Y8_N48 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
+; delay:DEL0|state.COUNTING ; FF_X82_Y8_N29 ; 20 ; Sync. load ; no ; -- ; -- ; -- ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X81_Y6_N14 ; 22 ; Clock enable, Latch enable ; no ; -- ; -- ; -- ;
+; formula_fsm:FSM|state.WAIT_TRIGGER ; FF_X82_Y6_N41 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
+; tick_50000:TICK0|CLK_OUT ; FF_X81_Y4_N32 ; 50 ; Clock ; no ; -- ; -- ; -- ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 24 ; Global Clock ; GCLK6 ; -- ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type ; Usage ;
++---------------------------------------------+-------------------------+
+; Block interconnects ; 221 / 289,320 ( < 1 % ) ;
+; C12 interconnects ; 3 / 13,420 ( < 1 % ) ;
+; C2 interconnects ; 73 / 119,108 ( < 1 % ) ;
+; C4 interconnects ; 50 / 56,300 ( < 1 % ) ;
+; DQS bus muxes ; 0 / 25 ( 0 % ) ;
+; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
+; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
+; Direct links ; 38 / 289,320 ( < 1 % ) ;
+; Global clocks ; 1 / 16 ( 6 % ) ;
+; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
+; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
+; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
+; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
+; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
+; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
+; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
+; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
+; Local interconnects ; 68 / 84,580 ( < 1 % ) ;
+; Quadrant clocks ; 0 / 66 ( 0 % ) ;
+; R14 interconnects ; 34 / 12,676 ( < 1 % ) ;
+; R14/C12 interconnect drivers ; 34 / 20,720 ( < 1 % ) ;
+; R3 interconnects ; 127 / 130,992 ( < 1 % ) ;
+; R6 interconnects ; 106 / 266,960 ( < 1 % ) ;
+; Spine clocks ; 1 / 360 ( < 1 % ) ;
+; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary ;
++----------------------------------+-------+
+; I/O Rules Statistic ; Total ;
++----------------------------------+-------+
+; Total I/O Rules ; 28 ;
+; Number of I/O Rules Passed ; 6 ;
+; Number of I/O Rules Failed ; 0 ;
+; Number of I/O Rules Unchecked ; 0 ;
+; Number of I/O Rules Inapplicable ; 22 ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
+; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
+; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+; Pin/Rules ; IO_000002 ; IO_000003 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000022 ; IO_000021 ; IO_000046 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000047 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+; Total Pass ; 0 ; 36 ; 36 ; 0 ; 0 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 36 ; 36 ; 0 ;
+; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Inapplicable ; 36 ; 0 ; 0 ; 36 ; 36 ; 0 ; 0 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 36 ; 0 ; 0 ; 36 ;
+; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; KEY[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[9] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; KEY[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; CLOCK_50 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options ;
++------------------------------------------------------------------+-----------------------------+
+; Option ; Setting ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Passive Serial ;
+; Enable Error Detection CRC_ERROR pin ; Off ;
+; Enable CvP_CONFDONE pin ; Off ;
+; Enable open drain on CRC_ERROR pin ; On ;
+; Enable open drain on CvP_CONFDONE pin ; On ;
+; Enable open drain on INIT_DONE pin ; On ;
+; Enable open drain on Partial Reconfiguration pins ; Off ;
+; Enable open drain on nCEO pin ; On ;
+; Enable Partial Reconfiguration pins ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ;
+; Enable internal scrubbing ; Off ;
+; Active Serial clock source ; 100 MHz Internal Oscillator ;
+; Device initialization clock source ; Internal Oscillator ;
+; Configuration via Protocol ; Off ;
+; Configuration Voltage Level ; Auto ;
+; Force Configuration Voltage Level ; Off ;
+; Enable nCEO output ; Off ;
+; Data[15..8] ; Unreserved ;
+; Data[7..5] ; Unreserved ;
+; Base pin-out file on sameframe device ; Off ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.10 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary ;
++--------------------------------------------------------------+--------------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++--------------------------------------------------------------+--------------------------+-------------------+
+; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 68.7 ;
+; CLOCK_50 ; CLOCK_50 ; 14.9 ;
+; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 2.9 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 2.6 ;
++--------------------------------------------------------------+--------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++-----------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details ;
++----------------------------------------+----------------------------------------+-------------------+
+; Source Register ; Destination Register ; Delay Added in ns ;
++----------------------------------------+----------------------------------------+-------------------+
+; tick_50000:TICK0|count[5] ; tick_50000:TICK0|CLK_OUT ; 2.060 ;
+; tick_50000:TICK0|count[11] ; tick_50000:TICK0|CLK_OUT ; 2.035 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|ledr[1] ; 2.002 ;
+; tick_50000:TICK0|count[6] ; tick_50000:TICK0|CLK_OUT ; 1.958 ;
+; tick_50000:TICK0|count[3] ; tick_50000:TICK0|CLK_OUT ; 1.946 ;
+; tick_50000:TICK0|count[2] ; tick_50000:TICK0|CLK_OUT ; 1.935 ;
+; tick_50000:TICK0|count[12] ; tick_50000:TICK0|CLK_OUT ; 1.923 ;
+; tick_50000:TICK0|count[8] ; tick_50000:TICK0|CLK_OUT ; 1.920 ;
+; tick_50000:TICK0|count[13] ; tick_50000:TICK0|CLK_OUT ; 1.905 ;
+; tick_50000:TICK0|count[9] ; tick_50000:TICK0|CLK_OUT ; 1.903 ;
+; tick_50000:TICK0|count[4] ; tick_50000:TICK0|CLK_OUT ; 1.902 ;
+; tick_50000:TICK0|count[14] ; tick_50000:TICK0|CLK_OUT ; 1.881 ;
+; tick_50000:TICK0|count[7] ; tick_50000:TICK0|CLK_OUT ; 1.881 ;
+; tick_50000:TICK0|count[15] ; tick_50000:TICK0|CLK_OUT ; 1.878 ;
+; tick_50000:TICK0|count[10] ; tick_50000:TICK0|CLK_OUT ; 1.848 ;
+; tick_50000:TICK0|count[0] ; tick_50000:TICK0|CLK_OUT ; 1.847 ;
+; tick_50000:TICK0|count[1] ; tick_50000:TICK0|CLK_OUT ; 1.816 ;
+; formula_fsm:FSM|start_delay ; delay:DEL0|state.IDLE ; 1.356 ;
+; formula_fsm:FSM|count[6] ; formula_fsm:FSM|ledr[2] ; 1.043 ;
+; LFSR:LFSR0|COUNT[1] ; LFSR:LFSR0|COUNT[2] ; 0.981 ;
+; formula_fsm:FSM|ledr[6] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.937 ;
+; delay:DEL0|count[8] ; delay:DEL0|state.IDLE ; 0.932 ;
+; formula_fsm:FSM|count[2] ; formula_fsm:FSM|ledr[2] ; 0.928 ;
+; formula_fsm:FSM|ledr[8] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.926 ;
+; formula_fsm:FSM|count[1] ; formula_fsm:FSM|ledr[2] ; 0.924 ;
+; delay:DEL0|state.COUNTING ; delay:DEL0|state.IDLE ; 0.922 ;
+; delay:DEL0|count[6] ; delay:DEL0|state.IDLE ; 0.920 ;
+; delay:DEL0|count[2] ; delay:DEL0|state.IDLE ; 0.919 ;
+; delay:DEL0|count[3] ; delay:DEL0|state.IDLE ; 0.915 ;
+; formula_fsm:FSM|count[0] ; formula_fsm:FSM|ledr[2] ; 0.903 ;
+; formula_fsm:FSM|ledr[9] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.899 ;
+; formula_fsm:FSM|count[4] ; formula_fsm:FSM|ledr[2] ; 0.867 ;
+; delay:DEL0|count[10] ; delay:DEL0|state.IDLE ; 0.866 ;
+; formula_fsm:FSM|ledr[3] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.859 ;
+; delay:DEL0|count[4] ; delay:DEL0|state.IDLE ; 0.851 ;
+; formula_fsm:FSM|ledr[0] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.850 ;
+; formula_fsm:FSM|ledr[1] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.836 ;
+; formula_fsm:FSM|ledr[2] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.820 ;
+; formula_fsm:FSM|ledr[4] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.790 ;
+; formula_fsm:FSM|count[7] ; formula_fsm:FSM|ledr[2] ; 0.782 ;
+; formula_fsm:FSM|count[3] ; formula_fsm:FSM|ledr[2] ; 0.782 ;
+; formula_fsm:FSM|count[5] ; formula_fsm:FSM|ledr[2] ; 0.782 ;
+; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[2] ; 0.782 ;
+; formula_fsm:FSM|count[8] ; formula_fsm:FSM|ledr[2] ; 0.782 ;
+; delay:DEL0|count[7] ; delay:DEL0|state.IDLE ; 0.750 ;
+; delay:DEL0|state.WAIT_LOW ; delay:DEL0|state.IDLE ; 0.748 ;
+; delay:DEL0|count[11] ; delay:DEL0|state.IDLE ; 0.746 ;
+; delay:DEL0|count[5] ; delay:DEL0|state.IDLE ; 0.746 ;
+; LFSR:LFSR0|COUNT[3] ; LFSR:LFSR0|COUNT[4] ; 0.735 ;
+; LFSR:LFSR0|COUNT[5] ; LFSR:LFSR0|COUNT[6] ; 0.735 ;
+; delay:DEL0|count[0] ; delay:DEL0|state.IDLE ; 0.734 ;
+; delay:DEL0|count[1] ; delay:DEL0|state.IDLE ; 0.729 ;
+; formula_fsm:FSM|ledr[5] ; formula_fsm:FSM|ledr[6] ; 0.728 ;
+; LFSR:LFSR0|COUNT[4] ; LFSR:LFSR0|COUNT[5] ; 0.722 ;
+; LFSR:LFSR0|COUNT[6] ; LFSR:LFSR0|COUNT[7] ; 0.722 ;
+; formula_fsm:FSM|state.WAIT_TRIGGER ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.696 ;
+; delay:DEL0|count[9] ; delay:DEL0|state.IDLE ; 0.690 ;
+; delay:DEL0|state.TIME_OUT ; delay:DEL0|state.IDLE ; 0.671 ;
+; LFSR:LFSR0|COUNT[7] ; LFSR:LFSR0|COUNT[1] ; 0.649 ;
+; delay:DEL0|state.IDLE ; delay:DEL0|state.IDLE ; 0.638 ;
+; formula_fsm:FSM|ledr[7] ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.633 ;
+; delay:DEL0|count[13] ; delay:DEL0|state.TIME_OUT ; 0.631 ;
+; delay:DEL0|count[12] ; delay:DEL0|state.TIME_OUT ; 0.609 ;
+; LFSR:LFSR0|COUNT[2] ; LFSR:LFSR0|COUNT[3] ; 0.563 ;
+; tick_50000:TICK0|CLK_OUT ; delay:DEL0|count[0] ; 0.110 ;
+; KEY[3] ; formula_fsm:FSM|state.WAIT_TRIGGER ; 0.024 ;
++----------------------------------------+----------------------------------------+-------------------+
+Note: This table only shows the top 66 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex8"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+ Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176235): Finished register packing
+ Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+ Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:12
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
+Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:04
+Info (11888): Total time spent on timing analysis during the Fitter is 0.37 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:02
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 52 warnings
+ Info: Peak virtual memory: 2138 megabytes
+ Info: Processing ended: Sun Dec 11 20:25:36 2016
+ Info: Elapsed time: 00:00:32
+ Info: Total CPU time (on all processors): 00:00:57
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg.
+
+
diff --git a/part_2/ex8/output_files/ex8.fit.smsg b/part_2/ex8/output_files/ex8.fit.smsg
index 43eead5..9302919 100755
--- a/part_2/ex8/output_files/ex8.fit.smsg
+++ b/part_2/ex8/output_files/ex8.fit.smsg
@@ -1,6 +1,6 @@
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
-Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_2/ex8/output_files/ex8.fit.summary b/part_2/ex8/output_files/ex8.fit.summary
index 3ae19a5..4340a86 100755
--- a/part_2/ex8/output_files/ex8.fit.summary
+++ b/part_2/ex8/output_files/ex8.fit.summary
@@ -1,20 +1,20 @@
-Fitter Status : Successful - Wed Dec 07 12:22:02 2016
-Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex8
-Top-level Entity Name : ex8
-Family : Cyclone V
-Device : 5CSEMA5F31C6
-Timing Models : Final
-Logic utilization (in ALMs) : 79 / 32,070 ( < 1 % )
-Total registers : 84
-Total pins : 36 / 457 ( 8 % )
-Total virtual pins : 0
-Total block memory bits : 0 / 4,065,280 ( 0 % )
-Total RAM Blocks : 0 / 397 ( 0 % )
-Total DSP Blocks : 0 / 87 ( 0 % )
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0 / 6 ( 0 % )
-Total DLLs : 0 / 4 ( 0 % )
+Fitter Status : Successful - Sun Dec 11 20:25:36 2016
+Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Revision Name : ex8
+Top-level Entity Name : ex8
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 76 / 32,070 ( < 1 % )
+Total registers : 75
+Total pins : 36 / 457 ( 8 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_2/ex8/output_files/ex8.flow.rpt b/part_2/ex8/output_files/ex8.flow.rpt
index 8f0c739..0dd5be9 100755
--- a/part_2/ex8/output_files/ex8.flow.rpt
+++ b/part_2/ex8/output_files/ex8.flow.rpt
@@ -1,128 +1,128 @@
-Flow report for ex8
-Wed Dec 07 12:22:30 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Flow Summary ;
-+---------------------------------+-------------------------------------------------+
-; Flow Status ; Successful - Wed Dec 07 12:22:20 2016 ;
-; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name ; ex8 ;
-; Top-level Entity Name ; ex8 ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Logic utilization (in ALMs) ; 79 / 32,070 ( < 1 % ) ;
-; Total registers ; 84 ;
-; Total pins ; 36 / 457 ( 8 % ) ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
-; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 / 6 ( 0 % ) ;
-; Total DLLs ; 0 / 4 ( 0 % ) ;
-+---------------------------------+-------------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 12/07/2016 12:21:12 ;
-; Main task ; Compilation ;
-; Revision Name ; ex8 ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID ; 260248564297098.148111327202376 ; -- ; -- ; -- ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 895 MB ; 00:00:22 ;
-; Fitter ; 00:00:35 ; 1.0 ; 2608 MB ; 00:00:57 ;
-; Assembler ; 00:00:10 ; 1.0 ; 891 MB ; 00:00:06 ;
-; TimeQuest Timing Analyzer ; 00:00:09 ; 1.1 ; 1209 MB ; 00:00:06 ;
-; Total ; 00:01:06 ; -- ; -- ; 00:01:31 ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Analysis & Synthesis ; eews104a-017 ; Windows 7 ; 6.1 ; x86_64 ;
-; Fitter ; eews104a-017 ; Windows 7 ; 6.1 ; x86_64 ;
-; Assembler ; eews104a-017 ; Windows 7 ; 6.1 ; x86_64 ;
-; TimeQuest Timing Analyzer ; eews104a-017 ; Windows 7 ; 6.1 ; x86_64 ;
-+---------------------------+------------------+-----------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8
-quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8
-quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8
-quartus_sta ex8 -c ex8
-
-
-
+Flow report for ex8
+Sun Dec 11 20:25:48 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+ 8. Flow Messages
+ 9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-------------------------------------------------------------------------------+
+; Flow Summary ;
++---------------------------------+---------------------------------------------+
+; Flow Status ; Successful - Sun Dec 11 20:25:43 2016 ;
+; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Revision Name ; ex8 ;
+; Top-level Entity Name ; ex8 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 76 / 32,070 ( < 1 % ) ;
+; Total registers ; 75 ;
+; Total pins ; 36 / 457 ( 8 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 12/11/2016 20:24:54 ;
+; Main task ; Compilation ;
+; Revision Name ; ex8 ;
++-------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 158515234070422.148148789408646 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
+; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 1012 MB ; 00:00:24 ;
+; Fitter ; 00:00:32 ; 1.0 ; 2138 MB ; 00:00:56 ;
+; Assembler ; 00:00:06 ; 1.0 ; 972 MB ; 00:00:06 ;
+; TimeQuest Timing Analyzer ; 00:00:05 ; 1.1 ; 1214 MB ; 00:00:05 ;
+; Total ; 00:00:53 ; -- ; -- ; 00:01:31 ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++-----------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++---------------------------+------------------+------------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++---------------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
+; Fitter ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
+; Assembler ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
+; TimeQuest Timing Analyzer ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
++---------------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8
+quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8
+quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8
+quartus_sta ex8 -c ex8
+
+
+
diff --git a/part_2/ex8/output_files/ex8.jdi b/part_2/ex8/output_files/ex8.jdi
index d856c57..a69b658 100755
--- a/part_2/ex8/output_files/ex8.jdi
+++ b/part_2/ex8/output_files/ex8.jdi
@@ -1,8 +1,8 @@
-<sld_project_info>
- <project>
- <hash md5_digest_80b="ebb09f580b225437ab24"/>
- </project>
- <file_info>
- <file device="5CSEMA5F31C6" path="ex8.sof" usercode="0xFFFFFFFF"/>
- </file_info>
-</sld_project_info>
+<sld_project_info>
+ <project>
+ <hash md5_digest_80b="226e380111dba8ff1ed0"/>
+ </project>
+ <file_info>
+ <file device="5CSEMA5F31C6" path="ex8.sof" usercode="0xFFFFFFFF"/>
+ </file_info>
+</sld_project_info>
diff --git a/part_2/ex8/output_files/ex8.map.rpt b/part_2/ex8/output_files/ex8.map.rpt
index ace9229..cf3e200 100755
--- a/part_2/ex8/output_files/ex8.map.rpt
+++ b/part_2/ex8/output_files/ex8.map.rpt
@@ -1,572 +1,573 @@
-Analysis & Synthesis report for ex8
-Wed Dec 07 12:21:24 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. State Machine - |ex8|delay:DEL0|state
- 9. State Machine - |ex8|formula_fsm:FSM|state
- 10. User-Specified and Inferred Latches
- 11. Registers Removed During Synthesis
- 12. General Register Statistics
- 13. Inverted Register Statistics
- 14. Multiplexer Restructuring Statistics (Restructuring Performed)
- 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
- 16. Parameter Settings for User Entity Instance: tick_2500:TICK1
- 17. Parameter Settings for User Entity Instance: formula_fsm:FSM
- 18. Parameter Settings for User Entity Instance: delay:DEL0
- 19. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
- 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
- 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
- 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
- 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
- 24. Port Connectivity Checks: "bin2bcd_16:BCD"
- 25. Port Connectivity Checks: "delay:DEL0"
- 26. Post-Synthesis Netlist Statistics for Top Partition
- 27. Elapsed Time Per Partition
- 28. Analysis & Synthesis Messages
- 29. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+---------------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Dec 07 12:21:23 2016 ;
-; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name ; ex8 ;
-; Top-level Entity Name ; ex8 ;
-; Family ; Cyclone V ;
-; Logic utilization (in ALMs) ; N/A ;
-; Total registers ; 67 ;
-; Total pins ; 36 ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 0 ;
-; Total DSP Blocks ; 0 ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 ;
-; Total DLLs ; 0 ;
-+---------------------------------+-------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Device ; 5CSEMA5F31C6 ; ;
-; Top-level entity name ; ex8 ; ex8 ;
-; Family name ; Cyclone V ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 3 ; 3 ;
-; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-; Synthesis Seed ; 1 ; 1 ;
-; Automatic Parallel Synthesis ; On ; On ;
-; Partial Reconfiguration Bitstream ID ; Off ; Off ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+---------+
-; verilog_files/tick_50000.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v ; ;
-; verilog_files/LFSR.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v ; ;
-; verilog_files/hex_to_7seg.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v ; ;
-; verilog_files/bin2bcd_16.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v ; ;
-; verilog_files/add3_ge5.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v ; ;
-; verilog_files/formula_fsm.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v ; ;
-; verilog_files/delay.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v ; ;
-; verilog_files/tick_2500.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v ; ;
-; verilog_files/ex8.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v ; ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+---------+
-
-
-+------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+--------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+--------------------------+
-; Estimate of Logic utilization (ALMs needed) ; 86 ;
-; ; ;
-; Combinational ALUT usage for logic ; 142 ;
-; -- 7 input functions ; 0 ;
-; -- 6 input functions ; 29 ;
-; -- 5 input functions ; 5 ;
-; -- 4 input functions ; 40 ;
-; -- <=3 input functions ; 68 ;
-; ; ;
-; Dedicated logic registers ; 67 ;
-; ; ;
-; I/O pins ; 36 ;
-; ; ;
-; Total DSP Blocks ; 0 ;
-; ; ;
-; Maximum fan-out node ; tick_50000:TICK0|CLK_OUT ;
-; Maximum fan-out ; 50 ;
-; Total fan-out ; 739 ;
-; Average fan-out ; 2.63 ;
-+---------------------------------------------+--------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex8 ; 142 (1) ; 67 (0) ; 0 ; 0 ; 36 ; 0 ; |ex8 ; ex8 ; work ;
-; |LFSR:LFSR0| ; 3 (3) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |ex8|LFSR:LFSR0 ; LFSR ; work ;
-; |bin2bcd_16:BCD| ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD ; bin2bcd_16 ; work ;
-; |add3_ge5:A22| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5 ; work ;
-; |add3_ge5:A26| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5 ; work ;
-; |add3_ge5:A30| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5 ; work ;
-; |add3_ge5:A35| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5 ; work ;
-; |delay:DEL0| ; 25 (25) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |ex8|delay:DEL0 ; delay ; work ;
-; |formula_fsm:FSM| ; 43 (43) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; |ex8|formula_fsm:FSM ; formula_fsm ; work ;
-; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG1| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG2| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
-; |tick_50000:TICK0| ; 36 (36) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex8|tick_50000:TICK0 ; tick_50000 ; work ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-Encoding Type: One-Hot
-+--------------------------------------------------------------------------------+
-; State Machine - |ex8|delay:DEL0|state ;
-+----------------+----------------+----------------+----------------+------------+
-; Name ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
-+----------------+----------------+----------------+----------------+------------+
-; state.IDLE ; 0 ; 0 ; 0 ; 0 ;
-; state.COUNTING ; 0 ; 0 ; 1 ; 1 ;
-; state.TIME_OUT ; 0 ; 1 ; 0 ; 1 ;
-; state.WAIT_LOW ; 1 ; 0 ; 0 ; 1 ;
-+----------------+----------------+----------------+----------------+------------+
-
-
-Encoding Type: One-Hot
-+--------------------------------------------------------------------------------------------+
-; State Machine - |ex8|formula_fsm:FSM|state ;
-+------------------------+--------------------+------------------------+---------------------+
-; Name ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
-+------------------------+--------------------+------------------------+---------------------+
-; state.WAIT_TRIGGER ; 0 ; 0 ; 0 ;
-; state.LIGHT_UP_LEDS ; 1 ; 0 ; 1 ;
-; state.WAIT_FOR_TIMEOUT ; 1 ; 1 ; 0 ;
-+------------------------+--------------------+------------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; User-Specified and Inferred Latches ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; formula_fsm:FSM|start_delay ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes ;
-; Number of user-specified and inferred latches = 1 ; ; ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
-
-
-+------------------------------------------------------------+
-; Registers Removed During Synthesis ;
-+---------------------------------------+--------------------+
-; Register name ; Reason for Removal ;
-+---------------------------------------+--------------------+
-; delay:DEL0|state~5 ; Lost fanout ;
-; delay:DEL0|state~6 ; Lost fanout ;
-; Total Number of Removed Registers = 2 ; ;
-+---------------------------------------+--------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 67 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 15 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 26 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+---------------------------------------------------+
-; Inverted Register Statistics ;
-+-----------------------------------------+---------+
-; Inverted Register ; Fan out ;
-+-----------------------------------------+---------+
-; LFSR:LFSR0|COUNT[1] ; 10 ;
-; tick_50000:TICK0|count[14] ; 2 ;
-; tick_50000:TICK0|count[15] ; 2 ;
-; tick_50000:TICK0|count[0] ; 2 ;
-; tick_50000:TICK0|count[1] ; 2 ;
-; tick_50000:TICK0|count[2] ; 2 ;
-; tick_50000:TICK0|count[3] ; 2 ;
-; tick_50000:TICK0|count[6] ; 2 ;
-; tick_50000:TICK0|count[8] ; 2 ;
-; tick_50000:TICK0|count[9] ; 2 ;
-; Total number of inverted registers = 10 ; ;
-+-----------------------------------------+---------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
-; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |ex8|formula_fsm:FSM|count[11] ;
-; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex8|delay:DEL0|count[0] ;
-; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex8|delay:DEL0|count[9] ;
-; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |ex8|formula_fsm:FSM|Selector3 ;
-; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |ex8|delay:DEL0|Selector15 ;
-; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |ex8|delay:DEL0|Selector14 ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
-
-
-+---------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
-+----------------+-------+--------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+--------------------------------------+
-; NBIT ; 16 ; Signed Integer ;
-+----------------+-------+--------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_2500:TICK1 ;
-+----------------+-------+-------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+-------------------------------------+
-; NBIT ; 12 ; Signed Integer ;
-+----------------+-------+-------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
-+------------------+-------+-----------------------------------+
-; Parameter Name ; Value ; Type ;
-+------------------+-------+-----------------------------------+
-; WAIT_TRIGGER ; 00 ; Unsigned Binary ;
-; LIGHT_UP_LEDS ; 01 ; Unsigned Binary ;
-; WAIT_FOR_TIMEOUT ; 10 ; Unsigned Binary ;
-+------------------+-------+-----------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------+
-; Parameter Settings for User Entity Instance: delay:DEL0 ;
-+----------------+-------+--------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+--------------------------------+
-; BIT_SZ ; 14 ; Signed Integer ;
-; IDLE ; 00 ; Unsigned Binary ;
-; COUNTING ; 01 ; Unsigned Binary ;
-; TIME_OUT ; 10 ; Unsigned Binary ;
-; WAIT_LOW ; 11 ; Unsigned Binary ;
-+----------------+-------+--------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31" ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-; oA[3] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
-+-------+-------+----------+------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
-+-------+-------+----------+------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+------------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
-+-------+-------+----------+-----------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+-----------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
-+-------+-------+----------+-----------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD" ;
-+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; B ; Input ; Warning ; Input port expression (7 bits) is smaller than the input port (16 bits) it drives. Extra input bit(s) "B[15..7]" will be connected to GND. ;
-; BCD_3 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; BCD_4 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "delay:DEL0" ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; N ; Input ; Warning ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives. Extra input bit(s) "N[13..7]" will be connected to GND. ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; arriav_ff ; 67 ;
-; ENA ; 12 ;
-; ENA SLD ; 14 ;
-; SLD ; 1 ;
-; plain ; 40 ;
-; arriav_lcell_comb ; 145 ;
-; arith ; 42 ;
-; 1 data inputs ; 42 ;
-; normal ; 103 ;
-; 0 data inputs ; 2 ;
-; 1 data inputs ; 13 ;
-; 2 data inputs ; 8 ;
-; 3 data inputs ; 6 ;
-; 4 data inputs ; 40 ;
-; 5 data inputs ; 5 ;
-; 6 data inputs ; 29 ;
-; boundary_port ; 36 ;
-; ; ;
-; Max LUT depth ; 6.00 ;
-; Average LUT depth ; 2.87 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
- Info: Processing started: Wed Dec 07 12:21:11 2016
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
- Info (12023): Found entity 1: tick_50000 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v
- Info (12023): Found entity 1: LFSR File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
- Info (12023): Found entity 1: hex_to_7seg File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
- Info (12023): Found entity 1: counter_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v Line: 3
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
- Info (12023): Found entity 1: bin2bcd_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 12
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
- Info (12023): Found entity 1: add3_ge5 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v Line: 9
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
- Info (12023): Found entity 1: formula_fsm File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
- Info (12023): Found entity 1: delay File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v
- Info (12023): Found entity 1: tick_2500 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex8.v
- Info (12023): Found entity 1: ex8 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 1
-Info (12127): Elaborating entity "ex8" for the top level hierarchy
-Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 13
-Info (12128): Elaborating entity "tick_2500" for hierarchy "tick_2500:TICK1" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 14
-Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 15
-Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 39
-Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
-Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
-Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 16
-Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 17
-Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 24
-Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 18
-Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 26
-Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 19
-Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
-Warning (13024): Output pins are stuck at VCC or GND
- Warning (13410): Pin "HEX2[1]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
- Warning (13410): Pin "HEX2[2]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
- Warning (13410): Pin "HEX2[6]" is stuck at VCC File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
-Info (286030): Timing-Driven Synthesis is running
-Info (17049): 2 registers lost all their fanouts during netlist optimizations.
-Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 3 input pin(s) that do not drive logic
- Warning (15610): No output dependent on input pin "KEY[0]" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
- Warning (15610): No output dependent on input pin "KEY[1]" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
- Warning (15610): No output dependent on input pin "KEY[2]" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
-Info (21057): Implemented 184 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 5 input pins
- Info (21059): Implemented 31 output pins
- Info (21061): Implemented 148 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
- Info: Peak virtual memory: 895 megabytes
- Info: Processing ended: Wed Dec 07 12:21:24 2016
- Info: Elapsed time: 00:00:13
- Info: Total CPU time (on all processors): 00:00:22
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg.
-
-
+Analysis & Synthesis report for ex8
+Sun Dec 11 20:25:03 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Source Files Read
+ 6. Analysis & Synthesis Resource Usage Summary
+ 7. Analysis & Synthesis Resource Utilization by Entity
+ 8. State Machine - |ex8|delay:DEL0|state
+ 9. State Machine - |ex8|formula_fsm:FSM|state
+ 10. User-Specified and Inferred Latches
+ 11. Registers Removed During Synthesis
+ 12. General Register Statistics
+ 13. Inverted Register Statistics
+ 14. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
+ 16. Parameter Settings for User Entity Instance: tick_2500:TICK1
+ 17. Parameter Settings for User Entity Instance: formula_fsm:FSM
+ 18. Parameter Settings for User Entity Instance: delay:DEL0
+ 19. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
+ 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
+ 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
+ 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
+ 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
+ 24. Port Connectivity Checks: "bin2bcd_16:BCD"
+ 25. Port Connectivity Checks: "delay:DEL0"
+ 26. Post-Synthesis Netlist Statistics for Top Partition
+ 27. Elapsed Time Per Partition
+ 28. Analysis & Synthesis Messages
+ 29. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++---------------------------------+---------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Sun Dec 11 20:25:03 2016 ;
+; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Revision Name ; ex8 ;
+; Top-level Entity Name ; ex8 ;
+; Family ; Cyclone V ;
+; Logic utilization (in ALMs) ; N/A ;
+; Total registers ; 64 ;
+; Total pins ; 36 ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 ;
+; Total DSP Blocks ; 0 ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++---------------------------------+---------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Top-level entity name ; ex8 ; ex8 ;
+; Family name ; Cyclone V ; Cyclone V ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; OpenCore Plus hardware evaluation ; Enable ; Enable ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Infer RAMs from Raw Logic ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; On ; On ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 3 ; 3 ;
+; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
+; Automatic Parallel Synthesis ; On ; On ;
+; Partial Reconfiguration Bitstream ID ; Off ; Off ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processors 2-4 ; 0.0% ;
++----------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
+; verilog_files/tick_50000.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v ; ;
+; verilog_files/LFSR.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v ; ;
+; verilog_files/hex_to_7seg.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v ; ;
+; verilog_files/bin2bcd_16.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v ; ;
+; verilog_files/add3_ge5.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v ; ;
+; verilog_files/formula_fsm.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v ; ;
+; verilog_files/delay.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v ; ;
+; verilog_files/tick_2500.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v ; ;
+; verilog_files/ex8.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v ; ;
++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
+
+
++------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+--------------------------+
+; Resource ; Usage ;
++---------------------------------------------+--------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 81 ;
+; ; ;
+; Combinational ALUT usage for logic ; 136 ;
+; -- 7 input functions ; 1 ;
+; -- 6 input functions ; 24 ;
+; -- 5 input functions ; 5 ;
+; -- 4 input functions ; 39 ;
+; -- <=3 input functions ; 67 ;
+; ; ;
+; Dedicated logic registers ; 64 ;
+; ; ;
+; I/O pins ; 36 ;
+; ; ;
+; Total DSP Blocks ; 0 ;
+; ; ;
+; Maximum fan-out node ; tick_50000:TICK0|CLK_OUT ;
+; Maximum fan-out ; 47 ;
+; Total fan-out ; 706 ;
+; Average fan-out ; 2.60 ;
++---------------------------------------------+--------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; |ex8 ; 136 (1) ; 64 (0) ; 0 ; 0 ; 36 ; 0 ; |ex8 ; ex8 ; work ;
+; |LFSR:LFSR0| ; 3 (3) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |ex8|LFSR:LFSR0 ; LFSR ; work ;
+; |bin2bcd_16:BCD| ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD ; bin2bcd_16 ; work ;
+; |add3_ge5:A22| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5 ; work ;
+; |add3_ge5:A26| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5 ; work ;
+; |add3_ge5:A30| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5 ; work ;
+; |add3_ge5:A34| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5 ; work ;
+; |add3_ge5:A35| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5 ; work ;
+; |delay:DEL0| ; 25 (25) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |ex8|delay:DEL0 ; delay ; work ;
+; |formula_fsm:FSM| ; 37 (37) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |ex8|formula_fsm:FSM ; formula_fsm ; work ;
+; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG1| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
+; |tick_50000:TICK0| ; 36 (36) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex8|tick_50000:TICK0 ; tick_50000 ; work ;
++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
+Encoding Type: One-Hot
++--------------------------------------------------------------------------------+
+; State Machine - |ex8|delay:DEL0|state ;
++----------------+----------------+----------------+----------------+------------+
+; Name ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
++----------------+----------------+----------------+----------------+------------+
+; state.IDLE ; 0 ; 0 ; 0 ; 0 ;
+; state.COUNTING ; 0 ; 0 ; 1 ; 1 ;
+; state.TIME_OUT ; 0 ; 1 ; 0 ; 1 ;
+; state.WAIT_LOW ; 1 ; 0 ; 0 ; 1 ;
++----------------+----------------+----------------+----------------+------------+
+
+
+Encoding Type: One-Hot
++--------------------------------------------------------------------------------------------+
+; State Machine - |ex8|formula_fsm:FSM|state ;
++------------------------+--------------------+------------------------+---------------------+
+; Name ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
++------------------------+--------------------+------------------------+---------------------+
+; state.WAIT_TRIGGER ; 0 ; 0 ; 0 ;
+; state.LIGHT_UP_LEDS ; 1 ; 0 ; 1 ;
+; state.WAIT_FOR_TIMEOUT ; 1 ; 1 ; 0 ;
++------------------------+--------------------+------------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; User-Specified and Inferred Latches ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; formula_fsm:FSM|start_delay ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes ;
+; Number of user-specified and inferred latches = 1 ; ; ;
++----------------------------------------------------+-------------------------------------+------------------------+
+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+
+
++------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++---------------------------------------+--------------------+
+; Register name ; Reason for Removal ;
++---------------------------------------+--------------------+
+; delay:DEL0|state~5 ; Lost fanout ;
+; delay:DEL0|state~6 ; Lost fanout ;
+; Total Number of Removed Registers = 2 ; ;
++---------------------------------------+--------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 64 ;
+; Number of registers using Synchronous Clear ; 0 ;
+; Number of registers using Synchronous Load ; 15 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 27 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++---------------------------------------------------+
+; Inverted Register Statistics ;
++-----------------------------------------+---------+
+; Inverted Register ; Fan out ;
++-----------------------------------------+---------+
+; LFSR:LFSR0|COUNT[1] ; 10 ;
+; tick_50000:TICK0|count[14] ; 2 ;
+; tick_50000:TICK0|count[15] ; 2 ;
+; tick_50000:TICK0|count[0] ; 2 ;
+; tick_50000:TICK0|count[1] ; 2 ;
+; tick_50000:TICK0|count[2] ; 2 ;
+; tick_50000:TICK0|count[3] ; 2 ;
+; tick_50000:TICK0|count[6] ; 2 ;
+; tick_50000:TICK0|count[8] ; 2 ;
+; tick_50000:TICK0|count[9] ; 2 ;
+; Total number of inverted registers = 10 ; ;
++-----------------------------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |ex8|formula_fsm:FSM|count[4] ;
+; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex8|delay:DEL0|count[6] ;
+; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex8|delay:DEL0|count[7] ;
+; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |ex8|formula_fsm:FSM|Selector4 ;
+; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |ex8|delay:DEL0|Selector16 ;
+; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |ex8|delay:DEL0|Selector17 ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+
+
++---------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
++----------------+-------+--------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------------+
+; NBIT ; 16 ; Signed Integer ;
++----------------+-------+--------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_2500:TICK1 ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+-------------------------------------+
+; NBIT ; 12 ; Signed Integer ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
++------------------+-------+-----------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------+-------+-----------------------------------+
+; WAIT_TRIGGER ; 00 ; Unsigned Binary ;
+; LIGHT_UP_LEDS ; 01 ; Unsigned Binary ;
+; WAIT_FOR_TIMEOUT ; 10 ; Unsigned Binary ;
++------------------+-------+-----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------+
+; Parameter Settings for User Entity Instance: delay:DEL0 ;
++----------------+-------+--------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------+
+; BIT_SZ ; 14 ; Signed Integer ;
+; IDLE ; 00 ; Unsigned Binary ;
+; COUNTING ; 01 ; Unsigned Binary ;
+; TIME_OUT ; 10 ; Unsigned Binary ;
+; WAIT_LOW ; 11 ; Unsigned Binary ;
++----------------+-------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31" ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
+; oA[3] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
++-------+-------+----------+------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
++-------+-------+----------+------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
++-------+-------+----------+-----------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+-----------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
++-------+-------+----------+-----------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+-----------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD" ;
++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; B ; Input ; Warning ; Input port expression (7 bits) is smaller than the input port (16 bits) it drives. Extra input bit(s) "B[15..7]" will be connected to GND. ;
+; BCD_3 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; BCD_4 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "delay:DEL0" ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; N ; Input ; Warning ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives. Extra input bit(s) "N[13..7]" will be connected to GND. ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type ; Count ;
++-----------------------+-----------------------------+
+; arriav_ff ; 64 ;
+; ENA ; 13 ;
+; ENA SLD ; 14 ;
+; SLD ; 1 ;
+; plain ; 36 ;
+; arriav_lcell_comb ; 140 ;
+; arith ; 39 ;
+; 1 data inputs ; 39 ;
+; extend ; 1 ;
+; 7 data inputs ; 1 ;
+; normal ; 100 ;
+; 0 data inputs ; 2 ;
+; 1 data inputs ; 14 ;
+; 2 data inputs ; 9 ;
+; 3 data inputs ; 7 ;
+; 4 data inputs ; 39 ;
+; 5 data inputs ; 5 ;
+; 6 data inputs ; 24 ;
+; boundary_port ; 36 ;
+; ; ;
+; Max LUT depth ; 6.00 ;
+; Average LUT depth ; 2.82 ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top ; 00:00:00 ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+ Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+ Info: Processing started: Sun Dec 11 20:24:53 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
+ Info (12023): Found entity 1: tick_50000 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/LFSR.v
+ Info (12023): Found entity 1: LFSR File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+ Info (12023): Found entity 1: hex_to_7seg File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
+ Info (12023): Found entity 1: counter_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v Line: 3
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+ Info (12023): Found entity 1: bin2bcd_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+ Info (12023): Found entity 1: add3_ge5 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
+ Info (12023): Found entity 1: formula_fsm File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
+ Info (12023): Found entity 1: delay File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v
+ Info (12023): Found entity 1: tick_2500 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex8.v
+ Info (12023): Found entity 1: ex8 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 1
+Info (12127): Elaborating entity "ex8" for the top level hierarchy
+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 13
+Info (12128): Elaborating entity "tick_2500" for hierarchy "tick_2500:TICK1" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 14
+Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 15
+Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 39
+Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
+Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
+Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 16
+Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 17
+Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 24
+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 18
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 26
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 19
+Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+ Warning (13410): Pin "HEX2[1]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
+ Warning (13410): Pin "HEX2[2]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
+ Warning (13410): Pin "HEX2[6]" is stuck at VCC File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 2 registers lost all their fanouts during netlist optimizations.
+Info (144001): Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+ Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 3 input pin(s) that do not drive logic
+ Warning (15610): No output dependent on input pin "KEY[0]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
+ Warning (15610): No output dependent on input pin "KEY[1]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
+ Warning (15610): No output dependent on input pin "KEY[2]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
+Info (21057): Implemented 178 device resources after synthesis - the final resource count might be different
+ Info (21058): Implemented 5 input pins
+ Info (21059): Implemented 31 output pins
+ Info (21061): Implemented 142 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
+ Info: Peak virtual memory: 1054 megabytes
+ Info: Processing ended: Sun Dec 11 20:25:03 2016
+ Info: Elapsed time: 00:00:10
+ Info: Total CPU time (on all processors): 00:00:24
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg.
+
+
diff --git a/part_2/ex8/output_files/ex8.map.smsg b/part_2/ex8/output_files/ex8.map.smsg
index c655eb9..79c40b9 100755
--- a/part_2/ex8/output_files/ex8.map.smsg
+++ b/part_2/ex8/output_files/ex8.map.smsg
@@ -1,37 +1,37 @@
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 38
-Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 38
+Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 7
diff --git a/part_2/ex8/output_files/ex8.map.summary b/part_2/ex8/output_files/ex8.map.summary
index 00a2e0f..f52138b 100755
--- a/part_2/ex8/output_files/ex8.map.summary
+++ b/part_2/ex8/output_files/ex8.map.summary
@@ -1,17 +1,17 @@
-Analysis & Synthesis Status : Successful - Wed Dec 07 12:21:23 2016
-Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex8
-Top-level Entity Name : ex8
-Family : Cyclone V
-Logic utilization (in ALMs) : N/A
-Total registers : 67
-Total pins : 36
-Total virtual pins : 0
-Total block memory bits : 0
-Total DSP Blocks : 0
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0
-Total DLLs : 0
+Analysis & Synthesis Status : Successful - Sun Dec 11 20:25:03 2016
+Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Revision Name : ex8
+Top-level Entity Name : ex8
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 64
+Total pins : 36
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_2/ex8/output_files/ex8.pin b/part_2/ex8/output_files/ex8.pin
index 7f57443..4e698e3 100755
--- a/part_2/ex8/output_files/ex8.pin
+++ b/part_2/ex8/output_files/ex8.pin
@@ -1,976 +1,977 @@
- -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
- -- Your use of Altera Corporation's design tools, logic functions
- -- and other software and tools, and its AMPP partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Altera Program License
- -- Subscription Agreement, the Altera Quartus Prime License Agreement,
- -- the Altera MegaCore Function License Agreement, or other
- -- applicable license agreement, including, without limitation,
- -- that your use is for the sole purpose of programming logic
- -- devices manufactured by Altera and sold by Altera or its
- -- authorized distributors. Please refer to the applicable
- -- agreement for further details.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 3A: 2.5V
- -- Bank 3B: 3.3V
- -- Bank 4A: 3.3V
- -- Bank 5A: 3.3V
- -- Bank 5B: 3.3V
- -- Bank 6B: 2.5V
- -- Bank 6A: 2.5V
- -- Bank 7A: 2.5V
- -- Bank 7B: 2.5V
- -- Bank 7C: 2.5V
- -- Bank 7D: 2.5V
- -- Bank 8A: 2.5V
- -- RREF : External reference resistor for the quad, MUST be connected to
- -- GND via a 2k Ohm resistor.
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
- -- must not be connected.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-CHIP "ex8" ASSIGNED TO AN: 5CSEMA5F31C6
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND : A2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A :
-VCCIO8A : A7 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A :
-GND : A12 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C :
-GND : A17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B :
-GND : A22 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A :
-GND : A26 : : : : 7A :
-GND : A27 : gnd : : : :
-HPS_TRST : A28 : : : : 7A :
-HPS_TMS : A29 : : : : 7A :
-GND : AA1 : gnd : : : :
-GND : AA2 : gnd : : : :
-GND : AA3 : gnd : : : :
-GND : AA4 : gnd : : : :
-VCC : AA5 : power : : 1.1V : :
-GND : AA6 : gnd : : : :
-DNU : AA7 : : : : :
-VCCA_FPLL : AA8 : power : : 2.5V : :
-GND : AA9 : gnd : : : :
-VCCPD3A : AA10 : power : : 2.5V : 3A :
-GND : AA11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3B :
-KEY[0] : AA14 : input : 3.3-V LVTTL : : 3B : Y
-KEY[1] : AA15 : input : 3.3-V LVTTL : : 3B : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
-VCCIO4A : AA17 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
-GND : AA22 : gnd : : : :
-VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
-VCCIO5B : AA27 : power : : 3.3V : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 5B :
-VREFB5BN0 : AA29 : power : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B :
-GND : AB1 : gnd : : : :
-GND : AB2 : gnd : : : :
-DNU : AB3 : : : : :
-DNU : AB4 : : : : :
-GND : AB5 : gnd : : : :
-VCCA_FPLL : AB6 : power : : 2.5V : :
-GND : AB7 : gnd : : : :
-nCSO, DATA4 : AB8 : : : : 3A :
-TDO : AB9 : output : : : 3A :
-VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : :
-VCC_AUX : AB11 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B :
-VCCIO3B : AB14 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B :
-VCC_AUX : AB16 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
-VCCPD3B4A : AB18 : power : : 3.3V : 3B, 4A :
-GND : AB19 : gnd : : : :
-VCCPD3B4A : AB20 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 5A :
-HEX2[0] : AB23 : output : 3.3-V LVTTL : : 5A : Y
-VCCIO5A : AB24 : power : : 3.3V : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB28 : : : : 5B :
-GND : AB29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B :
-GND : AC1 : gnd : : : :
-GND : AC2 : gnd : : : :
-GND : AC3 : gnd : : : :
-GND : AC4 : gnd : : : :
-TCK : AC5 : input : : : 3A :
-GND : AC6 : gnd : : : :
-AS_DATA3, DATA3 : AC7 : : : : 3A :
-GND : AC8 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3A :
-VCCPD3A : AC10 : power : : 2.5V : 3A :
-VCCIO3A : AC11 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3A :
-VCCPD3B4A : AC13 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3B :
-VCCPD3B4A : AC15 : power : : 3.3V : 3B, 4A :
-GND : AC16 : gnd : : : :
-VCCPD3B4A : AC17 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
-VCCPD3B4A : AC19 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
-VCCIO4A : AC21 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
-VREFB5AN0 : AC24 : power : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5A :
-GND : AC26 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5A :
-HEX2[3] : AC28 : output : 3.3-V LVTTL : : 5B : Y
-HEX2[5] : AC29 : output : 3.3-V LVTTL : : 5B : Y
-HEX2[6] : AC30 : output : 3.3-V LVTTL : : 5B : Y
-GND : AD1 : gnd : : : :
-GND : AD2 : gnd : : : :
-DNU : AD3 : : : : :
-DNU : AD4 : : : : :
-GND : AD5 : gnd : : : :
-VREFB3AN0 : AD6 : power : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
-VCCIO3A : AD8 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3A :
-VCCIO3B : AD13 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B :
-DNU : AD15 : : : : :
-VCCPD3B4A : AD16 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
-VCCIO4A : AD18 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
-VCC_AUX : AD22 : power : : 2.5V : :
-GND : AD23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5A :
-HEX1[6] : AD27 : output : 3.3-V LVTTL : : 5A : Y
-VCCIO5A : AD28 : power : : 3.3V : 5A :
-HEX2[2] : AD29 : output : 3.3-V LVTTL : : 5B : Y
-HEX2[4] : AD30 : output : 3.3-V LVTTL : : 5B : Y
-GND : AE1 : gnd : : : :
-GND : AE2 : gnd : : : :
-GND : AE3 : gnd : : : :
-GND : AE4 : gnd : : : :
-AS_DATA1, DATA1 : AE5 : : : : 3A :
-AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3A :
-AS_DATA2, DATA2 : AE8 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3A :
-GND : AE10 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B :
-VCCIO3B : AE15 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
-GND : AE20 : gnd : : : :
-VCCPD3B4A : AE21 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
-VCCIO4A : AE25 : power : : 3.3V : 4A :
-HEX0[0] : AE26 : output : 3.3-V LVTTL : : 5A : Y
-HEX0[1] : AE27 : output : 3.3-V LVTTL : : 5A : Y
-HEX0[2] : AE28 : output : 3.3-V LVTTL : : 5A : Y
-HEX2[1] : AE29 : output : 3.3-V LVTTL : : 5B : Y
-VCCIO5B : AE30 : power : : 3.3V : 5B :
-GND : AF1 : gnd : : : :
-GND : AF2 : gnd : : : :
-GND : AF3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A :
-VCCIO3A : AF7 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
-GND : AF12 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B :
-CLOCK_50 : AF14 : input : 3.3-V LVTTL : : 3B : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
-GND : AF17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
-VCCIO4A : AF22 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A :
-GND : AF27 : gnd : : : :
-HEX0[4] : AF28 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[4] : AF29 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[5] : AF30 : output : 3.3-V LVTTL : : 5A : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A :
-VCCIO3A : AG4 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3A :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B :
-GND : AG14 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
-VCCIO4A : AG19 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
-HEX0[3] : AG27 : output : 3.3-V LVTTL : : 5A : Y
-HEX0[5] : AG28 : output : 3.3-V LVTTL : : 5A : Y
-VCCIO5A : AG29 : power : : 3.3V : 5A :
-HEX1[3] : AG30 : output : 3.3-V LVTTL : : 5A : Y
-GND : AH1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A :
-GND : AH6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3B :
-GND : AH11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH15 : : : : 3B :
-VCCIO4A : AH16 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A :
-GND : AH21 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4A :
-VCCIO4A : AH26 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
-HEX0[6] : AH28 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[1] : AH29 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[2] : AH30 : output : 3.3-V LVTTL : : 5A : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2 : : : : 3A :
-GND : AJ3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B :
-VCCIO3B : AJ8 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B :
-VCCIO3B : AJ13 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B :
-VREFB3BN0 : AJ15 : power : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A :
-GND : AJ18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 4A :
-VCCIO4A : AJ23 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A :
-GND : AJ28 : gnd : : : :
-HEX1[0] : AJ29 : output : 3.3-V LVTTL : : 5A : Y
-GND : AJ30 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK4 : : : : 3B :
-GND : AK5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B :
-VCCIO3B : AK10 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B :
-GND : AK15 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A :
-VREFB4AN0 : AK17 : power : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A :
-VCCIO4A : AK20 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A :
-GND : AK25 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK29 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A :
-VCCIO8A : B4 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A :
-GND : B9 : gnd : : : :
-VREFB8AN0 : B10 : power : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A :
-GND : B14 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B :
-GND : B19 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A :
-HPS_TDI : B27 : : : : 7A :
-HPS_TDO : B28 : : : : 7A :
-GND : B29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A :
-GND : C6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A :
-VCCIO8A : C11 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D :
-GND : C16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B :
-GND : C21 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A :
-GND : C26 : gnd : : : :
-HPS_nRST : C27 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
-VCCIO8A : D8 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
-GND : D13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C :
-VCCIO7C_HPS : D18 : power : : 2.5V : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A :
-GND : D23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A :
-HPS_CLK1 : D25 : : : : 7A :
-GND : D26 : : : : 7A :
-HPS_RZQ_0 : D27 : : : : 6A :
-VCCIO6A_HPS : D28 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A :
-VCCIO8A : E5 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
-GND : E10 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D :
-VCCIO7D_HPS : E15 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B :
-VCCIO7B_HPS : E20 : power : : 2.5V : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B :
-VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A :
-GND : E25 : gnd : : : :
-DNU : E26 : : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A :
-GND : E30 : gnd : : : :
-DNU : F1 : : : : :
-GND : F2 : gnd : : : :
-CONF_DONE : F3 : : : : 9A :
-nSTATUS : F4 : : : : 9A :
-GND : F5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
-GND : F7 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A :
-VCCIO8A : F12 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D :
-GND : F17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B :
-VCCIO7A_HPS : F22 : power : : 2.5V : 7A :
-HPS_nPOR : F23 : : : : 7A :
-HPS_PORSEL : F24 : : : : 7A :
-HPS_CLK2 : F25 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
-GND : F27 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A :
-GND : G1 : : : : :
-DNU : G2 : : : : :
-GND : G3 : gnd : : : :
-GND : G4 : gnd : : : :
-nCE : G5 : : : : 9A :
-MSEL2 : G6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8A :
-VCCIO8A : G9 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A :
-VCCIO8A : G14 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C :
-VCCIO7B_HPS : G19 : power : : 2.5V : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A :
-VCCRSTCLK_HPS : G23 : : : : 7A :
-GND : G24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
-VCCIO6A_HPS : G29 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A :
-GND : H1 : gnd : : : :
-GND : H2 : gnd : : : :
-DNU : H3 : : : : :
-DNU : H4 : : : : :
-GND : H5 : gnd : : : :
-VCCIO8A : H6 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
-VCCBAT : H9 : power : : 1.2V : :
-VCC_AUX : H10 : power : : 2.5V : :
-GND : H11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A :
-VCCIO7D_HPS : H16 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A :
-VCCIO7A_HPS : H21 : power : : 2.5V : 7A :
-HPS_TCK : H22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
-VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A :
-GND : J1 : gnd : : : :
-GND : J2 : gnd : : : :
-GND : J3 : gnd : : : :
-GND : J4 : gnd : : : :
-nCONFIG : J5 : : : : 9A :
-GND : J6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
-GND : J8 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
-VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A :
-VCCIO8A : J13 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8A :
-DNU : J15 : : : : :
-VCC_AUX : J16 : power : : 2.5V : :
-VCCPD7C_HPS : J17 : power : : 2.5V : 7C :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B :
-VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : :
-VCC_AUX_SHARED : J21 : power : : 2.5V : :
-GND : J22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
-GND : J28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A :
-GND : K1 : gnd : : : :
-GND : K2 : gnd : : : :
-DNU : K3 : : : : :
-DNU : K4 : : : : :
-GND : K5 : gnd : : : :
-MSEL1 : K6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
-VCCA_FPLL : K9 : power : : 2.5V : :
-GND : K10 : gnd : : : :
-VCCPD8A : K11 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 8A :
-VCCPD8A : K13 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A :
-GND : K15 : gnd : : : :
-VCCPD7D_HPS : K16 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B :
-VCCPD7B_HPS : K18 : power : : 2.5V : 7B :
-VCCPD7A_HPS : K19 : power : : 2.5V : 7A :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
-VCCIO6A_HPS : K24 : power : : 2.5V : 6A :
-GND : K25 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A :
-VCCIO6A_HPS : K30 : power : : 2.5V : 6A :
-GND : L1 : gnd : : : :
-GND : L2 : gnd : : : :
-GND : L3 : gnd : : : :
-GND : L4 : gnd : : : :
-VCC : L5 : power : : 1.1V : :
-GND : L6 : gnd : : : :
-MSEL3 : L7 : : : : 9A :
-MSEL0 : L8 : : : : 9A :
-MSEL4 : L9 : : : : 9A :
-VCCPD8A : L10 : power : : 2.5V : 8A :
-GND : L11 : gnd : : : :
-VCCPD8A : L12 : power : : 2.5V : 8A :
-GND : L13 : gnd : : : :
-VCCPD8A : L14 : power : : 2.5V : 8A :
-GND : L15 : gnd : : : :
-VCC_HPS : L16 : power : : 1.1V : :
-GND : L17 : gnd : : : :
-VCC_HPS : L18 : power : : 1.1V : :
-GND : L19 : gnd : : : :
-VCC_HPS : L20 : power : : 1.1V : :
-VCCPLL_HPS : L21 : power : : 2.5V : :
-GND : L22 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A :
-VCCIO6A_HPS : L27 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A :
-GND : M1 : gnd : : : :
-GND : M2 : gnd : : : :
-DNU : M3 : : : : :
-DNU : M4 : : : : :
-GND : M5 : gnd : : : :
-VCC : M6 : power : : 1.1V : :
-GND : M7 : gnd : : : :
-GND : M8 : gnd : : : :
-VCC : M9 : power : : 1.1V : :
-GND : M10 : gnd : : : :
-VCC : M11 : power : : 1.1V : :
-GND : M12 : gnd : : : :
-VCC : M13 : power : : 1.1V : :
-GND : M14 : gnd : : : :
-VCC_HPS : M15 : power : : 1.1V : :
-GND : M16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D :
-GND : M18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A :
-GND : M20 : gnd : : : :
-VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A :
-VCCIO6A_HPS : M24 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
-GND : M29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A :
-GND : N1 : gnd : : : :
-GND : N2 : gnd : : : :
-GND : N3 : gnd : : : :
-GND : N4 : gnd : : : :
-VCC : N5 : power : : 1.1V : :
-GND : N6 : gnd : : : :
-VCCA_FPLL : N7 : power : : 2.5V : :
-GND : N8 : gnd : : : :
-GND : N9 : gnd : : : :
-VCC : N10 : power : : 1.1V : :
-GND : N11 : gnd : : : :
-VCC : N12 : power : : 1.1V : :
-GND : N13 : gnd : : : :
-VCC : N14 : power : : 1.1V : :
-GND : N15 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D :
-GND : N17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A :
-GND : N19 : gnd : : : :
-VCC_HPS : N20 : power : : 1.1V : :
-VCCIO6A_HPS : N21 : power : : 2.5V : 6A :
-VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A :
-GND : N26 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B :
-GND : P1 : gnd : : : :
-GND : P2 : gnd : : : :
-DNU : P3 : : : : :
-DNU : P4 : : : : :
-GND : P5 : gnd : : : :
-VCCA_FPLL : P6 : power : : 2.5V : :
-GND : P7 : gnd : : : :
-GND : P8 : gnd : : : :
-GND : P9 : gnd : : : :
-GND : P10 : gnd : : : :
-VCC : P11 : power : : 1.1V : :
-GND : P12 : gnd : : : :
-VCC : P13 : power : : 1.1V : :
-GND : P14 : gnd : : : :
-VCC_HPS : P15 : power : : 1.1V : :
-GND : P16 : gnd : : : :
-VCC_HPS : P17 : power : : 1.1V : :
-GND : P18 : gnd : : : :
-VCC_HPS : P19 : power : : 1.1V : :
-GND : P20 : gnd : : : :
-VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B :
-VCCIO6B_HPS : P23 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B :
-VCCIO6B_HPS : P28 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B :
-GND : R1 : gnd : : : :
-GND : R2 : gnd : : : :
-GND : R3 : gnd : : : :
-GND : R4 : gnd : : : :
-VCC : R5 : power : : 1.1V : :
-GND : R6 : gnd : : : :
-VCCA_FPLL : R7 : power : : 2.5V : :
-GND : R8 : gnd : : : :
-GND : R9 : gnd : : : :
-VCC : R10 : power : : 1.1V : :
-GND : R11 : gnd : : : :
-VCC : R12 : power : : 1.1V : :
-GND : R13 : gnd : : : :
-VCC : R14 : power : : 1.1V : :
-GND : R15 : gnd : : : :
-VCC_HPS : R16 : power : : 1.1V : :
-GND : R17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B :
-VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B :
-VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
-VCCIO6B_HPS : R25 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B :
-GND : R30 : gnd : : : :
-GND : T1 : gnd : : : :
-GND : T2 : gnd : : : :
-DNU : T3 : : : : :
-DNU : T4 : : : : :
-GND : T5 : gnd : : : :
-VCC : T6 : power : : 1.1V : :
-GND : T7 : gnd : : : :
-GND : T8 : gnd : : : :
-GND : T9 : gnd : : : :
-GND : T10 : gnd : : : :
-VCC : T11 : power : : 1.1V : :
-GND : T12 : gnd : : : :
-VCC : T13 : power : : 1.1V : :
-GND : T14 : gnd : : : :
-GND : T15 : gnd : : : :
-GND : T16 : gnd : : : :
-VCC_HPS : T17 : power : : 1.1V : :
-GND : T18 : gnd : : : :
-VCC_HPS : T19 : power : : 1.1V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B :
-VCCIO6B_HPS : T22 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
-GND : T27 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B :
-GND : U1 : gnd : : : :
-GND : U2 : gnd : : : :
-GND : U3 : gnd : : : :
-GND : U4 : gnd : : : :
-VCC : U5 : power : : 1.1V : :
-GND : U6 : gnd : : : :
-DCLK : U7 : : : : 3A :
-TDI : U8 : input : : : 3A :
-GND : U9 : gnd : : : :
-VCC : U10 : power : : 1.1V : :
-GND : U11 : gnd : : : :
-VCC : U12 : power : : 1.1V : :
-GND : U13 : gnd : : : :
-VCC : U14 : power : : 1.1V : :
-GND : U15 : gnd : : : :
-VCC_HPS : U16 : power : : 1.1V : :
-GND : U17 : gnd : : : :
-VCC_HPS : U18 : power : : 1.1V : :
-VCCIO6B_HPS : U19 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B :
-VCC : U21 : power : : 1.1V : :
-GND : U22 : gnd : : : :
-VCCPD5B : U23 : power : : 3.3V : 5B :
-GND : U24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
-GND : U29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B :
-GND : V1 : gnd : : : :
-GND : V2 : gnd : : : :
-DNU : V3 : : : : :
-DNU : V4 : : : : :
-GND : V5 : gnd : : : :
-VCCA_FPLL : V6 : power : : 2.5V : :
-GND : V7 : gnd : : : :
-VCCA_FPLL : V8 : power : : 2.5V : :
-TMS : V9 : input : : : 3A :
-GND : V10 : gnd : : : :
-VCC : V11 : power : : 1.1V : :
-GND : V12 : gnd : : : :
-VCC : V13 : power : : 1.1V : :
-GND : V14 : gnd : : : :
-VCC : V15 : power : : 1.1V : :
-LEDR[0] : V16 : output : 3.3-V LVTTL : : 4A : Y
-LEDR[2] : V17 : output : 3.3-V LVTTL : : 4A : Y
-LEDR[3] : V18 : output : 3.3-V LVTTL : : 4A : Y
-GND : V19 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
-GND : V21 : gnd : : : :
-VCCPD5A : V22 : power : : 3.3V : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5A :
-VCCPD5A : V24 : power : : 3.3V : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
-VCCIO6B_HPS : V26 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B :
-GND : W1 : gnd : : : :
-GND : W2 : gnd : : : :
-GND : W3 : gnd : : : :
-GND : W4 : gnd : : : :
-VCC : W5 : power : : 1.1V : :
-GND : W6 : gnd : : : :
-GND : W7 : gnd : : : :
-GND : W8 : gnd : : : :
-GND : W9 : gnd : : : :
-VCC : W10 : power : : 1.1V : :
-GND : W11 : gnd : : : :
-VCC : W12 : power : : 1.1V : :
-GND : W13 : gnd : : : :
-VCC : W14 : power : : 1.1V : :
-KEY[2] : W15 : input : 3.3-V LVTTL : : 3B : Y
-LEDR[1] : W16 : output : 3.3-V LVTTL : : 4A : Y
-LEDR[4] : W17 : output : 3.3-V LVTTL : : 4A : Y
-GND : W18 : gnd : : : :
-LEDR[5] : W19 : output : 3.3-V LVTTL : : 4A : Y
-LEDR[7] : W20 : output : 3.3-V LVTTL : : 5A : Y
-LEDR[8] : W21 : output : 3.3-V LVTTL : : 5A : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5A :
-VCCIO5A : W23 : power : : 3.3V : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W24 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B :
-GND : W28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B :
-GND : Y1 : gnd : : : :
-GND : Y2 : gnd : : : :
-DNU : Y3 : : : : :
-DNU : Y4 : : : : :
-GND : Y5 : gnd : : : :
-VCC : Y6 : power : : 1.1V : :
-GND : Y7 : gnd : : : :
-GND : Y8 : gnd : : : :
-VCC : Y9 : power : : 1.1V : :
-GND : Y10 : gnd : : : :
-VCC : Y11 : power : : 1.1V : :
-GND : Y12 : gnd : : : :
-VCC : Y13 : power : : 1.1V : :
-GND : Y14 : gnd : : : :
-GND : Y15 : gnd : : : :
-KEY[3] : Y16 : input : 3.3-V LVTTL : : 3B : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
-LEDR[6] : Y19 : output : 3.3-V LVTTL : : 4A : Y
-GND : Y20 : gnd : : : :
-LEDR[9] : Y21 : output : 3.3-V LVTTL : : 5A : Y
-VCCA_FPLL : Y22 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A :
-GND : Y25 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B :
-GND : Y30 : gnd : : : :
+ -- Copyright (C) 2016 Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Intel Program License
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel MegaCore Function License Agreement, or other
+ -- applicable license agreement, including, without limitation,
+ -- that your use is for the sole purpose of programming logic
+ -- devices manufactured by Intel and sold by Intel or its
+ -- authorized distributors. Please refer to the applicable
+ -- agreement for further details.
+ --
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 3A: 2.5V
+ -- Bank 3B: 3.3V
+ -- Bank 4A: 3.3V
+ -- Bank 5A: 3.3V
+ -- Bank 5B: 3.3V
+ -- Bank 6B: 2.5V
+ -- Bank 6A: 2.5V
+ -- Bank 7A: 2.5V
+ -- Bank 7B: 2.5V
+ -- Bank 7C: 2.5V
+ -- Bank 7D: 2.5V
+ -- Bank 8A: 2.5V
+ -- Bank 9A: Dedicated configuration pins only, no VCCIO required.
+ -- RREF : External reference resistor for the quad, MUST be connected to
+ -- GND via a 2k Ohm resistor.
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
+ -- must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+CHIP "ex8" ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A :
+VCCIO8A : A7 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A :
+GND : A12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C :
+GND : A17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B :
+GND : A22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A :
+GND : A26 : : : : 7A :
+GND : A27 : gnd : : : :
+HPS_TRST : A28 : : : : 7A :
+HPS_TMS : A29 : : : : 7A :
+GND : AA1 : gnd : : : :
+GND : AA2 : gnd : : : :
+GND : AA3 : gnd : : : :
+GND : AA4 : gnd : : : :
+VCC : AA5 : power : : 1.1V : :
+GND : AA6 : gnd : : : :
+DNU : AA7 : : : : :
+VCCA_FPLL : AA8 : power : : 2.5V : :
+GND : AA9 : gnd : : : :
+VCCPD3A : AA10 : power : : 2.5V : 3A :
+GND : AA11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3B :
+KEY[0] : AA14 : input : 3.3-V LVTTL : : 3B : Y
+KEY[1] : AA15 : input : 3.3-V LVTTL : : 3B : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
+VCCIO4A : AA17 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
+GND : AA22 : gnd : : : :
+VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
+VCCIO5B : AA27 : power : : 3.3V : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 5B :
+VREFB5BN0 : AA29 : power : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B :
+GND : AB1 : gnd : : : :
+GND : AB2 : gnd : : : :
+DNU : AB3 : : : : :
+DNU : AB4 : : : : :
+GND : AB5 : gnd : : : :
+VCCA_FPLL : AB6 : power : : 2.5V : :
+GND : AB7 : gnd : : : :
+nCSO, DATA4 : AB8 : : : : 3A :
+TDO : AB9 : output : : : 3A :
+VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX : AB11 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B :
+VCCIO3B : AB14 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B :
+VCC_AUX : AB16 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
+VCCPD3B4A : AB18 : power : : 3.3V : 3B, 4A :
+GND : AB19 : gnd : : : :
+VCCPD3B4A : AB20 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 5A :
+HEX2[0] : AB23 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AB24 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28 : : : : 5B :
+GND : AB29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B :
+GND : AC1 : gnd : : : :
+GND : AC2 : gnd : : : :
+GND : AC3 : gnd : : : :
+GND : AC4 : gnd : : : :
+TCK : AC5 : input : : : 3A :
+GND : AC6 : gnd : : : :
+AS_DATA3, DATA3 : AC7 : : : : 3A :
+GND : AC8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3A :
+VCCPD3A : AC10 : power : : 2.5V : 3A :
+VCCIO3A : AC11 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3A :
+VCCPD3B4A : AC13 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3B :
+VCCPD3B4A : AC15 : power : : 3.3V : 3B, 4A :
+GND : AC16 : gnd : : : :
+VCCPD3B4A : AC17 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
+VCCPD3B4A : AC19 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
+VCCIO4A : AC21 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
+VREFB5AN0 : AC24 : power : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5A :
+GND : AC26 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5A :
+HEX2[3] : AC28 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[5] : AC29 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[6] : AC30 : output : 3.3-V LVTTL : : 5B : Y
+GND : AD1 : gnd : : : :
+GND : AD2 : gnd : : : :
+DNU : AD3 : : : : :
+DNU : AD4 : : : : :
+GND : AD5 : gnd : : : :
+VREFB3AN0 : AD6 : power : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
+VCCIO3A : AD8 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3A :
+VCCIO3B : AD13 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B :
+DNU : AD15 : : : : :
+VCCPD3B4A : AD16 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
+VCCIO4A : AD18 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
+VCC_AUX : AD22 : power : : 2.5V : :
+GND : AD23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5A :
+HEX1[6] : AD27 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AD28 : power : : 3.3V : 5A :
+HEX2[2] : AD29 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[4] : AD30 : output : 3.3-V LVTTL : : 5B : Y
+GND : AE1 : gnd : : : :
+GND : AE2 : gnd : : : :
+GND : AE3 : gnd : : : :
+GND : AE4 : gnd : : : :
+AS_DATA1, DATA1 : AE5 : : : : 3A :
+AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3A :
+AS_DATA2, DATA2 : AE8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3A :
+GND : AE10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B :
+VCCIO3B : AE15 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
+GND : AE20 : gnd : : : :
+VCCPD3B4A : AE21 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
+VCCIO4A : AE25 : power : : 3.3V : 4A :
+HEX0[0] : AE26 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[1] : AE27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[2] : AE28 : output : 3.3-V LVTTL : : 5A : Y
+HEX2[1] : AE29 : output : 3.3-V LVTTL : : 5B : Y
+VCCIO5B : AE30 : power : : 3.3V : 5B :
+GND : AF1 : gnd : : : :
+GND : AF2 : gnd : : : :
+GND : AF3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A :
+VCCIO3A : AF7 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
+GND : AF12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B :
+CLOCK_50 : AF14 : input : 3.3-V LVTTL : : 3B : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
+GND : AF17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
+VCCIO4A : AF22 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A :
+GND : AF27 : gnd : : : :
+HEX0[4] : AF28 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[4] : AF29 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[5] : AF30 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A :
+VCCIO3A : AG4 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3A :
+GND : AG9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B :
+GND : AG14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
+VCCIO4A : AG19 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
+GND : AG24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
+HEX0[3] : AG27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[5] : AG28 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AG29 : power : : 3.3V : 5A :
+HEX1[3] : AG30 : output : 3.3-V LVTTL : : 5A : Y
+GND : AH1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A :
+GND : AH6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3B :
+GND : AH11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15 : : : : 3B :
+VCCIO4A : AH16 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A :
+GND : AH21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4A :
+VCCIO4A : AH26 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
+HEX0[6] : AH28 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[1] : AH29 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[2] : AH30 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2 : : : : 3A :
+GND : AJ3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B :
+VCCIO3B : AJ8 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B :
+VCCIO3B : AJ13 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B :
+VREFB3BN0 : AJ15 : power : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A :
+GND : AJ18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 4A :
+VCCIO4A : AJ23 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A :
+GND : AJ28 : gnd : : : :
+HEX1[0] : AJ29 : output : 3.3-V LVTTL : : 5A : Y
+GND : AJ30 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4 : : : : 3B :
+GND : AK5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B :
+VCCIO3B : AK10 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B :
+GND : AK15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A :
+VREFB4AN0 : AK17 : power : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A :
+VCCIO4A : AK20 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A :
+GND : AK25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A :
+VCCIO8A : B4 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A :
+GND : B9 : gnd : : : :
+VREFB8AN0 : B10 : power : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A :
+GND : B14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B :
+GND : B19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A :
+GND : B24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A :
+HPS_TDI : B27 : : : : 7A :
+HPS_TDO : B28 : : : : 7A :
+GND : B29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A :
+GND : C1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A :
+GND : C6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A :
+VCCIO8A : C11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D :
+GND : C16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B :
+GND : C21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A :
+GND : C26 : gnd : : : :
+HPS_nRST : C27 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A :
+GND : D3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
+VCCIO8A : D8 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
+GND : D13 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C :
+VCCIO7C_HPS : D18 : power : : 2.5V : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A :
+GND : D23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A :
+HPS_CLK1 : D25 : : : : 7A :
+GND : D26 : : : : 7A :
+HPS_RZQ_0 : D27 : : : : 6A :
+VCCIO6A_HPS : D28 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A :
+VCCIO8A : E5 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
+GND : E10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D :
+VCCIO7D_HPS : E15 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B :
+VCCIO7B_HPS : E20 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B :
+VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A :
+GND : E25 : gnd : : : :
+DNU : E26 : : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A :
+GND : E30 : gnd : : : :
+DNU : F1 : : : : :
+GND : F2 : gnd : : : :
+CONF_DONE : F3 : : : : 9A :
+nSTATUS : F4 : : : : 9A :
+GND : F5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
+GND : F7 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A :
+VCCIO8A : F12 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D :
+GND : F17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B :
+VCCIO7A_HPS : F22 : power : : 2.5V : 7A :
+HPS_nPOR : F23 : : : : 7A :
+HPS_PORSEL : F24 : : : : 7A :
+HPS_CLK2 : F25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
+GND : F27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A :
+GND : G1 : : : : :
+DNU : G2 : : : : :
+GND : G3 : gnd : : : :
+GND : G4 : gnd : : : :
+nCE : G5 : : : : 9A :
+MSEL2 : G6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8A :
+VCCIO8A : G9 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A :
+VCCIO8A : G14 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C :
+VCCIO7B_HPS : G19 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A :
+VCCRSTCLK_HPS : G23 : : : : 7A :
+GND : G24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
+VCCIO6A_HPS : G29 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A :
+GND : H1 : gnd : : : :
+GND : H2 : gnd : : : :
+DNU : H3 : : : : :
+DNU : H4 : : : : :
+GND : H5 : gnd : : : :
+VCCIO8A : H6 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
+VCCBAT : H9 : power : : 1.2V : :
+VCC_AUX : H10 : power : : 2.5V : :
+GND : H11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A :
+VCCIO7D_HPS : H16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A :
+VCCIO7A_HPS : H21 : power : : 2.5V : 7A :
+HPS_TCK : H22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
+VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A :
+GND : J1 : gnd : : : :
+GND : J2 : gnd : : : :
+GND : J3 : gnd : : : :
+GND : J4 : gnd : : : :
+nCONFIG : J5 : : : : 9A :
+GND : J6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
+GND : J8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
+VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A :
+VCCIO8A : J13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8A :
+DNU : J15 : : : : :
+VCC_AUX : J16 : power : : 2.5V : :
+VCCPD7C_HPS : J17 : power : : 2.5V : 7C :
+GND : J18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B :
+VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX_SHARED : J21 : power : : 2.5V : :
+GND : J22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
+GND : J28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A :
+GND : K1 : gnd : : : :
+GND : K2 : gnd : : : :
+DNU : K3 : : : : :
+DNU : K4 : : : : :
+GND : K5 : gnd : : : :
+MSEL1 : K6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
+VCCA_FPLL : K9 : power : : 2.5V : :
+GND : K10 : gnd : : : :
+VCCPD8A : K11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 8A :
+VCCPD8A : K13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A :
+GND : K15 : gnd : : : :
+VCCPD7D_HPS : K16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B :
+VCCPD7B_HPS : K18 : power : : 2.5V : 7B :
+VCCPD7A_HPS : K19 : power : : 2.5V : 7A :
+GND : K20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
+VCCIO6A_HPS : K24 : power : : 2.5V : 6A :
+GND : K25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A :
+VCCIO6A_HPS : K30 : power : : 2.5V : 6A :
+GND : L1 : gnd : : : :
+GND : L2 : gnd : : : :
+GND : L3 : gnd : : : :
+GND : L4 : gnd : : : :
+VCC : L5 : power : : 1.1V : :
+GND : L6 : gnd : : : :
+MSEL3 : L7 : : : : 9A :
+MSEL0 : L8 : : : : 9A :
+MSEL4 : L9 : : : : 9A :
+VCCPD8A : L10 : power : : 2.5V : 8A :
+GND : L11 : gnd : : : :
+VCCPD8A : L12 : power : : 2.5V : 8A :
+GND : L13 : gnd : : : :
+VCCPD8A : L14 : power : : 2.5V : 8A :
+GND : L15 : gnd : : : :
+VCC_HPS : L16 : power : : 1.1V : :
+GND : L17 : gnd : : : :
+VCC_HPS : L18 : power : : 1.1V : :
+GND : L19 : gnd : : : :
+VCC_HPS : L20 : power : : 1.1V : :
+VCCPLL_HPS : L21 : power : : 2.5V : :
+GND : L22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A :
+VCCIO6A_HPS : L27 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A :
+GND : M1 : gnd : : : :
+GND : M2 : gnd : : : :
+DNU : M3 : : : : :
+DNU : M4 : : : : :
+GND : M5 : gnd : : : :
+VCC : M6 : power : : 1.1V : :
+GND : M7 : gnd : : : :
+GND : M8 : gnd : : : :
+VCC : M9 : power : : 1.1V : :
+GND : M10 : gnd : : : :
+VCC : M11 : power : : 1.1V : :
+GND : M12 : gnd : : : :
+VCC : M13 : power : : 1.1V : :
+GND : M14 : gnd : : : :
+VCC_HPS : M15 : power : : 1.1V : :
+GND : M16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D :
+GND : M18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A :
+GND : M20 : gnd : : : :
+VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A :
+VCCIO6A_HPS : M24 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
+GND : M29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A :
+GND : N1 : gnd : : : :
+GND : N2 : gnd : : : :
+GND : N3 : gnd : : : :
+GND : N4 : gnd : : : :
+VCC : N5 : power : : 1.1V : :
+GND : N6 : gnd : : : :
+VCCA_FPLL : N7 : power : : 2.5V : :
+GND : N8 : gnd : : : :
+GND : N9 : gnd : : : :
+VCC : N10 : power : : 1.1V : :
+GND : N11 : gnd : : : :
+VCC : N12 : power : : 1.1V : :
+GND : N13 : gnd : : : :
+VCC : N14 : power : : 1.1V : :
+GND : N15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D :
+GND : N17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A :
+GND : N19 : gnd : : : :
+VCC_HPS : N20 : power : : 1.1V : :
+VCCIO6A_HPS : N21 : power : : 2.5V : 6A :
+VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A :
+GND : N26 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B :
+GND : P1 : gnd : : : :
+GND : P2 : gnd : : : :
+DNU : P3 : : : : :
+DNU : P4 : : : : :
+GND : P5 : gnd : : : :
+VCCA_FPLL : P6 : power : : 2.5V : :
+GND : P7 : gnd : : : :
+GND : P8 : gnd : : : :
+GND : P9 : gnd : : : :
+GND : P10 : gnd : : : :
+VCC : P11 : power : : 1.1V : :
+GND : P12 : gnd : : : :
+VCC : P13 : power : : 1.1V : :
+GND : P14 : gnd : : : :
+VCC_HPS : P15 : power : : 1.1V : :
+GND : P16 : gnd : : : :
+VCC_HPS : P17 : power : : 1.1V : :
+GND : P18 : gnd : : : :
+VCC_HPS : P19 : power : : 1.1V : :
+GND : P20 : gnd : : : :
+VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B :
+VCCIO6B_HPS : P23 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B :
+VCCIO6B_HPS : P28 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B :
+GND : R1 : gnd : : : :
+GND : R2 : gnd : : : :
+GND : R3 : gnd : : : :
+GND : R4 : gnd : : : :
+VCC : R5 : power : : 1.1V : :
+GND : R6 : gnd : : : :
+VCCA_FPLL : R7 : power : : 2.5V : :
+GND : R8 : gnd : : : :
+GND : R9 : gnd : : : :
+VCC : R10 : power : : 1.1V : :
+GND : R11 : gnd : : : :
+VCC : R12 : power : : 1.1V : :
+GND : R13 : gnd : : : :
+VCC : R14 : power : : 1.1V : :
+GND : R15 : gnd : : : :
+VCC_HPS : R16 : power : : 1.1V : :
+GND : R17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B :
+VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B :
+VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
+VCCIO6B_HPS : R25 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B :
+GND : R30 : gnd : : : :
+GND : T1 : gnd : : : :
+GND : T2 : gnd : : : :
+DNU : T3 : : : : :
+DNU : T4 : : : : :
+GND : T5 : gnd : : : :
+VCC : T6 : power : : 1.1V : :
+GND : T7 : gnd : : : :
+GND : T8 : gnd : : : :
+GND : T9 : gnd : : : :
+GND : T10 : gnd : : : :
+VCC : T11 : power : : 1.1V : :
+GND : T12 : gnd : : : :
+VCC : T13 : power : : 1.1V : :
+GND : T14 : gnd : : : :
+GND : T15 : gnd : : : :
+GND : T16 : gnd : : : :
+VCC_HPS : T17 : power : : 1.1V : :
+GND : T18 : gnd : : : :
+VCC_HPS : T19 : power : : 1.1V : :
+GND : T20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B :
+VCCIO6B_HPS : T22 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
+GND : T27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B :
+GND : U1 : gnd : : : :
+GND : U2 : gnd : : : :
+GND : U3 : gnd : : : :
+GND : U4 : gnd : : : :
+VCC : U5 : power : : 1.1V : :
+GND : U6 : gnd : : : :
+DCLK : U7 : : : : 3A :
+TDI : U8 : input : : : 3A :
+GND : U9 : gnd : : : :
+VCC : U10 : power : : 1.1V : :
+GND : U11 : gnd : : : :
+VCC : U12 : power : : 1.1V : :
+GND : U13 : gnd : : : :
+VCC : U14 : power : : 1.1V : :
+GND : U15 : gnd : : : :
+VCC_HPS : U16 : power : : 1.1V : :
+GND : U17 : gnd : : : :
+VCC_HPS : U18 : power : : 1.1V : :
+VCCIO6B_HPS : U19 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B :
+VCC : U21 : power : : 1.1V : :
+GND : U22 : gnd : : : :
+VCCPD5B : U23 : power : : 3.3V : 5B :
+GND : U24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
+GND : U29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B :
+GND : V1 : gnd : : : :
+GND : V2 : gnd : : : :
+DNU : V3 : : : : :
+DNU : V4 : : : : :
+GND : V5 : gnd : : : :
+VCCA_FPLL : V6 : power : : 2.5V : :
+GND : V7 : gnd : : : :
+VCCA_FPLL : V8 : power : : 2.5V : :
+TMS : V9 : input : : : 3A :
+GND : V10 : gnd : : : :
+VCC : V11 : power : : 1.1V : :
+GND : V12 : gnd : : : :
+VCC : V13 : power : : 1.1V : :
+GND : V14 : gnd : : : :
+VCC : V15 : power : : 1.1V : :
+LEDR[0] : V16 : output : 3.3-V LVTTL : : 4A : Y
+LEDR[2] : V17 : output : 3.3-V LVTTL : : 4A : Y
+LEDR[3] : V18 : output : 3.3-V LVTTL : : 4A : Y
+GND : V19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
+GND : V21 : gnd : : : :
+VCCPD5A : V22 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5A :
+VCCPD5A : V24 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
+VCCIO6B_HPS : V26 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B :
+GND : W1 : gnd : : : :
+GND : W2 : gnd : : : :
+GND : W3 : gnd : : : :
+GND : W4 : gnd : : : :
+VCC : W5 : power : : 1.1V : :
+GND : W6 : gnd : : : :
+GND : W7 : gnd : : : :
+GND : W8 : gnd : : : :
+GND : W9 : gnd : : : :
+VCC : W10 : power : : 1.1V : :
+GND : W11 : gnd : : : :
+VCC : W12 : power : : 1.1V : :
+GND : W13 : gnd : : : :
+VCC : W14 : power : : 1.1V : :
+KEY[2] : W15 : input : 3.3-V LVTTL : : 3B : Y
+LEDR[1] : W16 : output : 3.3-V LVTTL : : 4A : Y
+LEDR[4] : W17 : output : 3.3-V LVTTL : : 4A : Y
+GND : W18 : gnd : : : :
+LEDR[5] : W19 : output : 3.3-V LVTTL : : 4A : Y
+LEDR[7] : W20 : output : 3.3-V LVTTL : : 5A : Y
+LEDR[8] : W21 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5A :
+VCCIO5A : W23 : power : : 3.3V : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W24 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B :
+GND : W28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B :
+GND : Y1 : gnd : : : :
+GND : Y2 : gnd : : : :
+DNU : Y3 : : : : :
+DNU : Y4 : : : : :
+GND : Y5 : gnd : : : :
+VCC : Y6 : power : : 1.1V : :
+GND : Y7 : gnd : : : :
+GND : Y8 : gnd : : : :
+VCC : Y9 : power : : 1.1V : :
+GND : Y10 : gnd : : : :
+VCC : Y11 : power : : 1.1V : :
+GND : Y12 : gnd : : : :
+VCC : Y13 : power : : 1.1V : :
+GND : Y14 : gnd : : : :
+GND : Y15 : gnd : : : :
+KEY[3] : Y16 : input : 3.3-V LVTTL : : 3B : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
+LEDR[6] : Y19 : output : 3.3-V LVTTL : : 4A : Y
+GND : Y20 : gnd : : : :
+LEDR[9] : Y21 : output : 3.3-V LVTTL : : 5A : Y
+VCCA_FPLL : Y22 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A :
+GND : Y25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B :
+GND : Y30 : gnd : : : :
diff --git a/part_2/ex8/output_files/ex8.sld b/part_2/ex8/output_files/ex8.sld
index 41a6030..f7d3ed7 100755
--- a/part_2/ex8/output_files/ex8.sld
+++ b/part_2/ex8/output_files/ex8.sld
@@ -1 +1 @@
-<sld_project_info/>
+<sld_project_info/>
diff --git a/part_2/ex8/output_files/ex8.sof b/part_2/ex8/output_files/ex8.sof
index ee348cb..aa1c290 100755
--- a/part_2/ex8/output_files/ex8.sof
+++ b/part_2/ex8/output_files/ex8.sof
Binary files differ
diff --git a/part_2/ex8/output_files/ex8.sta.rpt b/part_2/ex8/output_files/ex8.sta.rpt
index d9b936c..5e481c2 100755
--- a/part_2/ex8/output_files/ex8.sta.rpt
+++ b/part_2/ex8/output_files/ex8.sta.rpt
@@ -1,864 +1,864 @@
-TimeQuest Timing Analyzer report for ex8
-Wed Dec 07 12:22:30 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. TimeQuest Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1100mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1100mV 85C Model Setup Summary
- 8. Slow 1100mV 85C Model Hold Summary
- 9. Slow 1100mV 85C Model Recovery Summary
- 10. Slow 1100mV 85C Model Removal Summary
- 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1100mV 85C Model Metastability Summary
- 13. Slow 1100mV 0C Model Fmax Summary
- 14. Slow 1100mV 0C Model Setup Summary
- 15. Slow 1100mV 0C Model Hold Summary
- 16. Slow 1100mV 0C Model Recovery Summary
- 17. Slow 1100mV 0C Model Removal Summary
- 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1100mV 0C Model Metastability Summary
- 20. Fast 1100mV 85C Model Setup Summary
- 21. Fast 1100mV 85C Model Hold Summary
- 22. Fast 1100mV 85C Model Recovery Summary
- 23. Fast 1100mV 85C Model Removal Summary
- 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
- 25. Fast 1100mV 85C Model Metastability Summary
- 26. Fast 1100mV 0C Model Setup Summary
- 27. Fast 1100mV 0C Model Hold Summary
- 28. Fast 1100mV 0C Model Recovery Summary
- 29. Fast 1100mV 0C Model Removal Summary
- 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
- 31. Fast 1100mV 0C Model Metastability Summary
- 32. Multicorner Timing Analysis Summary
- 33. Board Trace Model Assignments
- 34. Input Transition Times
- 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
- 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
- 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
- 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
- 39. Setup Transfers
- 40. Hold Transfers
- 41. Report TCCS
- 42. Report RSKM
- 43. Unconstrained Paths Summary
- 44. Clock Status Summary
- 45. Unconstrained Input Ports
- 46. Unconstrained Output Ports
- 47. Unconstrained Input Ports
- 48. Unconstrained Output Ports
- 49. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary ;
-+-----------------------+---------------------------------------------------------+
-; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Timing Analyzer ; TimeQuest ;
-; Revision Name ; ex8 ;
-; Device Family ; Cyclone V ;
-; Device Name ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+---------------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.06 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 2.2% ;
-; Processor 3 ; 2.1% ;
-; Processor 4 ; 2.1% ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; CLOCK_50 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
-; tick_50000:TICK0|CLK_OUT ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { tick_50000:TICK0|CLK_OUT } ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-
-
-+----------------------------------------------------------------+
-; Slow 1100mV 85C Model Fmax Summary ;
-+------------+-----------------+--------------------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+--------------------------+------+
-; 229.83 MHz ; 229.83 MHz ; tick_50000:TICK0|CLK_OUT ; ;
-; 296.74 MHz ; 296.74 MHz ; CLOCK_50 ; ;
-+------------+-----------------+--------------------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Setup Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT ; -3.351 ; -141.123 ;
-; CLOCK_50 ; -2.370 ; -46.721 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.669 ; -1.669 ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Slow 1100mV 85C Model Hold Summary ;
-+-------------------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT ; 0.287 ; 0.000 ;
-; CLOCK_50 ; 0.375 ; 0.000 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.603 ; 0.000 ;
-+-------------------------------------+-------+---------------+
-
-
-------------------------------------------
-; Slow 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50 ; -0.655 ; -20.255 ;
-; tick_50000:TICK0|CLK_OUT ; -0.394 ; -31.614 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.435 ; 0.000 ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------------
-; Slow 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------+
-; Slow 1100mV 0C Model Fmax Summary ;
-+------------+-----------------+--------------------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+--------------------------+------+
-; 234.36 MHz ; 234.36 MHz ; tick_50000:TICK0|CLK_OUT ; ;
-; 278.71 MHz ; 278.71 MHz ; CLOCK_50 ; ;
-+------------+-----------------+--------------------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Setup Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT ; -3.267 ; -138.732 ;
-; CLOCK_50 ; -2.588 ; -48.020 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.583 ; -1.583 ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Slow 1100mV 0C Model Hold Summary ;
-+-------------------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT ; 0.289 ; 0.000 ;
-; CLOCK_50 ; 0.391 ; 0.000 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.463 ; 0.000 ;
-+-------------------------------------+-------+---------------+
-
-
------------------------------------------
-; Slow 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50 ; -0.714 ; -18.725 ;
-; tick_50000:TICK0|CLK_OUT ; -0.394 ; -30.708 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.391 ; 0.000 ;
-+-------------------------------------+--------+---------------+
-
-
-----------------------------------------------
-; Slow 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Setup Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT ; -1.909 ; -72.643 ;
-; CLOCK_50 ; -1.138 ; -16.318 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.609 ; -0.609 ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Fast 1100mV 85C Model Hold Summary ;
-+-------------------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT ; 0.048 ; 0.000 ;
-; CLOCK_50 ; 0.181 ; 0.000 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.219 ; 0.000 ;
-+-------------------------------------+-------+---------------+
-
-
-------------------------------------------
-; Fast 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50 ; -0.779 ; -14.378 ;
-; tick_50000:TICK0|CLK_OUT ; -0.014 ; -0.134 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.468 ; 0.000 ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------------
-; Fast 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Setup Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT ; -1.657 ; -63.529 ;
-; CLOCK_50 ; -1.092 ; -13.791 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.488 ; -0.488 ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Fast 1100mV 0C Model Hold Summary ;
-+-------------------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT ; 0.013 ; 0.000 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.128 ; 0.000 ;
-; CLOCK_50 ; 0.171 ; 0.000 ;
-+-------------------------------------+-------+---------------+
-
-
------------------------------------------
-; Fast 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50 ; -0.829 ; -17.064 ;
-; tick_50000:TICK0|CLK_OUT ; 0.025 ; 0.000 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.460 ; 0.000 ;
-+-------------------------------------+--------+---------------+
-
-
-----------------------------------------------
-; Fast 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+--------------------------------------+----------+-------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+--------------------------------------+----------+-------+----------+---------+---------------------+
-; Worst-case Slack ; -3.351 ; 0.013 ; N/A ; N/A ; -0.829 ;
-; CLOCK_50 ; -2.588 ; 0.171 ; N/A ; N/A ; -0.829 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.669 ; 0.128 ; N/A ; N/A ; 0.391 ;
-; tick_50000:TICK0|CLK_OUT ; -3.351 ; 0.013 ; N/A ; N/A ; -0.394 ;
-; Design-wide TNS ; -189.513 ; 0.0 ; 0.0 ; 0.0 ; -51.869 ;
-; CLOCK_50 ; -48.020 ; 0.000 ; N/A ; N/A ; -20.255 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.669 ; 0.000 ; N/A ; N/A ; 0.000 ;
-; tick_50000:TICK0|CLK_OUT ; -141.123 ; 0.000 ; N/A ; N/A ; -31.614 ;
-+--------------------------------------+----------+-------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+-------------------------------------------------------------+
-; Input Transition Times ;
-+----------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+----------+--------------+-----------------+-----------------+
-; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; KEY[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; KEY[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-+----------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Setup Transfers ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 451 ; 0 ; 0 ; 0 ;
-; tick_50000:TICK0|CLK_OUT ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1 ; 0 ; 0 ; 0 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 43 ; 25 ; 0 ; 0 ;
-; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 914 ; 0 ; 0 ; 0 ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Hold Transfers ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 451 ; 0 ; 0 ; 0 ;
-; tick_50000:TICK0|CLK_OUT ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1 ; 0 ; 0 ; 0 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 43 ; 25 ; 0 ; 0 ;
-; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 914 ; 0 ; 0 ; 0 ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 1 ; 1 ;
-; Unconstrained Input Port Paths ; 3 ; 3 ;
-; Unconstrained Output Ports ; 28 ; 28 ;
-; Unconstrained Output Port Paths ; 121 ; 121 ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Clock Status Summary ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; Target ; Clock ; Type ; Status ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
-; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; Base ; Constrained ;
-+-------------------------------------+-------------------------------------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime TimeQuest Timing Analyzer
- Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
- Info: Processing started: Wed Dec 07 12:22:21 2016
-Info: Command: quartus_sta ex8 -c ex8
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
- Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
- Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
- Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1100mV 85C Model
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.351
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.351 -141.123 tick_50000:TICK0|CLK_OUT
- Info (332119): -2.370 -46.721 CLOCK_50
- Info (332119): -1.669 -1.669 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332146): Worst-case hold slack is 0.287
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.287 0.000 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.375 0.000 CLOCK_50
- Info (332119): 0.603 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.655
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -0.655 -20.255 CLOCK_50
- Info (332119): -0.394 -31.614 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.435 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info: Analyzing Slow 1100mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.267
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.267 -138.732 tick_50000:TICK0|CLK_OUT
- Info (332119): -2.588 -48.020 CLOCK_50
- Info (332119): -1.583 -1.583 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332146): Worst-case hold slack is 0.289
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.289 0.000 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.391 0.000 CLOCK_50
- Info (332119): 0.463 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.714
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -0.714 -18.725 CLOCK_50
- Info (332119): -0.394 -30.708 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.391 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info: Analyzing Fast 1100mV 85C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.909
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -1.909 -72.643 tick_50000:TICK0|CLK_OUT
- Info (332119): -1.138 -16.318 CLOCK_50
- Info (332119): -0.609 -0.609 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332146): Worst-case hold slack is 0.048
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.048 0.000 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.181 0.000 CLOCK_50
- Info (332119): 0.219 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.779
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -0.779 -14.378 CLOCK_50
- Info (332119): -0.014 -0.134 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.468 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info: Analyzing Fast 1100mV 0C Model
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.657
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -1.657 -63.529 tick_50000:TICK0|CLK_OUT
- Info (332119): -1.092 -13.791 CLOCK_50
- Info (332119): -0.488 -0.488 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332146): Worst-case hold slack is 0.013
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.013 0.000 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.128 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
- Info (332119): 0.171 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.829
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -0.829 -17.064 CLOCK_50
- Info (332119): 0.025 0.000 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.460 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
- Info: Peak virtual memory: 1209 megabytes
- Info: Processing ended: Wed Dec 07 12:22:30 2016
- Info: Elapsed time: 00:00:09
- Info: Total CPU time (on all processors): 00:00:06
-
-
+TimeQuest Timing Analyzer report for ex8
+Sun Dec 11 20:25:48 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. TimeQuest Timing Analyzer Summary
+ 3. Parallel Compilation
+ 4. Clocks
+ 5. Slow 1100mV 85C Model Fmax Summary
+ 6. Timing Closure Recommendations
+ 7. Slow 1100mV 85C Model Setup Summary
+ 8. Slow 1100mV 85C Model Hold Summary
+ 9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Setup Transfers
+ 40. Hold Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths Summary
+ 44. Clock Status Summary
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Unconstrained Input Ports
+ 48. Unconstrained Output Ports
+ 49. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary ;
++-----------------------+-----------------------------------------------------+
+; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Timing Analyzer ; TimeQuest ;
+; Revision Name ; ex8 ;
+; Device Family ; Cyclone V ;
+; Device Name ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Delay Model ; Combined ;
+; Rise/Fall Delays ; Enabled ;
++-----------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.12 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 4.1% ;
+; Processor 3 ; 4.0% ;
+; Processor 4 ; 3.8% ;
++----------------------------+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+; CLOCK_50 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
+; tick_50000:TICK0|CLK_OUT ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { tick_50000:TICK0|CLK_OUT } ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary ;
++------------+-----------------+--------------------------+------+
+; Fmax ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+--------------------------+------+
+; 252.02 MHz ; 252.02 MHz ; tick_50000:TICK0|CLK_OUT ; ;
+; 282.97 MHz ; 282.97 MHz ; CLOCK_50 ; ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 85C Model Setup Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT ; -2.968 ; -107.976 ;
+; CLOCK_50 ; -2.534 ; -41.925 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.603 ; -1.603 ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Slow 1100mV 85C Model Hold Summary ;
++-------------------------------------+-------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT ; 0.203 ; 0.000 ;
+; CLOCK_50 ; 0.384 ; 0.000 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.419 ; 0.000 ;
++-------------------------------------+-------+---------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50 ; -0.643 ; -16.740 ;
+; tick_50000:TICK0|CLK_OUT ; -0.394 ; -26.810 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.357 ; 0.000 ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary ;
++------------+-----------------+--------------------------+------+
+; Fmax ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+--------------------------+------+
+; 252.33 MHz ; 252.33 MHz ; tick_50000:TICK0|CLK_OUT ; ;
+; 264.27 MHz ; 264.27 MHz ; CLOCK_50 ; ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 0C Model Setup Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT ; -2.963 ; -106.734 ;
+; CLOCK_50 ; -2.784 ; -42.820 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.493 ; -1.493 ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Slow 1100mV 0C Model Hold Summary ;
++-------------------------------------+-------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT ; 0.233 ; 0.000 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.302 ; 0.000 ;
+; CLOCK_50 ; 0.406 ; 0.000 ;
++-------------------------------------+-------+---------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50 ; -0.717 ; -15.605 ;
+; tick_50000:TICK0|CLK_OUT ; -0.394 ; -26.816 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.396 ; 0.000 ;
++-------------------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Setup Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT ; -1.503 ; -52.250 ;
+; CLOCK_50 ; -1.304 ; -15.219 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.568 ; -0.568 ;
++-------------------------------------+--------+---------------+
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Hold Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT ; -0.034 ; -0.067 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.057 ; 0.000 ;
+; CLOCK_50 ; 0.185 ; 0.000 ;
++-------------------------------------+--------+---------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50 ; -0.786 ; -12.110 ;
+; tick_50000:TICK0|CLK_OUT ; 0.065 ; 0.000 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.369 ; 0.000 ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Setup Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT ; -1.311 ; -45.679 ;
+; CLOCK_50 ; -1.229 ; -13.104 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.445 ; -0.445 ;
++-------------------------------------+--------+---------------+
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Hold Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT ; -0.034 ; -0.067 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.014 ; -0.014 ;
+; CLOCK_50 ; 0.177 ; 0.000 ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50 ; -0.844 ; -14.423 ;
+; tick_50000:TICK0|CLK_OUT ; 0.081 ; 0.000 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.396 ; 0.000 ;
++-------------------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-----------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary ;
++--------------------------------------+----------+--------+----------+---------+---------------------+
+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++--------------------------------------+----------+--------+----------+---------+---------------------+
+; Worst-case Slack ; -2.968 ; -0.034 ; N/A ; N/A ; -0.844 ;
+; CLOCK_50 ; -2.784 ; 0.177 ; N/A ; N/A ; -0.844 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.603 ; -0.014 ; N/A ; N/A ; 0.357 ;
+; tick_50000:TICK0|CLK_OUT ; -2.968 ; -0.034 ; N/A ; N/A ; -0.394 ;
+; Design-wide TNS ; -151.504 ; -0.081 ; 0.0 ; 0.0 ; -43.55 ;
+; CLOCK_50 ; -42.820 ; 0.000 ; N/A ; N/A ; -16.740 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.603 ; -0.014 ; N/A ; N/A ; 0.000 ;
+; tick_50000:TICK0|CLK_OUT ; -107.976 ; -0.067 ; N/A ; N/A ; -26.816 ;
++--------------------------------------+----------+--------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times ;
++----------+--------------+-----------------+-----------------+
+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; KEY[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; KEY[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; CLOCK_50 ; CLOCK_50 ; 405 ; 0 ; 0 ; 0 ;
+; tick_50000:TICK0|CLK_OUT ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1 ; 0 ; 0 ; 0 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 39 ; 21 ; 0 ; 0 ;
+; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 752 ; 0 ; 0 ; 0 ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; CLOCK_50 ; CLOCK_50 ; 405 ; 0 ; 0 ; 0 ;
+; tick_50000:TICK0|CLK_OUT ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1 ; 0 ; 0 ; 0 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 39 ; 21 ; 0 ; 0 ;
+; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 752 ; 0 ; 0 ; 0 ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary ;
++---------------------------------+-------+------+
+; Property ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks ; 0 ; 0 ;
+; Unconstrained Clocks ; 0 ; 0 ;
+; Unconstrained Input Ports ; 1 ; 1 ;
+; Unconstrained Input Port Paths ; 3 ; 3 ;
+; Unconstrained Output Ports ; 28 ; 28 ;
+; Unconstrained Output Port Paths ; 121 ; 121 ;
++---------------------------------+-------+------+
+
+
++------------------------------------------------------------------------------------------------+
+; Clock Status Summary ;
++-------------------------------------+-------------------------------------+------+-------------+
+; Target ; Clock ; Type ; Status ;
++-------------------------------------+-------------------------------------+------+-------------+
+; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
+; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; Base ; Constrained ;
++-------------------------------------+-------------------------------------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+ Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+ Info: Processing started: Sun Dec 11 20:25:43 2016
+Info: Command: quartus_sta ex8 -c ex8
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+ Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
+ Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
+ Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Critical Warning (332148): Timing requirements not met
+ Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -2.968
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -2.968 -107.976 tick_50000:TICK0|CLK_OUT
+ Info (332119): -2.534 -41.925 CLOCK_50
+ Info (332119): -1.603 -1.603 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332146): Worst-case hold slack is 0.203
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 0.203 0.000 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.384 0.000 CLOCK_50
+ Info (332119): 0.419 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.643
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -0.643 -16.740 CLOCK_50
+ Info (332119): -0.394 -26.810 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.357 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+ Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -2.963
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -2.963 -106.734 tick_50000:TICK0|CLK_OUT
+ Info (332119): -2.784 -42.820 CLOCK_50
+ Info (332119): -1.493 -1.493 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332146): Worst-case hold slack is 0.233
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 0.233 0.000 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.302 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+ Info (332119): 0.406 0.000 CLOCK_50
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.717
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -0.717 -15.605 CLOCK_50
+ Info (332119): -0.394 -26.816 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.396 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+ Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.503
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -1.503 -52.250 tick_50000:TICK0|CLK_OUT
+ Info (332119): -1.304 -15.219 CLOCK_50
+ Info (332119): -0.568 -0.568 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332146): Worst-case hold slack is -0.034
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -0.034 -0.067 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.057 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+ Info (332119): 0.185 0.000 CLOCK_50
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.786
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -0.786 -12.110 CLOCK_50
+ Info (332119): 0.065 0.000 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.369 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info: Analyzing Fast 1100mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+ Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.311
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -1.311 -45.679 tick_50000:TICK0|CLK_OUT
+ Info (332119): -1.229 -13.104 CLOCK_50
+ Info (332119): -0.445 -0.445 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332146): Worst-case hold slack is -0.034
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -0.034 -0.067 tick_50000:TICK0|CLK_OUT
+ Info (332119): -0.014 -0.014 formula_fsm:FSM|state.LIGHT_UP_LEDS
+ Info (332119): 0.177 0.000 CLOCK_50
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.844
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -0.844 -14.423 CLOCK_50
+ Info (332119): 0.081 0.000 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.396 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
+ Info: Peak virtual memory: 1214 megabytes
+ Info: Processing ended: Sun Dec 11 20:25:48 2016
+ Info: Elapsed time: 00:00:05
+ Info: Total CPU time (on all processors): 00:00:05
+
+
diff --git a/part_2/ex8/output_files/ex8.sta.summary b/part_2/ex8/output_files/ex8.sta.summary
index 0dc051d..3a5916d 100755
--- a/part_2/ex8/output_files/ex8.sta.summary
+++ b/part_2/ex8/output_files/ex8.sta.summary
@@ -1,149 +1,149 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.351
-TNS : -141.123
-
-Type : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -2.370
-TNS : -46.721
-
-Type : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.669
-TNS : -1.669
-
-Type : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.287
-TNS : 0.000
-
-Type : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.375
-TNS : 0.000
-
-Type : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.603
-TNS : 0.000
-
-Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.655
-TNS : -20.255
-
-Type : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS : -31.614
-
-Type : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.435
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.267
-TNS : -138.732
-
-Type : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -2.588
-TNS : -48.020
-
-Type : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.583
-TNS : -1.583
-
-Type : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.289
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.391
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.463
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.714
-TNS : -18.725
-
-Type : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS : -30.708
-
-Type : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.391
-TNS : 0.000
-
-Type : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.909
-TNS : -72.643
-
-Type : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -1.138
-TNS : -16.318
-
-Type : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.609
-TNS : -0.609
-
-Type : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.048
-TNS : 0.000
-
-Type : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.181
-TNS : 0.000
-
-Type : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.219
-TNS : 0.000
-
-Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.779
-TNS : -14.378
-
-Type : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.014
-TNS : -0.134
-
-Type : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.468
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.657
-TNS : -63.529
-
-Type : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -1.092
-TNS : -13.791
-
-Type : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.488
-TNS : -0.488
-
-Type : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.013
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.128
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.171
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.829
-TNS : -17.064
-
-Type : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.025
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.460
-TNS : 0.000
-
-------------------------------------------------------------
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -2.968
+TNS : -107.976
+
+Type : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -2.534
+TNS : -41.925
+
+Type : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -1.603
+TNS : -1.603
+
+Type : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.203
+TNS : 0.000
+
+Type : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.384
+TNS : 0.000
+
+Type : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.419
+TNS : 0.000
+
+Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.643
+TNS : -16.740
+
+Type : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.394
+TNS : -26.810
+
+Type : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.357
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -2.963
+TNS : -106.734
+
+Type : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -2.784
+TNS : -42.820
+
+Type : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -1.493
+TNS : -1.493
+
+Type : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.233
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.302
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.406
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.717
+TNS : -15.605
+
+Type : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.394
+TNS : -26.816
+
+Type : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.396
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -1.503
+TNS : -52.250
+
+Type : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -1.304
+TNS : -15.219
+
+Type : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -0.568
+TNS : -0.568
+
+Type : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.034
+TNS : -0.067
+
+Type : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.057
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.185
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.786
+TNS : -12.110
+
+Type : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.065
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.369
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -1.311
+TNS : -45.679
+
+Type : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -1.229
+TNS : -13.104
+
+Type : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -0.445
+TNS : -0.445
+
+Type : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.034
+TNS : -0.067
+
+Type : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -0.014
+TNS : -0.014
+
+Type : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.177
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.844
+TNS : -14.423
+
+Type : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.081
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.396
+TNS : 0.000
+
+------------------------------------------------------------
diff --git a/part_2/ex8/verilog_files/formula_fsm.v b/part_2/ex8/verilog_files/formula_fsm.v
index f79a62e..36c5668 100755
--- a/part_2/ex8/verilog_files/formula_fsm.v
+++ b/part_2/ex8/verilog_files/formula_fsm.v
@@ -8,7 +8,7 @@ reg [1:0] state;
reg led_on, en_lfsr, start_delay;
reg [9:0] ledr;
-reg [11:0] count;
+reg [8:0] count;
parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;
@@ -41,17 +41,17 @@ always @ (posedge clk)
ledr = 0;
LIGHT_UP_LEDS:
begin
- if(count == 1'b0)
+ if(count == 9'b0)
begin
ledr <= {ledr[8:0], 1'b1};
- count <= 12'd2499;
+ count <= 9'd499;
end
else
begin
count <= count - 1'b1;
end
end
- default: count <= 12'd2499;
+ default: count <= 9'd499;
endcase
always @ (*)
diff --git a/part_2/ex9/c5_pin_model_dump.txt b/part_2/ex9/c5_pin_model_dump.txt
index a895a64..31bb72c 100644
--- a/part_2/ex9/c5_pin_model_dump.txt
+++ b/part_2/ex9/c5_pin_model_dump.txt
@@ -1,118 +1,118 @@
-io_4iomodule_c5_index: 55gpio_index: 2
-io_4iomodule_c5_index: 54gpio_index: 465
-io_4iomodule_c5_index: 33gpio_index: 6
-io_4iomodule_c5_index: 51gpio_index: 461
-io_4iomodule_c5_index: 27gpio_index: 10
-io_4iomodule_c5_index: 57gpio_index: 457
-io_4iomodule_c5_index: 34gpio_index: 14
-io_4iomodule_c5_index: 28gpio_index: 453
-io_4iomodule_c5_index: 26gpio_index: 19
-io_4iomodule_c5_index: 47gpio_index: 449
-io_4iomodule_c5_index: 29gpio_index: 22
-io_4iomodule_c5_index: 3gpio_index: 445
-io_4iomodule_c5_index: 16gpio_index: 27
-io_4iomodule_c5_index: 6gpio_index: 441
-io_4iomodule_c5_index: 50gpio_index: 30
-io_4iomodule_c5_index: 35gpio_index: 437
-io_4iomodule_c5_index: 7gpio_index: 35
-io_4iomodule_c5_index: 53gpio_index: 433
-io_4iomodule_c5_index: 12gpio_index: 38
-io_4iomodule_c5_index: 1gpio_index: 429
-io_4iomodule_c5_index: 22gpio_index: 43
-io_4iomodule_c5_index: 8gpio_index: 425
-io_4iomodule_c5_index: 20gpio_index: 46
-io_4iomodule_c5_index: 30gpio_index: 421
-io_4iomodule_c5_index: 2gpio_index: 51
-io_4iomodule_c5_index: 31gpio_index: 417
-io_4iomodule_c5_index: 39gpio_index: 54
-io_4iomodule_c5_index: 18gpio_index: 413
-io_4iomodule_c5_index: 10gpio_index: 59
-io_4iomodule_c5_index: 42gpio_index: 409
-io_4iomodule_c5_index: 5gpio_index: 62
-io_4iomodule_c5_index: 24gpio_index: 405
-io_4iomodule_c5_index: 37gpio_index: 67
-io_4iomodule_c5_index: 13gpio_index: 401
-io_4iomodule_c5_index: 0gpio_index: 70
-io_4iomodule_c5_index: 44gpio_index: 397
-io_4iomodule_c5_index: 38gpio_index: 75
-io_4iomodule_c5_index: 52gpio_index: 393
-io_4iomodule_c5_index: 32gpio_index: 78
-io_4iomodule_c5_index: 56gpio_index: 389
-io_4iomodule_a_index: 13gpio_index: 385
-io_4iomodule_c5_index: 4gpio_index: 83
-io_4iomodule_c5_index: 23gpio_index: 86
-io_4iomodule_a_index: 15gpio_index: 381
-io_4iomodule_a_index: 8gpio_index: 377
-io_4iomodule_c5_index: 46gpio_index: 91
-io_4iomodule_a_index: 5gpio_index: 373
-io_4iomodule_a_index: 11gpio_index: 369
-io_4iomodule_c5_index: 41gpio_index: 94
-io_4iomodule_a_index: 3gpio_index: 365
-io_4iomodule_c5_index: 25gpio_index: 99
-io_4iomodule_a_index: 7gpio_index: 361
-io_4iomodule_c5_index: 9gpio_index: 102
-io_4iomodule_a_index: 0gpio_index: 357
-io_4iomodule_c5_index: 14gpio_index: 107
-io_4iomodule_a_index: 12gpio_index: 353
-io_4iomodule_c5_index: 45gpio_index: 110
-io_4iomodule_c5_index: 17gpio_index: 115
-io_4iomodule_a_index: 4gpio_index: 349
-io_4iomodule_c5_index: 36gpio_index: 118
-io_4iomodule_a_index: 10gpio_index: 345
-io_4iomodule_a_index: 16gpio_index: 341
-io_4iomodule_c5_index: 15gpio_index: 123
-io_4iomodule_a_index: 14gpio_index: 337
-io_4iomodule_c5_index: 43gpio_index: 126
-io_4iomodule_c5_index: 19gpio_index: 131
-io_4iomodule_a_index: 1gpio_index: 333
-io_4iomodule_c5_index: 59gpio_index: 134
-io_4iomodule_a_index: 2gpio_index: 329
-io_4iomodule_a_index: 9gpio_index: 325
-io_4iomodule_c5_index: 48gpio_index: 139
-io_4iomodule_a_index: 6gpio_index: 321
-io_4iomodule_a_index: 17gpio_index: 317
-io_4iomodule_c5_index: 40gpio_index: 142
-io_4iomodule_c5_index: 11gpio_index: 147
-io_4iomodule_c5_index: 58gpio_index: 150
-io_4iomodule_c5_index: 21gpio_index: 155
-io_4iomodule_c5_index: 49gpio_index: 158
-io_4iomodule_h_c5_index: 0gpio_index: 161
-io_4iomodule_h_c5_index: 6gpio_index: 165
-io_4iomodule_h_c5_index: 10gpio_index: 169
-io_4iomodule_h_c5_index: 3gpio_index: 173
-io_4iomodule_h_c5_index: 8gpio_index: 176
-io_4iomodule_h_c5_index: 11gpio_index: 180
-io_4iomodule_h_c5_index: 7gpio_index: 184
-io_4iomodule_h_c5_index: 5gpio_index: 188
-io_4iomodule_h_c5_index: 1gpio_index: 192
-io_4iomodule_h_c5_index: 2gpio_index: 196
-io_4iomodule_h_c5_index: 9gpio_index: 200
-io_4iomodule_h_c5_index: 4gpio_index: 204
-io_4iomodule_h_index: 15gpio_index: 208
-io_4iomodule_h_index: 1gpio_index: 212
-io_4iomodule_h_index: 3gpio_index: 216
-io_4iomodule_h_index: 2gpio_index: 220
-io_4iomodule_h_index: 11gpio_index: 224
-io_4iomodule_vref_h_index: 1gpio_index: 228
-io_4iomodule_h_index: 20gpio_index: 231
-io_4iomodule_h_index: 8gpio_index: 235
-io_4iomodule_h_index: 6gpio_index: 239
-io_4iomodule_h_index: 10gpio_index: 243
-io_4iomodule_h_index: 23gpio_index: 247
-io_4iomodule_h_index: 7gpio_index: 251
-io_4iomodule_h_index: 22gpio_index: 255
-io_4iomodule_h_index: 5gpio_index: 259
-io_4iomodule_h_index: 24gpio_index: 263
-io_4iomodule_h_index: 0gpio_index: 267
-io_4iomodule_h_index: 13gpio_index: 271
-io_4iomodule_h_index: 21gpio_index: 275
-io_4iomodule_h_index: 16gpio_index: 279
-io_4iomodule_vref_h_index: 0gpio_index: 283
-io_4iomodule_h_index: 12gpio_index: 286
-io_4iomodule_h_index: 4gpio_index: 290
-io_4iomodule_h_index: 19gpio_index: 294
-io_4iomodule_h_index: 18gpio_index: 298
-io_4iomodule_h_index: 17gpio_index: 302
-io_4iomodule_h_index: 25gpio_index: 306
-io_4iomodule_h_index: 14gpio_index: 310
-io_4iomodule_h_index: 9gpio_index: 314
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_2/ex9/db/.cmp.kpt b/part_2/ex9/db/.cmp.kpt
index 1617b0b..51a51ce 100644
--- a/part_2/ex9/db/.cmp.kpt
+++ b/part_2/ex9/db/.cmp.kpt
Binary files differ
diff --git a/part_2/ex9/db/ex9.(0).cnf.cdb b/part_2/ex9/db/ex9.(0).cnf.cdb
index 2a49e3b..8525cd4 100644
--- a/part_2/ex9/db/ex9.(0).cnf.cdb
+++ b/part_2/ex9/db/ex9.(0).cnf.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(0).cnf.hdb b/part_2/ex9/db/ex9.(0).cnf.hdb
index f90ac91..4b411ff 100644
--- a/part_2/ex9/db/ex9.(0).cnf.hdb
+++ b/part_2/ex9/db/ex9.(0).cnf.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(1).cnf.cdb b/part_2/ex9/db/ex9.(1).cnf.cdb
index 6fa5bfa..5738c43 100644
--- a/part_2/ex9/db/ex9.(1).cnf.cdb
+++ b/part_2/ex9/db/ex9.(1).cnf.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(1).cnf.hdb b/part_2/ex9/db/ex9.(1).cnf.hdb
index 829c3df..74fd96e 100644
--- a/part_2/ex9/db/ex9.(1).cnf.hdb
+++ b/part_2/ex9/db/ex9.(1).cnf.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(2).cnf.cdb b/part_2/ex9/db/ex9.(2).cnf.cdb
index 43aabd2..1fc3dad 100644
--- a/part_2/ex9/db/ex9.(2).cnf.cdb
+++ b/part_2/ex9/db/ex9.(2).cnf.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(2).cnf.hdb b/part_2/ex9/db/ex9.(2).cnf.hdb
index a2fe649..cef343d 100644
--- a/part_2/ex9/db/ex9.(2).cnf.hdb
+++ b/part_2/ex9/db/ex9.(2).cnf.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(3).cnf.cdb b/part_2/ex9/db/ex9.(3).cnf.cdb
index dbd336f..f2e3fb4 100644
--- a/part_2/ex9/db/ex9.(3).cnf.cdb
+++ b/part_2/ex9/db/ex9.(3).cnf.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(3).cnf.hdb b/part_2/ex9/db/ex9.(3).cnf.hdb
index ac9f5e9..e0a8e13 100644
--- a/part_2/ex9/db/ex9.(3).cnf.hdb
+++ b/part_2/ex9/db/ex9.(3).cnf.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(4).cnf.cdb b/part_2/ex9/db/ex9.(4).cnf.cdb
index 13f6ae2..c07454b 100644
--- a/part_2/ex9/db/ex9.(4).cnf.cdb
+++ b/part_2/ex9/db/ex9.(4).cnf.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(4).cnf.hdb b/part_2/ex9/db/ex9.(4).cnf.hdb
index b7d17a9..79a989e 100644
--- a/part_2/ex9/db/ex9.(4).cnf.hdb
+++ b/part_2/ex9/db/ex9.(4).cnf.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(5).cnf.cdb b/part_2/ex9/db/ex9.(5).cnf.cdb
index d06bc36..006be23 100644
--- a/part_2/ex9/db/ex9.(5).cnf.cdb
+++ b/part_2/ex9/db/ex9.(5).cnf.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(5).cnf.hdb b/part_2/ex9/db/ex9.(5).cnf.hdb
index d5d29c3..5bf565f 100644
--- a/part_2/ex9/db/ex9.(5).cnf.hdb
+++ b/part_2/ex9/db/ex9.(5).cnf.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(6).cnf.cdb b/part_2/ex9/db/ex9.(6).cnf.cdb
index 05cba02..e0f349d 100644
--- a/part_2/ex9/db/ex9.(6).cnf.cdb
+++ b/part_2/ex9/db/ex9.(6).cnf.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(6).cnf.hdb b/part_2/ex9/db/ex9.(6).cnf.hdb
index 9cf3763..8fd64f2 100644
--- a/part_2/ex9/db/ex9.(6).cnf.hdb
+++ b/part_2/ex9/db/ex9.(6).cnf.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(7).cnf.cdb b/part_2/ex9/db/ex9.(7).cnf.cdb
index 604867e..a0dd9e5 100644
--- a/part_2/ex9/db/ex9.(7).cnf.cdb
+++ b/part_2/ex9/db/ex9.(7).cnf.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(7).cnf.hdb b/part_2/ex9/db/ex9.(7).cnf.hdb
index da601fb..422205c 100644
--- a/part_2/ex9/db/ex9.(7).cnf.hdb
+++ b/part_2/ex9/db/ex9.(7).cnf.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(8).cnf.cdb b/part_2/ex9/db/ex9.(8).cnf.cdb
index 97e595e..62ff4d4 100644
--- a/part_2/ex9/db/ex9.(8).cnf.cdb
+++ b/part_2/ex9/db/ex9.(8).cnf.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(8).cnf.hdb b/part_2/ex9/db/ex9.(8).cnf.hdb
index 42ab8b5..2ce9333 100644
--- a/part_2/ex9/db/ex9.(8).cnf.hdb
+++ b/part_2/ex9/db/ex9.(8).cnf.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.(9).cnf.cdb b/part_2/ex9/db/ex9.(9).cnf.cdb
deleted file mode 100644
index e219d8b..0000000
--- a/part_2/ex9/db/ex9.(9).cnf.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/db/ex9.(9).cnf.hdb b/part_2/ex9/db/ex9.(9).cnf.hdb
deleted file mode 100644
index 0bbfa6a..0000000
--- a/part_2/ex9/db/ex9.(9).cnf.hdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/db/ex9.asm.qmsg b/part_2/ex9/db/ex9.asm.qmsg
index c869bf0..45a240e 100644
--- a/part_2/ex9/db/ex9.asm.qmsg
+++ b/part_2/ex9/db/ex9.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112492741 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112492743 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:08:12 2016 " "Processing started: Wed Dec 07 12:08:12 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112492743 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481112492743 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481112492743 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481112493565 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481112498243 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:20 2016 " "Processing ended: Wed Dec 07 12:08:20 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481112500798 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481488253376 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481488253382 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:30:53 2016 " "Processing started: Sun Dec 11 20:30:53 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481488253382 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481488253382 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481488253382 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481488254041 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481488259233 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "979 " "Peak virtual memory: 979 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481488259594 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:30:59 2016 " "Processing ended: Sun Dec 11 20:30:59 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481488259594 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481488259594 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481488259594 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481488259594 ""}
diff --git a/part_2/ex9/db/ex9.asm.rdb b/part_2/ex9/db/ex9.asm.rdb
index 3a4d871..1ffef45 100644
--- a/part_2/ex9/db/ex9.asm.rdb
+++ b/part_2/ex9/db/ex9.asm.rdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.cbx.xml b/part_2/ex9/db/ex9.cbx.xml
index 9156ad4..3c357f6 100644
--- a/part_2/ex9/db/ex9.cbx.xml
+++ b/part_2/ex9/db/ex9.cbx.xml
@@ -1,5 +1,5 @@
-<?xml version="1.0" ?>
-<LOG_ROOT>
- <PROJECT NAME="ex9">
- </PROJECT>
-</LOG_ROOT>
+<?xml version="1.0" ?>
+<LOG_ROOT>
+ <PROJECT NAME="ex9">
+ </PROJECT>
+</LOG_ROOT>
diff --git a/part_2/ex9/db/ex9.cmp.ammdb b/part_2/ex9/db/ex9.cmp.ammdb
deleted file mode 100644
index b640a2a..0000000
--- a/part_2/ex9/db/ex9.cmp.ammdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/db/ex9.cmp.bpm b/part_2/ex9/db/ex9.cmp.bpm
index 2d49b22..822783a 100644
--- a/part_2/ex9/db/ex9.cmp.bpm
+++ b/part_2/ex9/db/ex9.cmp.bpm
Binary files differ
diff --git a/part_2/ex9/db/ex9.cmp.cdb b/part_2/ex9/db/ex9.cmp.cdb
index 3d4dfef..523adce 100644
--- a/part_2/ex9/db/ex9.cmp.cdb
+++ b/part_2/ex9/db/ex9.cmp.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.cmp.hdb b/part_2/ex9/db/ex9.cmp.hdb
index 3756b65..527505a 100644
--- a/part_2/ex9/db/ex9.cmp.hdb
+++ b/part_2/ex9/db/ex9.cmp.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.cmp.idb b/part_2/ex9/db/ex9.cmp.idb
index 5cbf640..a6ead63 100644
--- a/part_2/ex9/db/ex9.cmp.idb
+++ b/part_2/ex9/db/ex9.cmp.idb
Binary files differ
diff --git a/part_2/ex9/db/ex9.cmp.logdb b/part_2/ex9/db/ex9.cmp.logdb
index b4567d7..625b3e6 100644
--- a/part_2/ex9/db/ex9.cmp.logdb
+++ b/part_2/ex9/db/ex9.cmp.logdb
@@ -1,96 +1,96 @@
-v1
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
-IO_RULES_MATRIX,Total Pass,57;0;57;0;0;57;57;0;57;57;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,0;57;0;57;57;0;0;57;0;0;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,28,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
+v1
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000003;IO_000001;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000022;IO_000021;IO_000046;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000047;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
+IO_RULES_MATRIX,Total Pass,0;57;57;0;0;57;57;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;57;57;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,57;0;0;57;57;0;0;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;0;0;57,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,KEY[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX3[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX4[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX5[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX5[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX5[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX5[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX5[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX5[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,HEX5[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,LEDR[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,KEY[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_2/ex9/db/ex9.cmp.rdb b/part_2/ex9/db/ex9.cmp.rdb
index 89d655d..e9a3bb6 100644
--- a/part_2/ex9/db/ex9.cmp.rdb
+++ b/part_2/ex9/db/ex9.cmp.rdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.cmp_merge.kpt b/part_2/ex9/db/ex9.cmp_merge.kpt
index fdd3bfe..a4ff375 100644
--- a/part_2/ex9/db/ex9.cmp_merge.kpt
+++ b/part_2/ex9/db/ex9.cmp_merge.kpt
Binary files differ
diff --git a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
index da61997..826025e 100644
--- a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
+++ b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
Binary files differ
diff --git a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
index 3a7a497..8ebe269 100644
--- a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
+++ b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
Binary files differ
diff --git a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
index aa473fa..8d531ee 100644
--- a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
+++ b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
Binary files differ
diff --git a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
index acc52a8..1e5e40e 100644
--- a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
+++ b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
Binary files differ
diff --git a/part_2/ex9/db/ex9.db_info b/part_2/ex9/db/ex9.db_info
index 0319e5b..4aad5b9 100644
--- a/part_2/ex9/db/ex9.db_info
+++ b/part_2/ex9/db/ex9.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Version_Index = 402707200
-Creation_Time = Wed Dec 07 11:55:17 2016
+Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Version_Index = 419480576
+Creation_Time = Sun Dec 11 20:28:46 2016
diff --git a/part_2/ex9/db/ex9.fit.qmsg b/part_2/ex9/db/ex9.fit.qmsg
index ad91f8e..9cc49ad 100644
--- a/part_2/ex9/db/ex9.fit.qmsg
+++ b/part_2/ex9/db/ex9.fit.qmsg
@@ -1,45 +1,46 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481112453657 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481112453658 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481112453895 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112453945 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112453945 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481112454353 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481112454715 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481112465342 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481112465453 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481112465453 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112465454 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481112465457 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112465458 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112465459 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481112465459 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481112465460 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481112465460 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481112466204 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481112466204 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481112466205 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481112466208 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481112466209 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481112466209 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481112466213 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481112466214 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481112466214 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481112466267 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112466278 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481112471355 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481112471629 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112472386 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481112473242 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481112474189 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112474189 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481112475466 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" { } { { "loc" "" { Generic "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481112480003 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481112480003 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481112481785 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481112481785 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112481789 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481112483588 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112483629 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112484239 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112484239 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112484754 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112487536 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481112487786 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481112487890 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2593 " "Peak virtual memory: 2593 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:09 2016 " "Processing ended: Wed Dec 07 12:08:09 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Elapsed time: 00:00:37" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:02 " "Total CPU time (on all processors): 00:01:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481112489326 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481488216378 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481488216378 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481488216384 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481488216418 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481488216418 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481488216800 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1481488216819 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481488216879 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481488228269 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481488228378 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481488228378 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488228378 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481488228383 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481488228383 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481488228385 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481488228386 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481488228386 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481488228386 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481488229012 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481488229013 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481488229013 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481488229018 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481488229018 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481488229019 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481488229026 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481488229027 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481488229027 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481488229081 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:13 " "Fitter preparation operations ending: elapsed time is 00:00:13" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488229082 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481488233823 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481488234092 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488234724 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481488235867 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481488237091 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488237091 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481488238139 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X33_Y0 X44_Y10 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X33_Y0 to location X44_Y10" { } { { "loc" "" { Generic "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X33_Y0 to location X44_Y10"} { { 12 { 0 ""} 33 0 12 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481488243100 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481488243100 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481488246581 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481488246581 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488246583 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.54 " "Total time spent on timing analysis during the Fitter is 0.54 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481488248270 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481488248303 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481488248769 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481488248769 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481488249249 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488251686 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481488251801 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.fit.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481488251868 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 31 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2145 " "Peak virtual memory: 2145 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481488252290 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:30:52 2016 " "Processing ended: Sun Dec 11 20:30:52 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481488252290 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Elapsed time: 00:00:37" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481488252290 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:04 " "Total CPU time (on all processors): 00:01:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481488252290 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481488252290 ""}
diff --git a/part_2/ex9/db/ex9.hier_info b/part_2/ex9/db/ex9.hier_info
index 2ac051e..1dcb685 100644
--- a/part_2/ex9/db/ex9.hier_info
+++ b/part_2/ex9/db/ex9.hier_info
@@ -1,784 +1,781 @@
-|ex9
-CLOCK_50 => CLOCK_50.IN1
-KEY[0] => _.IN1
-KEY[1] => ~NO_FANOUT~
-KEY[2] => ~NO_FANOUT~
-KEY[3] => _.IN1
-HEX0[0] << hex_to_7seg:SEG0.port0
-HEX0[1] << hex_to_7seg:SEG0.port0
-HEX0[2] << hex_to_7seg:SEG0.port0
-HEX0[3] << hex_to_7seg:SEG0.port0
-HEX0[4] << hex_to_7seg:SEG0.port0
-HEX0[5] << hex_to_7seg:SEG0.port0
-HEX0[6] << hex_to_7seg:SEG0.port0
-HEX1[0] << hex_to_7seg:SEG1.port0
-HEX1[1] << hex_to_7seg:SEG1.port0
-HEX1[2] << hex_to_7seg:SEG1.port0
-HEX1[3] << hex_to_7seg:SEG1.port0
-HEX1[4] << hex_to_7seg:SEG1.port0
-HEX1[5] << hex_to_7seg:SEG1.port0
-HEX1[6] << hex_to_7seg:SEG1.port0
-HEX2[0] << hex_to_7seg:SEG2.port0
-HEX2[1] << hex_to_7seg:SEG2.port0
-HEX2[2] << hex_to_7seg:SEG2.port0
-HEX2[3] << hex_to_7seg:SEG2.port0
-HEX2[4] << hex_to_7seg:SEG2.port0
-HEX2[5] << hex_to_7seg:SEG2.port0
-HEX2[6] << hex_to_7seg:SEG2.port0
-HEX3[0] << hex_to_7seg:SEG3.port0
-HEX3[1] << hex_to_7seg:SEG3.port0
-HEX3[2] << hex_to_7seg:SEG3.port0
-HEX3[3] << hex_to_7seg:SEG3.port0
-HEX3[4] << hex_to_7seg:SEG3.port0
-HEX3[5] << hex_to_7seg:SEG3.port0
-HEX3[6] << hex_to_7seg:SEG3.port0
-HEX4[0] << hex_to_7seg:SEG4.port0
-HEX4[1] << hex_to_7seg:SEG4.port0
-HEX4[2] << hex_to_7seg:SEG4.port0
-HEX4[3] << hex_to_7seg:SEG4.port0
-HEX4[4] << hex_to_7seg:SEG4.port0
-HEX4[5] << hex_to_7seg:SEG4.port0
-HEX4[6] << hex_to_7seg:SEG4.port0
-HEX5[0] << hex_to_7seg:SEG5.port0
-HEX5[1] << hex_to_7seg:SEG5.port0
-HEX5[2] << hex_to_7seg:SEG5.port0
-HEX5[3] << hex_to_7seg:SEG5.port0
-HEX5[4] << hex_to_7seg:SEG5.port0
-HEX5[5] << hex_to_7seg:SEG5.port0
-HEX5[6] << hex_to_7seg:SEG5.port0
-LEDR[0] << formula_fsm:FSM.port5
-LEDR[1] << formula_fsm:FSM.port5
-LEDR[2] << formula_fsm:FSM.port5
-LEDR[3] << formula_fsm:FSM.port5
-LEDR[4] << formula_fsm:FSM.port5
-LEDR[5] << formula_fsm:FSM.port5
-LEDR[6] << formula_fsm:FSM.port5
-LEDR[7] << formula_fsm:FSM.port5
-LEDR[8] << formula_fsm:FSM.port5
-LEDR[9] << formula_fsm:FSM.port5
-
-
-|ex9|tick_50000:TICK0
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => count[12].CLK
-CLOCK_IN => count[13].CLK
-CLOCK_IN => count[14].CLK
-CLOCK_IN => count[15].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|formula_fsm:FSM
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => count[9].CLK
-clk => count[10].CLK
-clk => count[11].CLK
-clk => ledr[0]~reg0.CLK
-clk => ledr[1]~reg0.CLK
-clk => ledr[2]~reg0.CLK
-clk => ledr[3]~reg0.CLK
-clk => ledr[4]~reg0.CLK
-clk => ledr[5]~reg0.CLK
-clk => ledr[6]~reg0.CLK
-clk => ledr[7]~reg0.CLK
-clk => ledr[8]~reg0.CLK
-clk => ledr[9]~reg0.CLK
-clk => state~3.DATAIN
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
-start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
-ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|LFSR:LFSR0
-CLK => COUNT[1]~reg0.CLK
-CLK => COUNT[2]~reg0.CLK
-CLK => COUNT[3]~reg0.CLK
-CLK => COUNT[4]~reg0.CLK
-CLK => COUNT[5]~reg0.CLK
-CLK => COUNT[6]~reg0.CLK
-CLK => COUNT[7]~reg0.CLK
-en => COUNT[1]~reg0.ENA
-en => COUNT[2]~reg0.ENA
-en => COUNT[3]~reg0.ENA
-en => COUNT[4]~reg0.ENA
-en => COUNT[5]~reg0.ENA
-en => COUNT[6]~reg0.ENA
-en => COUNT[7]~reg0.ENA
-COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|delay:DEL0
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => count[9].CLK
-clk => count[10].CLK
-clk => count[11].CLK
-clk => count[12].CLK
-clk => count[13].CLK
-clk => state~4.DATAIN
-N[0] => count.DATAB
-N[1] => count.DATAB
-N[2] => count.DATAB
-N[3] => count.DATAB
-N[4] => count.DATAB
-N[5] => count.DATAB
-N[6] => count.DATAB
-N[7] => ~NO_FANOUT~
-N[8] => ~NO_FANOUT~
-N[9] => ~NO_FANOUT~
-N[10] => ~NO_FANOUT~
-N[11] => ~NO_FANOUT~
-N[12] => ~NO_FANOUT~
-N[13] => ~NO_FANOUT~
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector17.IN3
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector14.IN2
-time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|counter_16:COUNT0
-clock => count[0]~reg0.CLK
-clock => count[1]~reg0.CLK
-clock => count[2]~reg0.CLK
-clock => count[3]~reg0.CLK
-clock => count[4]~reg0.CLK
-clock => count[5]~reg0.CLK
-clock => count[6]~reg0.CLK
-clock => count[7]~reg0.CLK
-clock => count[8]~reg0.CLK
-clock => count[9]~reg0.CLK
-clock => count[10]~reg0.CLK
-clock => count[11]~reg0.CLK
-clock => count[12]~reg0.CLK
-clock => count[13]~reg0.CLK
-clock => count[14]~reg0.CLK
-clock => count[15]~reg0.CLK
-clock => state.CLK
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => state.OUTPUTSELECT
-stop => state.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD
-B[0] => BCD_0[0].DATAIN
-B[1] => w35[0].IN1
-B[2] => w30[0].IN1
-B[3] => w26[0].IN1
-B[4] => w22[0].IN1
-B[5] => w18[0].IN1
-B[6] => w15[0].IN1
-B[7] => w12[0].IN1
-B[8] => w9[0].IN1
-B[9] => w7[0].IN1
-B[10] => w5[0].IN1
-B[11] => w3[0].IN1
-B[12] => w2[0].IN1
-B[13] => w1[0].IN1
-B[14] => w1[1].IN1
-B[15] => w1[2].IN1
-BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
-BCD_0[1] <= add3_ge5:A35.port1
-BCD_0[2] <= add3_ge5:A35.port1
-BCD_0[3] <= add3_ge5:A35.port1
-BCD_1[0] <= add3_ge5:A35.port1
-BCD_1[1] <= add3_ge5:A34.port1
-BCD_1[2] <= add3_ge5:A34.port1
-BCD_1[3] <= add3_ge5:A34.port1
-BCD_2[0] <= add3_ge5:A34.port1
-BCD_2[1] <= add3_ge5:A33.port1
-BCD_2[2] <= add3_ge5:A33.port1
-BCD_2[3] <= add3_ge5:A33.port1
-BCD_3[0] <= add3_ge5:A33.port1
-BCD_3[1] <= add3_ge5:A32.port1
-BCD_3[2] <= add3_ge5:A32.port1
-BCD_3[3] <= add3_ge5:A32.port1
-BCD_4[0] <= add3_ge5:A32.port1
-BCD_4[1] <= add3_ge5:A31.port1
-BCD_4[2] <= add3_ge5:A31.port1
-BCD_4[3] <= add3_ge5:A31.port1
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A1
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A2
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A3
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A4
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A5
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A6
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A7
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A8
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A9
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A10
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A11
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A12
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A13
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A14
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A15
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A16
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A17
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A18
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A19
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A20
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A21
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A22
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A23
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A24
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A25
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A26
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A27
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A28
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A29
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A30
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A31
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A32
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A33
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A34
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A35
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|hex_to_7seg:SEG0
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG1
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG2
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG3
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG4
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG5
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
+|ex9
+CLOCK_50 => CLOCK_50.IN1
+KEY[0] => _.IN1
+KEY[1] => ~NO_FANOUT~
+KEY[2] => ~NO_FANOUT~
+KEY[3] => _.IN1
+HEX0[0] <= hex_to_7seg:SEG0.port0
+HEX0[1] <= hex_to_7seg:SEG0.port0
+HEX0[2] <= hex_to_7seg:SEG0.port0
+HEX0[3] <= hex_to_7seg:SEG0.port0
+HEX0[4] <= hex_to_7seg:SEG0.port0
+HEX0[5] <= hex_to_7seg:SEG0.port0
+HEX0[6] <= hex_to_7seg:SEG0.port0
+HEX1[0] <= hex_to_7seg:SEG1.port0
+HEX1[1] <= hex_to_7seg:SEG1.port0
+HEX1[2] <= hex_to_7seg:SEG1.port0
+HEX1[3] <= hex_to_7seg:SEG1.port0
+HEX1[4] <= hex_to_7seg:SEG1.port0
+HEX1[5] <= hex_to_7seg:SEG1.port0
+HEX1[6] <= hex_to_7seg:SEG1.port0
+HEX2[0] <= hex_to_7seg:SEG2.port0
+HEX2[1] <= hex_to_7seg:SEG2.port0
+HEX2[2] <= hex_to_7seg:SEG2.port0
+HEX2[3] <= hex_to_7seg:SEG2.port0
+HEX2[4] <= hex_to_7seg:SEG2.port0
+HEX2[5] <= hex_to_7seg:SEG2.port0
+HEX2[6] <= hex_to_7seg:SEG2.port0
+HEX3[0] <= hex_to_7seg:SEG3.port0
+HEX3[1] <= hex_to_7seg:SEG3.port0
+HEX3[2] <= hex_to_7seg:SEG3.port0
+HEX3[3] <= hex_to_7seg:SEG3.port0
+HEX3[4] <= hex_to_7seg:SEG3.port0
+HEX3[5] <= hex_to_7seg:SEG3.port0
+HEX3[6] <= hex_to_7seg:SEG3.port0
+HEX4[0] <= hex_to_7seg:SEG4.port0
+HEX4[1] <= hex_to_7seg:SEG4.port0
+HEX4[2] <= hex_to_7seg:SEG4.port0
+HEX4[3] <= hex_to_7seg:SEG4.port0
+HEX4[4] <= hex_to_7seg:SEG4.port0
+HEX4[5] <= hex_to_7seg:SEG4.port0
+HEX4[6] <= hex_to_7seg:SEG4.port0
+HEX5[0] <= hex_to_7seg:SEG5.port0
+HEX5[1] <= hex_to_7seg:SEG5.port0
+HEX5[2] <= hex_to_7seg:SEG5.port0
+HEX5[3] <= hex_to_7seg:SEG5.port0
+HEX5[4] <= hex_to_7seg:SEG5.port0
+HEX5[5] <= hex_to_7seg:SEG5.port0
+HEX5[6] <= hex_to_7seg:SEG5.port0
+LEDR[0] <= formula_fsm:FSM.port5
+LEDR[1] <= formula_fsm:FSM.port5
+LEDR[2] <= formula_fsm:FSM.port5
+LEDR[3] <= formula_fsm:FSM.port5
+LEDR[4] <= formula_fsm:FSM.port5
+LEDR[5] <= formula_fsm:FSM.port5
+LEDR[6] <= formula_fsm:FSM.port5
+LEDR[7] <= formula_fsm:FSM.port5
+LEDR[8] <= formula_fsm:FSM.port5
+LEDR[9] <= formula_fsm:FSM.port5
+
+
+|ex9|tick_50000:TICK0
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => count[12].CLK
+CLOCK_IN => count[13].CLK
+CLOCK_IN => count[14].CLK
+CLOCK_IN => count[15].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|formula_fsm:FSM
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => ledr[0]~reg0.CLK
+clk => ledr[1]~reg0.CLK
+clk => ledr[2]~reg0.CLK
+clk => ledr[3]~reg0.CLK
+clk => ledr[4]~reg0.CLK
+clk => ledr[5]~reg0.CLK
+clk => ledr[6]~reg0.CLK
+clk => ledr[7]~reg0.CLK
+clk => ledr[8]~reg0.CLK
+clk => ledr[9]~reg0.CLK
+clk => state~3.DATAIN
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
+start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
+ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|LFSR:LFSR0
+CLK => COUNT[1]~reg0.CLK
+CLK => COUNT[2]~reg0.CLK
+CLK => COUNT[3]~reg0.CLK
+CLK => COUNT[4]~reg0.CLK
+CLK => COUNT[5]~reg0.CLK
+CLK => COUNT[6]~reg0.CLK
+CLK => COUNT[7]~reg0.CLK
+en => COUNT[1]~reg0.ENA
+en => COUNT[2]~reg0.ENA
+en => COUNT[3]~reg0.ENA
+en => COUNT[4]~reg0.ENA
+en => COUNT[5]~reg0.ENA
+en => COUNT[6]~reg0.ENA
+en => COUNT[7]~reg0.ENA
+COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|delay:DEL0
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => count[10].CLK
+clk => count[11].CLK
+clk => count[12].CLK
+clk => count[13].CLK
+clk => state~4.DATAIN
+N[0] => count.DATAB
+N[1] => count.DATAB
+N[2] => count.DATAB
+N[3] => count.DATAB
+N[4] => count.DATAB
+N[5] => count.DATAB
+N[6] => count.DATAB
+N[7] => ~NO_FANOUT~
+N[8] => ~NO_FANOUT~
+N[9] => ~NO_FANOUT~
+N[10] => ~NO_FANOUT~
+N[11] => ~NO_FANOUT~
+N[12] => ~NO_FANOUT~
+N[13] => ~NO_FANOUT~
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => Selector17.IN3
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => Selector14.IN2
+time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|counter_16:COUNT0
+clock => count[0]~reg0.CLK
+clock => count[1]~reg0.CLK
+clock => count[2]~reg0.CLK
+clock => count[3]~reg0.CLK
+clock => count[4]~reg0.CLK
+clock => count[5]~reg0.CLK
+clock => count[6]~reg0.CLK
+clock => count[7]~reg0.CLK
+clock => count[8]~reg0.CLK
+clock => count[9]~reg0.CLK
+clock => count[10]~reg0.CLK
+clock => count[11]~reg0.CLK
+clock => count[12]~reg0.CLK
+clock => count[13]~reg0.CLK
+clock => count[14]~reg0.CLK
+clock => count[15]~reg0.CLK
+clock => state.CLK
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => state.OUTPUTSELECT
+stop => state.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD
+B[0] => BCD_0[0].DATAIN
+B[1] => w35[0].IN1
+B[2] => w30[0].IN1
+B[3] => w26[0].IN1
+B[4] => w22[0].IN1
+B[5] => w18[0].IN1
+B[6] => w15[0].IN1
+B[7] => w12[0].IN1
+B[8] => w9[0].IN1
+B[9] => w7[0].IN1
+B[10] => w5[0].IN1
+B[11] => w3[0].IN1
+B[12] => w2[0].IN1
+B[13] => w1[0].IN1
+B[14] => w1[1].IN1
+B[15] => w1[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A35.port1
+BCD_0[2] <= add3_ge5:A35.port1
+BCD_0[3] <= add3_ge5:A35.port1
+BCD_1[0] <= add3_ge5:A35.port1
+BCD_1[1] <= add3_ge5:A34.port1
+BCD_1[2] <= add3_ge5:A34.port1
+BCD_1[3] <= add3_ge5:A34.port1
+BCD_2[0] <= add3_ge5:A34.port1
+BCD_2[1] <= add3_ge5:A33.port1
+BCD_2[2] <= add3_ge5:A33.port1
+BCD_2[3] <= add3_ge5:A33.port1
+BCD_3[0] <= add3_ge5:A33.port1
+BCD_3[1] <= add3_ge5:A32.port1
+BCD_3[2] <= add3_ge5:A32.port1
+BCD_3[3] <= add3_ge5:A32.port1
+BCD_4[0] <= add3_ge5:A32.port1
+BCD_4[1] <= add3_ge5:A31.port1
+BCD_4[2] <= add3_ge5:A31.port1
+BCD_4[3] <= add3_ge5:A31.port1
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A1
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A2
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A3
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A4
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A5
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A6
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A7
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A8
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A9
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A10
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A11
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A12
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A13
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A14
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A15
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A16
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A17
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A18
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A19
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A20
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A21
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A22
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A23
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A24
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A25
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A26
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A27
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A28
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A29
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A30
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A31
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A32
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A33
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A34
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A35
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG3
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG4
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG5
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diff --git a/part_2/ex9/db/ex9.hif b/part_2/ex9/db/ex9.hif
index 72b4f73..71330c9 100644
--- a/part_2/ex9/db/ex9.hif
+++ b/part_2/ex9/db/ex9.hif
Binary files differ
diff --git a/part_2/ex9/db/ex9.lpc.html b/part_2/ex9/db/ex9.lpc.html
index 795349d..66398b2 100644
--- a/part_2/ex9/db/ex9.lpc.html
+++ b/part_2/ex9/db/ex9.lpc.html
@@ -1,770 +1,770 @@
-<TABLE>
-<TR bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-<TR >
-<TD >SEG5</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >7</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG3</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG1</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A35</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A34</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A33</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A32</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A31</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A30</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A29</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A28</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A27</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A26</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A25</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A24</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A23</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A22</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A21</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A20</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A19</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A18</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A17</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A16</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A15</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A14</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A13</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A12</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A11</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A10</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A9</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A8</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A7</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A6</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A5</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A4</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A3</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD</TD>
-<TD >16</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >20</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >COUNT0</TD>
-<TD >3</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >16</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >DEL0</TD>
-<TD >16</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >1</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >LFSR0</TD>
-<TD >2</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >FSM</TD>
-<TD >3</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >12</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >TICK0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-</TABLE>
+<TABLE>
+<TR bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG5</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >7</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A35</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A34</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A33</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A32</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A31</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A30</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A29</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A28</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A27</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A26</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A25</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A24</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A23</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A22</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A21</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A20</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A19</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A18</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A17</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A16</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A15</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A14</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A13</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A12</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A11</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A10</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A9</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A4</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >COUNT0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >DEL0</TD>
+<TD >16</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >1</TD>
+<TD >7</TD>
+<TD >7</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >LFSR0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >FSM</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >TICK0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_2/ex9/db/ex9.lpc.rdb b/part_2/ex9/db/ex9.lpc.rdb
index 9db0391..a762277 100644
--- a/part_2/ex9/db/ex9.lpc.rdb
+++ b/part_2/ex9/db/ex9.lpc.rdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.lpc.txt b/part_2/ex9/db/ex9.lpc.txt
index 538b3bf..d85a84b 100644
--- a/part_2/ex9/db/ex9.lpc.txt
+++ b/part_2/ex9/db/ex9.lpc.txt
@@ -1,53 +1,53 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; SEG5 ; 4 ; 4 ; 0 ; 4 ; 7 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; SEG4 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; SEG3 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; SEG2 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; SEG1 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; SEG0 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A35 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A34 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A33 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A32 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A31 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A30 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A29 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A28 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A27 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A26 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A25 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A24 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A23 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A22 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A21 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A20 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A19 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A18 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A17 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A16 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A15 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A14 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A13 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A12 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A11 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A10 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A9 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A8 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A7 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A6 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A5 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A4 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A3 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A2 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD|A1 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; BCD ; 16 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; COUNT0 ; 3 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; DEL0 ; 16 ; 7 ; 0 ; 7 ; 1 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; LFSR0 ; 2 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; FSM ; 3 ; 0 ; 0 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; TICK0 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG5 ; 4 ; 4 ; 0 ; 4 ; 7 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG4 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG3 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG2 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG1 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; SEG0 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A35 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A34 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A33 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A32 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A31 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A30 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A29 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A28 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A27 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A26 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A25 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A24 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A23 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A22 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A21 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A20 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A19 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A18 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A17 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A16 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A15 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A14 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A13 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A12 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A11 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A10 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A9 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A8 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A7 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A6 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A5 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A4 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A3 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A2 ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD|A1 ; 4 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; BCD ; 16 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; COUNT0 ; 3 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; DEL0 ; 16 ; 7 ; 0 ; 7 ; 1 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; LFSR0 ; 2 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; FSM ; 3 ; 0 ; 0 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; TICK0 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_2/ex9/db/ex9.map.ammdb b/part_2/ex9/db/ex9.map.ammdb
index 174eb00..a4afc79 100644
--- a/part_2/ex9/db/ex9.map.ammdb
+++ b/part_2/ex9/db/ex9.map.ammdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.map.bpm b/part_2/ex9/db/ex9.map.bpm
index 1016d90..bd51c17 100644
--- a/part_2/ex9/db/ex9.map.bpm
+++ b/part_2/ex9/db/ex9.map.bpm
Binary files differ
diff --git a/part_2/ex9/db/ex9.map.cdb b/part_2/ex9/db/ex9.map.cdb
index 3bfd4b0..1d4ff12 100644
--- a/part_2/ex9/db/ex9.map.cdb
+++ b/part_2/ex9/db/ex9.map.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.map.hdb b/part_2/ex9/db/ex9.map.hdb
index 1b64dd1..180812a 100644
--- a/part_2/ex9/db/ex9.map.hdb
+++ b/part_2/ex9/db/ex9.map.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.map.kpt b/part_2/ex9/db/ex9.map.kpt
index 537bff0..59f8096 100644
--- a/part_2/ex9/db/ex9.map.kpt
+++ b/part_2/ex9/db/ex9.map.kpt
Binary files differ
diff --git a/part_2/ex9/db/ex9.map.logdb b/part_2/ex9/db/ex9.map.logdb
index d45424f..626799f 100644
--- a/part_2/ex9/db/ex9.map.logdb
+++ b/part_2/ex9/db/ex9.map.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex9/db/ex9.map.qmsg b/part_2/ex9/db/ex9.map.qmsg
index 0c6e7c8..31b3a95 100644
--- a/part_2/ex9/db/ex9.map.qmsg
+++ b/part_2/ex9/db/ex9.map.qmsg
@@ -1,73 +1,73 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112434281 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112434284 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:07:13 2016 " "Processing started: Wed Dec 07 12:07:13 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112434284 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112434284 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112434284 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481112434902 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481112434902 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" { } { { "verilog_files/tick_50000.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443515 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" { } { { "verilog_files/LFSR.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443519 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443523 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 38 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481112443527 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443528 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443528 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" { } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443536 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" { } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443536 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443536 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" { } { { "verilog_files/counter_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443540 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443540 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443543 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443548 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443548 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443548 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443552 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443552 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" { } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443555 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443555 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481112443627 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" { } { { "verilog_files/ex9.v" "TICK0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443633 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" { } { { "verilog_files/ex9.v" "FSM" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 16 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443637 ""}
-{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 39 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
-{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
-{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" { } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" { } { { "verilog_files/ex9.v" "LFSR0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443643 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" { } { { "verilog_files/ex9.v" "DEL0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443647 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" { } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481112443648 "|ex9|delay:DEL0"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" { } { { "verilog_files/ex9.v" "COUNT0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 22 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443692 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" { } { { "verilog_files/ex9.v" "BCD" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443714 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_16.v" "A1" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443719 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "verilog_files/ex9.v" "SEG0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443728 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481112444476 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" { } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481112444661 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481112444740 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481112445211 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112445296 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481112445625 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112445625 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" { } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112446084 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" { } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112446084 "|ex9|KEY[2]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481112446084 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "354 " "Implemented 354 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481112446087 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481112446087 ""} { "Info" "ICUT_CUT_TM_LCELLS" "297 " "Implemented 297 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481112446087 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481112446087 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "918 " "Peak virtual memory: 918 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:07:26 2016 " "Processing ended: Wed Dec 07 12:07:26 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112446141 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481488205223 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481488205230 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:30:05 2016 " "Processing started: Sun Dec 11 20:30:05 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481488205230 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488205230 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488205231 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481488205451 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481488205451 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" { } { { "verilog_files/tick_50000.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/tick_50000.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214169 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214169 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/LFSR.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/LFSR.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" { } { { "verilog_files/LFSR.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/LFSR.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214170 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214170 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/hex_to_7seg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214177 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214177 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v" 38 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481488214178 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214178 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214178 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" { } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v" 7 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214181 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" { } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214181 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214181 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" { } { { "verilog_files/counter_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/counter_16.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214189 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214189 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214196 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214196 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214198 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/add3_ge5.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214204 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214204 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" { } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214204 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214204 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481488214245 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" { } { { "verilog_files/ex9.v" "TICK0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214253 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" { } { { "verilog_files/ex9.v" "FSM" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 16 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214258 ""}
+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v" 39 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481488214259 "|ex9|formula_fsm:FSM"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v" 58 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481488214259 "|ex9|formula_fsm:FSM"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" { } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v" 58 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214259 "|ex9|formula_fsm:FSM"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" { } { { "verilog_files/ex9.v" "LFSR0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214264 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" { } { { "verilog_files/ex9.v" "DEL0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214266 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" { } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481488214267 "|ex9|delay:DEL0"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" { } { { "verilog_files/ex9.v" "COUNT0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 22 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214272 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" { } { { "verilog_files/ex9.v" "BCD" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214275 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_16.v" "A1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214283 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" { } { { "verilog_files/ex9.v" "SEG0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214293 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481488214702 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" { } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" { } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481488214855 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481488214913 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481488215194 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.map.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488215217 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481488215297 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488215297 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" { } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481488215352 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" { } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481488215352 "|ex9|KEY[2]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481488215352 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "345 " "Implemented 345 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481488215353 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481488215353 ""} { "Info" "ICUT_CUT_TM_LCELLS" "288 " "Implemented 288 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481488215353 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481488215353 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1067 " "Peak virtual memory: 1067 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481488215362 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:30:15 2016 " "Processing ended: Sun Dec 11 20:30:15 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481488215362 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481488215362 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481488215362 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488215362 ""}
diff --git a/part_2/ex9/db/ex9.map.rdb b/part_2/ex9/db/ex9.map.rdb
index 68fd1db..c4fa58d 100644
--- a/part_2/ex9/db/ex9.map.rdb
+++ b/part_2/ex9/db/ex9.map.rdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.map_bb.cdb b/part_2/ex9/db/ex9.map_bb.cdb
index bf85f94..18feadc 100644
--- a/part_2/ex9/db/ex9.map_bb.cdb
+++ b/part_2/ex9/db/ex9.map_bb.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.map_bb.hdb b/part_2/ex9/db/ex9.map_bb.hdb
index 490d26d..d02e0ee 100644
--- a/part_2/ex9/db/ex9.map_bb.hdb
+++ b/part_2/ex9/db/ex9.map_bb.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.map_bb.logdb b/part_2/ex9/db/ex9.map_bb.logdb
index d45424f..626799f 100644
--- a/part_2/ex9/db/ex9.map_bb.logdb
+++ b/part_2/ex9/db/ex9.map_bb.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex9/db/ex9.pre_map.hdb b/part_2/ex9/db/ex9.pre_map.hdb
index ee4dd3e..b18d89e 100644
--- a/part_2/ex9/db/ex9.pre_map.hdb
+++ b/part_2/ex9/db/ex9.pre_map.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.quiproj.2651.rdr.flock b/part_2/ex9/db/ex9.quiproj.2651.rdr.flock
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex9/db/ex9.quiproj.2651.rdr.flock
diff --git a/part_2/ex9/db/ex9.root_partition.map.reg_db.cdb b/part_2/ex9/db/ex9.root_partition.map.reg_db.cdb
index c515539..de4e15b 100644
--- a/part_2/ex9/db/ex9.root_partition.map.reg_db.cdb
+++ b/part_2/ex9/db/ex9.root_partition.map.reg_db.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.routing.rdb b/part_2/ex9/db/ex9.routing.rdb
index e96d120..6d15c42 100644
--- a/part_2/ex9/db/ex9.routing.rdb
+++ b/part_2/ex9/db/ex9.routing.rdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.rtlv.hdb b/part_2/ex9/db/ex9.rtlv.hdb
index 4ef2452..1194309 100644
--- a/part_2/ex9/db/ex9.rtlv.hdb
+++ b/part_2/ex9/db/ex9.rtlv.hdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.rtlv_sg.cdb b/part_2/ex9/db/ex9.rtlv_sg.cdb
index 59f14dd..cda087a 100644
--- a/part_2/ex9/db/ex9.rtlv_sg.cdb
+++ b/part_2/ex9/db/ex9.rtlv_sg.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.rtlv_sg_swap.cdb b/part_2/ex9/db/ex9.rtlv_sg_swap.cdb
index b693e9a..fab1f8c 100644
--- a/part_2/ex9/db/ex9.rtlv_sg_swap.cdb
+++ b/part_2/ex9/db/ex9.rtlv_sg_swap.cdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.sld_design_entry.sci b/part_2/ex9/db/ex9.sld_design_entry.sci
index 92c1102..03eacdc 100644
--- a/part_2/ex9/db/ex9.sld_design_entry.sci
+++ b/part_2/ex9/db/ex9.sld_design_entry.sci
Binary files differ
diff --git a/part_2/ex9/db/ex9.sld_design_entry_dsc.sci b/part_2/ex9/db/ex9.sld_design_entry_dsc.sci
index 92c1102..03eacdc 100644
--- a/part_2/ex9/db/ex9.sld_design_entry_dsc.sci
+++ b/part_2/ex9/db/ex9.sld_design_entry_dsc.sci
Binary files differ
diff --git a/part_2/ex9/db/ex9.smart_action.txt b/part_2/ex9/db/ex9.smart_action.txt
index 437a63e..c8e8a13 100644
--- a/part_2/ex9/db/ex9.smart_action.txt
+++ b/part_2/ex9/db/ex9.smart_action.txt
@@ -1 +1 @@
-DONE
+DONE
diff --git a/part_2/ex9/db/ex9.smp_dump.txt b/part_2/ex9/db/ex9.smp_dump.txt
index 26e74f6..bd2b24e 100644
--- a/part_2/ex9/db/ex9.smp_dump.txt
+++ b/part_2/ex9/db/ex9.smp_dump.txt
@@ -1,13 +1,13 @@
-
-State Machine - |ex9|delay:DEL0|state
-Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE
-state.IDLE 0 0 0 0
-state.COUNTING 0 0 1 1
-state.TIME_OUT 0 1 0 1
-state.WAIT_LOW 1 0 0 1
-
-State Machine - |ex9|formula_fsm:FSM|state
-Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS
-state.WAIT_TRIGGER 0 0 0
-state.LIGHT_UP_LEDS 1 0 1
-state.WAIT_FOR_TIMEOUT 1 1 0
+
+State Machine - |ex9|delay:DEL0|state
+Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE
+state.IDLE 0 0 0 0
+state.COUNTING 0 0 1 1
+state.TIME_OUT 0 1 0 1
+state.WAIT_LOW 1 0 0 1
+
+State Machine - |ex9|formula_fsm:FSM|state
+Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS
+state.WAIT_TRIGGER 0 0 0
+state.LIGHT_UP_LEDS 1 0 1
+state.WAIT_FOR_TIMEOUT 1 1 0
diff --git a/part_2/ex9/db/ex9.sta.qmsg b/part_2/ex9/db/ex9.sta.qmsg
index aab3a60..6d964db 100644
--- a/part_2/ex9/db/ex9.sta.qmsg
+++ b/part_2/ex9/db/ex9.sta.qmsg
@@ -1,53 +1,53 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112502374 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112502377 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:08:21 2016 " "Processing started: Wed Dec 07 12:08:21 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112502377 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112502377 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112502378 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112502505 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503130 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503130 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503180 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503180 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503779 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503861 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503862 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503864 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503869 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503894 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112503895 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112503939 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112503972 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503972 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.462 " "Worst-case setup slack is -3.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.462 -161.413 tick_50000:TICK0\|CLK_OUT " " -3.462 -161.413 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.047 -40.775 CLOCK_50 " " -2.047 -40.775 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.675 -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -1.675 -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503984 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 tick_50000:TICK0\|CLK_OUT " " 0.179 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.385 0.000 CLOCK_50 " " 0.385 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.629 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.629 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504002 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504013 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504023 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.637 " "Worst-case minimum pulse width slack is -0.637" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.637 -18.132 CLOCK_50 " " -0.637 -18.132 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.394 -38.762 tick_50000:TICK0\|CLK_OUT " " -0.394 -38.762 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.459 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.459 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504032 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112504054 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504090 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505120 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505353 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112505409 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505409 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.416 " "Worst-case setup slack is -3.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.416 -157.230 tick_50000:TICK0\|CLK_OUT " " -3.416 -157.230 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.323 -41.799 CLOCK_50 " " -2.323 -41.799 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.568 -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -1.568 -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505436 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 tick_50000:TICK0\|CLK_OUT " " 0.193 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.405 0.000 CLOCK_50 " " 0.405 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.501 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.501 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505454 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505465 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505488 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.689 " "Worst-case minimum pulse width slack is -0.689" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.689 -16.816 CLOCK_50 " " -0.689 -16.816 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.394 -38.286 tick_50000:TICK0\|CLK_OUT " " -0.394 -38.286 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.412 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.412 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505519 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112505541 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505804 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506731 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506844 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112506847 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506847 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.794 " "Worst-case setup slack is -1.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.794 -79.872 tick_50000:TICK0\|CLK_OUT " " -1.794 -79.872 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.918 -13.912 CLOCK_50 " " -0.918 -13.912 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.572 -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -0.572 -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506855 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.020 " "Worst-case hold slack is -0.020" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.020 -0.037 tick_50000:TICK0\|CLK_OUT " " -0.020 -0.037 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.185 0.000 CLOCK_50 " " 0.185 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.202 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.202 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506866 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506875 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506884 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.740 " "Worst-case minimum pulse width slack is -0.740" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.740 -12.957 CLOCK_50 " " -0.740 -12.957 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.012 -0.190 tick_50000:TICK0\|CLK_OUT " " -0.012 -0.190 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.478 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.478 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506893 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112506923 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507323 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112507325 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507325 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.581 " "Worst-case setup slack is -1.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.581 -69.264 tick_50000:TICK0\|CLK_OUT " " -1.581 -69.264 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.868 -11.639 CLOCK_50 " " -0.868 -11.639 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.462 -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -0.462 -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507338 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.021 " "Worst-case hold slack is -0.021" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.021 -0.052 tick_50000:TICK0\|CLK_OUT " " -0.021 -0.052 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.122 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.122 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 CLOCK_50 " " 0.177 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507349 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507359 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507368 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.789 " "Worst-case minimum pulse width slack is -0.789" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.789 -15.486 CLOCK_50 " " -0.789 -15.486 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.024 0.000 tick_50000:TICK0\|CLK_OUT " " 0.024 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.468 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.468 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507377 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112509824 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112509826 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1213 " "Peak virtual memory: 1213 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:30 2016 " "Processing ended: Wed Dec 07 12:08:30 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112510016 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481488260359 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481488260364 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:31:00 2016 " "Processing started: Sun Dec 11 20:31:00 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481488260364 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260364 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260364 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488260408 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260942 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260942 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260979 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260979 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261468 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261488 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261488 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481488261490 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481488261490 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481488261490 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261490 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261491 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261500 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488261501 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488261507 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481488261525 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261525 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.933 " "Worst-case setup slack is -3.933" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261525 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261525 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.933 -177.510 tick_50000:TICK0\|CLK_OUT " " -3.933 -177.510 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261525 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.353 -2.353 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -2.353 -2.353 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261525 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.198 -38.652 CLOCK_50 " " -2.198 -38.652 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261525 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261525 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.222 " "Worst-case hold slack is 0.222" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.222 0.000 tick_50000:TICK0\|CLK_OUT " " 0.222 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.381 0.000 CLOCK_50 " " 0.381 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.023 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 1.023 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261527 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261527 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261528 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261528 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.658 " "Worst-case minimum pulse width slack is -0.658" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.658 -17.489 CLOCK_50 " " -0.658 -17.489 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.394 -41.338 tick_50000:TICK0\|CLK_OUT " " -0.394 -41.338 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.439 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.439 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261528 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261528 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488261535 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261565 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262445 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262515 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481488262519 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262519 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.867 " "Worst-case setup slack is -3.867" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262520 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262520 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.867 -173.770 tick_50000:TICK0\|CLK_OUT " " -3.867 -173.770 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262520 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.391 -39.269 CLOCK_50 " " -2.391 -39.269 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262520 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.208 -2.208 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -2.208 -2.208 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262520 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262520 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.218 " "Worst-case hold slack is 0.218" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.218 0.000 tick_50000:TICK0\|CLK_OUT " " 0.218 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 CLOCK_50 " " 0.401 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.821 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.821 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262521 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262521 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262522 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262523 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.707 " "Worst-case minimum pulse width slack is -0.707" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.707 -16.083 CLOCK_50 " " -0.707 -16.083 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.394 -42.153 tick_50000:TICK0\|CLK_OUT " " -0.394 -42.153 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.422 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.422 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262523 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262523 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488262529 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262660 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263437 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263511 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481488263514 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263514 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.263 " "Worst-case setup slack is -2.263" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.263 -94.992 tick_50000:TICK0\|CLK_OUT " " -2.263 -94.992 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.029 -1.029 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -1.029 -1.029 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.002 -13.129 CLOCK_50 " " -1.002 -13.129 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263515 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263515 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.065 " "Worst-case hold slack is 0.065" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.065 0.000 tick_50000:TICK0\|CLK_OUT " " 0.065 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.184 0.000 CLOCK_50 " " 0.184 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.518 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.518 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263517 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263517 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263518 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263518 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.771 " "Worst-case minimum pulse width slack is -0.771" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.771 -12.597 CLOCK_50 " " -0.771 -12.597 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.035 -1.610 tick_50000:TICK0\|CLK_OUT " " -0.035 -1.610 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.481 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.481 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263519 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263519 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488263526 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263693 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481488263695 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263695 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.967 " "Worst-case setup slack is -1.967" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.967 -82.047 tick_50000:TICK0\|CLK_OUT " " -1.967 -82.047 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.958 -11.100 CLOCK_50 " " -0.958 -11.100 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.846 -0.846 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " -0.846 -0.846 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263695 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263695 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.049 " "Worst-case hold slack is 0.049" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263697 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263697 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.049 0.000 tick_50000:TICK0\|CLK_OUT " " 0.049 0.000 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263697 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.175 0.000 CLOCK_50 " " 0.175 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263697 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.366 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.366 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263697 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263697 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263698 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263698 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.807 " "Worst-case minimum pulse width slack is -0.807" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.807 -14.887 CLOCK_50 " " -0.807 -14.887 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.016 -0.422 tick_50000:TICK0\|CLK_OUT " " -0.016 -0.422 tick_50000:TICK0\|CLK_OUT " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.477 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " " 0.477 0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263699 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263699 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488265239 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488265240 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1216 " "Peak virtual memory: 1216 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481488265279 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:31:05 2016 " "Processing ended: Sun Dec 11 20:31:05 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481488265279 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481488265279 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481488265279 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488265279 ""}
diff --git a/part_2/ex9/db/ex9.sta.rdb b/part_2/ex9/db/ex9.sta.rdb
index 68555e7..e2677ef 100644
--- a/part_2/ex9/db/ex9.sta.rdb
+++ b/part_2/ex9/db/ex9.sta.rdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex9/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
index 6b64eb8..465cbcd 100644
--- a/part_2/ex9/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
+++ b/part_2/ex9/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
Binary files differ
diff --git a/part_2/ex9/db/ex9.tis_db_list.ddb b/part_2/ex9/db/ex9.tis_db_list.ddb
index 88225e8..2df45d7 100644
--- a/part_2/ex9/db/ex9.tis_db_list.ddb
+++ b/part_2/ex9/db/ex9.tis_db_list.ddb
Binary files differ
diff --git a/part_2/ex9/db/ex9.tiscmp.fast_1100mv_0c.ddb b/part_2/ex9/db/ex9.tiscmp.fast_1100mv_0c.ddb
index 921ec00..4719c12 100644
--- a/part_2/ex9/db/ex9.tiscmp.fast_1100mv_0c.ddb
+++ b/part_2/ex9/db/ex9.tiscmp.fast_1100mv_0c.ddb
Binary files differ
diff --git a/part_2/ex9/db/ex9.tiscmp.fast_1100mv_85c.ddb b/part_2/ex9/db/ex9.tiscmp.fast_1100mv_85c.ddb
index 691218d..f953c78 100644
--- a/part_2/ex9/db/ex9.tiscmp.fast_1100mv_85c.ddb
+++ b/part_2/ex9/db/ex9.tiscmp.fast_1100mv_85c.ddb
Binary files differ
diff --git a/part_2/ex9/db/ex9.tiscmp.slow_1100mv_0c.ddb b/part_2/ex9/db/ex9.tiscmp.slow_1100mv_0c.ddb
index fb0a6c4..5d1ccd6 100644
--- a/part_2/ex9/db/ex9.tiscmp.slow_1100mv_0c.ddb
+++ b/part_2/ex9/db/ex9.tiscmp.slow_1100mv_0c.ddb
Binary files differ
diff --git a/part_2/ex9/db/ex9.tiscmp.slow_1100mv_85c.ddb b/part_2/ex9/db/ex9.tiscmp.slow_1100mv_85c.ddb
index 2e4f8b4..137bca4 100644
--- a/part_2/ex9/db/ex9.tiscmp.slow_1100mv_85c.ddb
+++ b/part_2/ex9/db/ex9.tiscmp.slow_1100mv_85c.ddb
Binary files differ
diff --git a/part_2/ex9/db/ex9.tmw_info b/part_2/ex9/db/ex9.tmw_info
index b5caf45..94024cd 100644
--- a/part_2/ex9/db/ex9.tmw_info
+++ b/part_2/ex9/db/ex9.tmw_info
@@ -1,6 +1,6 @@
-start_full_compilation:s:00:01:18
-start_analysis_synthesis:s:00:00:19-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:40-start_full_compilation
-start_assembler:s:00:00:09-start_full_compilation
-start_timing_analyzer:s:00:00:10-start_full_compilation
+start_full_compilation:s:00:01:01
+start_analysis_synthesis:s:00:00:11-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:37-start_full_compilation
+start_assembler:s:00:00:07-start_full_compilation
+start_timing_analyzer:s:00:00:06-start_full_compilation
diff --git a/part_2/ex9/db/ex9.vpr.ammdb b/part_2/ex9/db/ex9.vpr.ammdb
index 51295de..519893b 100644
--- a/part_2/ex9/db/ex9.vpr.ammdb
+++ b/part_2/ex9/db/ex9.vpr.ammdb
Binary files differ
diff --git a/part_2/ex9/db/ex9_partition_pins.json b/part_2/ex9/db/ex9_partition_pins.json
index 701d3b6..f8c0864 100644
--- a/part_2/ex9/db/ex9_partition_pins.json
+++ b/part_2/ex9/db/ex9_partition_pins.json
@@ -1,201 +1,201 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "HEX0[0]",
- "strict" : false
- },
- {
- "name" : "HEX0[1]",
- "strict" : false
- },
- {
- "name" : "HEX0[2]",
- "strict" : false
- },
- {
- "name" : "HEX0[3]",
- "strict" : false
- },
- {
- "name" : "HEX0[4]",
- "strict" : false
- },
- {
- "name" : "HEX0[5]",
- "strict" : false
- },
- {
- "name" : "HEX0[6]",
- "strict" : false
- },
- {
- "name" : "HEX1[0]",
- "strict" : false
- },
- {
- "name" : "HEX1[1]",
- "strict" : false
- },
- {
- "name" : "HEX1[2]",
- "strict" : false
- },
- {
- "name" : "HEX1[3]",
- "strict" : false
- },
- {
- "name" : "HEX1[4]",
- "strict" : false
- },
- {
- "name" : "HEX1[5]",
- "strict" : false
- },
- {
- "name" : "HEX1[6]",
- "strict" : false
- },
- {
- "name" : "HEX2[0]",
- "strict" : false
- },
- {
- "name" : "HEX2[1]",
- "strict" : false
- },
- {
- "name" : "HEX2[2]",
- "strict" : false
- },
- {
- "name" : "HEX2[3]",
- "strict" : false
- },
- {
- "name" : "HEX2[4]",
- "strict" : false
- },
- {
- "name" : "HEX2[5]",
- "strict" : false
- },
- {
- "name" : "HEX2[6]",
- "strict" : false
- },
- {
- "name" : "HEX3[0]",
- "strict" : false
- },
- {
- "name" : "HEX3[1]",
- "strict" : false
- },
- {
- "name" : "HEX3[2]",
- "strict" : false
- },
- {
- "name" : "HEX3[3]",
- "strict" : false
- },
- {
- "name" : "HEX3[4]",
- "strict" : false
- },
- {
- "name" : "HEX3[5]",
- "strict" : false
- },
- {
- "name" : "HEX3[6]",
- "strict" : false
- },
- {
- "name" : "HEX4[0]",
- "strict" : false
- },
- {
- "name" : "HEX4[1]",
- "strict" : false
- },
- {
- "name" : "HEX4[2]",
- "strict" : false
- },
- {
- "name" : "HEX4[3]",
- "strict" : false
- },
- {
- "name" : "HEX4[4]",
- "strict" : false
- },
- {
- "name" : "HEX4[5]",
- "strict" : false
- },
- {
- "name" : "HEX4[6]",
- "strict" : false
- },
- {
- "name" : "LEDR[0]",
- "strict" : false
- },
- {
- "name" : "LEDR[1]",
- "strict" : false
- },
- {
- "name" : "LEDR[2]",
- "strict" : false
- },
- {
- "name" : "LEDR[3]",
- "strict" : false
- },
- {
- "name" : "LEDR[4]",
- "strict" : false
- },
- {
- "name" : "LEDR[5]",
- "strict" : false
- },
- {
- "name" : "LEDR[6]",
- "strict" : false
- },
- {
- "name" : "LEDR[7]",
- "strict" : false
- },
- {
- "name" : "LEDR[8]",
- "strict" : false
- },
- {
- "name" : "LEDR[9]",
- "strict" : false
- },
- {
- "name" : "KEY[0]",
- "strict" : false
- },
- {
- "name" : "CLOCK_50",
- "strict" : false
- },
- {
- "name" : "KEY[3]",
- "strict" : false
- }
- ]
- }
- ]
+{
+ "partitions" : [
+ {
+ "name" : "Top",
+ "pins" : [
+ {
+ "name" : "HEX0[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX0[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX1[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX2[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX3[6]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[0]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[1]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[2]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[3]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[4]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[5]",
+ "strict" : false
+ },
+ {
+ "name" : "HEX4[6]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[0]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[1]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[2]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[3]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[4]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[5]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[6]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[7]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[8]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[9]",
+ "strict" : false
+ },
+ {
+ "name" : "KEY[0]",
+ "strict" : false
+ },
+ {
+ "name" : "CLOCK_50",
+ "strict" : false
+ },
+ {
+ "name" : "KEY[3]",
+ "strict" : false
+ }
+ ]
+ }
+ ]
} \ No newline at end of file
diff --git a/part_2/ex9/ex9.qsf b/part_2/ex9/ex9.qsf
index af789d5..dab96ce 100644
--- a/part_2/ex9/ex9.qsf
+++ b/part_2/ex9/ex9.qsf
@@ -252,7 +252,7 @@ set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY ex9
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00 NOVEMBER 25, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
diff --git a/part_2/ex9/ex9.qws b/part_2/ex9/ex9.qws
deleted file mode 100644
index 518237b..0000000
--- a/part_2/ex9/ex9.qws
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/ex9_assignment_defaults.qdf b/part_2/ex9/ex9_assignment_defaults.qdf
new file mode 100644
index 0000000..89a4543
--- /dev/null
+++ b/part_2/ex9/ex9_assignment_defaults.qdf
@@ -0,0 +1,795 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2016 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Intel and sold by Intel or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+# Date created = 20:28:46 December 11, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+# automatically by the Quartus Prime software and is used
+# to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL -value OFF
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
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+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
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+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info b/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info
index f84b742..4aad5b9 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Version_Index = 402707200
-Creation_Time = Fri Nov 25 10:41:49 2016
+Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Version_Index = 419480576
+Creation_Time = Sun Dec 11 20:28:46 2016
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
index 5548723..03f9cd0 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
index c0fbf3e..fcfae5a 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
index 926b6ab..2950f00 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
index e9d3716..431891a 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
index d0adce8..f51c2b8 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
index d45424f..626799f 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
index 614de49..370a8f5 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
index 7f6ab88..3fbb214 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.dpi b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
index ff7d621..e1634ea 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
index e4db04f..0224820 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
index 963b5cc..4615adb 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
index a65cde8..bc4d8d2 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.kpt b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
index 7826f1d..2944142 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb
deleted file mode 100644
index 26d62d0..0000000
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
deleted file mode 100644
index 1b63352..0000000
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
deleted file mode 100644
index bf98b99..0000000
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.opi b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.opi
deleted file mode 100644
index 56a6051..0000000
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.opi
+++ /dev/null
@@ -1 +0,0 @@
-1 \ No newline at end of file
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb
deleted file mode 100644
index 26d62d0..0000000
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
deleted file mode 100644
index ecc33d2..0000000
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
deleted file mode 100644
index 5b44096..0000000
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
deleted file mode 100644
index 7f6ab88..0000000
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb
deleted file mode 100644
index e4db04f..0000000
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
deleted file mode 100644
index 963b5cc..0000000
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
deleted file mode 100644
index a65cde8..0000000
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
+++ /dev/null
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.rrp.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.rrp.hdb
index e0bf383..00b36c3 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.rrp.hdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.rrp.hdb
Binary files differ
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.rrs.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.rrs.cdb
index f715ca1..1d9c08e 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.rrs.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.rrs.cdb
Binary files differ
diff --git a/part_2/ex9/output_files/ex9.asm.rpt b/part_2/ex9/output_files/ex9.asm.rpt
index abf1d89..1851753 100644
--- a/part_2/ex9/output_files/ex9.asm.rpt
+++ b/part_2/ex9/output_files/ex9.asm.rpt
@@ -1,92 +1,92 @@
-Assembler report for ex9
-Wed Dec 07 12:08:20 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Wed Dec 07 12:08:20 2016 ;
-; Revision Name ; ex9 ;
-; Top-level Entity Name ; ex9 ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+----------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+----------------------------------------------------------------------------+
-; File Name ;
-+----------------------------------------------------------------------------+
-; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
-+----------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------+
-; Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
-+----------------+-------------------------------------------------------------------------------------+
-; Option ; Setting ;
-+----------------+-------------------------------------------------------------------------------------+
-; Device ; 5CSEMA5F31C6 ;
-; JTAG usercode ; 0x00B4D80C ;
-; Checksum ; 0x00B4D80C ;
-+----------------+-------------------------------------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
- Info: Processing started: Wed Dec 07 12:08:12 2016
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 896 megabytes
- Info: Processing ended: Wed Dec 07 12:08:20 2016
- Info: Elapsed time: 00:00:08
- Info: Total CPU time (on all processors): 00:00:06
-
-
+Assembler report for ex9
+Sun Dec 11 20:30:59 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: ex9.sof
+ 6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Sun Dec 11 20:30:59 2016 ;
+; Revision Name ; ex9 ;
+; Top-level Entity Name ; ex9 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++---------------------------+
+; Assembler Generated Files ;
++---------------------------+
+; File Name ;
++---------------------------+
+; ex9.sof ;
++---------------------------+
+
+
++-----------------------------------+
+; Assembler Device Options: ex9.sof ;
++----------------+------------------+
+; Option ; Setting ;
++----------------+------------------+
+; Device ; 5CSEMA5F31C6 ;
+; JTAG usercode ; 0x00B4AD1F ;
+; Checksum ; 0x00B4AD1F ;
++----------------+------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+ Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+ Info: Processing started: Sun Dec 11 20:30:53 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 979 megabytes
+ Info: Processing ended: Sun Dec 11 20:30:59 2016
+ Info: Elapsed time: 00:00:06
+ Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_2/ex9/output_files/ex9.done b/part_2/ex9/output_files/ex9.done
index 2aa652f..3f30efe 100644
--- a/part_2/ex9/output_files/ex9.done
+++ b/part_2/ex9/output_files/ex9.done
@@ -1 +1 @@
-Wed Dec 07 12:08:31 2016
+Sun Dec 11 20:31:05 2016
diff --git a/part_2/ex9/output_files/ex9.fit.rpt b/part_2/ex9/output_files/ex9.fit.rpt
index 90d3227..bc51ba0 100644
--- a/part_2/ex9/output_files/ex9.fit.rpt
+++ b/part_2/ex9/output_files/ex9.fit.rpt
@@ -1,2129 +1,2129 @@
-Fitter report for ex9
-Wed Dec 07 12:08:07 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. I/O Assignment Warnings
- 6. Fitter Netlist Optimizations
- 7. Ignored Assignments
- 8. Incremental Compilation Preservation Summary
- 9. Incremental Compilation Partition Settings
- 10. Incremental Compilation Placement Preservation
- 11. Pin-Out File
- 12. Fitter Resource Usage Summary
- 13. Fitter Partition Statistics
- 14. Input Pins
- 15. Output Pins
- 16. I/O Bank Usage
- 17. All Package Pins
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Global & Other Fast Signals
- 23. Routing Usage Summary
- 24. I/O Rules Summary
- 25. I/O Rules Details
- 26. I/O Rules Matrix
- 27. Fitter Device Options
- 28. Operating Settings and Conditions
- 29. Estimated Delay Added for Hold Timing Summary
- 30. Estimated Delay Added for Hold Timing Details
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+---------------------------------+-------------------------------------------------+
-; Fitter Status ; Successful - Wed Dec 07 12:08:07 2016 ;
-; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name ; ex9 ;
-; Top-level Entity Name ; ex9 ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Logic utilization (in ALMs) ; 159 / 32,070 ( < 1 % ) ;
-; Total registers ; 95 ;
-; Total pins ; 57 / 457 ( 12 % ) ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
-; Total RAM Blocks ; 0 / 397 ( 0 % ) ;
-; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 / 6 ( 0 % ) ;
-; Total DLLs ; 0 / 4 ( 0 % ) ;
-+---------------------------------+-------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; 5CSEMA5F31C6 ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Auto RAM to MLAB Conversion ; On ; On ;
-; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
-; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
-; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Clamping Diode ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-; Advanced Physical Optimization ; On ; On ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.02 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.8% ;
-; Processor 3 ; 0.8% ;
-; Processor 4 ; 0.8% ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings ;
-+----------+--------------------------------------+
-; Pin Name ; Reason ;
-+----------+--------------------------------------+
-; HEX0[0] ; Missing drive strength and slew rate ;
-; HEX0[1] ; Missing drive strength and slew rate ;
-; HEX0[2] ; Missing drive strength and slew rate ;
-; HEX0[3] ; Missing drive strength and slew rate ;
-; HEX0[4] ; Missing drive strength and slew rate ;
-; HEX0[5] ; Missing drive strength and slew rate ;
-; HEX0[6] ; Missing drive strength and slew rate ;
-; HEX1[0] ; Missing drive strength and slew rate ;
-; HEX1[1] ; Missing drive strength and slew rate ;
-; HEX1[2] ; Missing drive strength and slew rate ;
-; HEX1[3] ; Missing drive strength and slew rate ;
-; HEX1[4] ; Missing drive strength and slew rate ;
-; HEX1[5] ; Missing drive strength and slew rate ;
-; HEX1[6] ; Missing drive strength and slew rate ;
-; HEX2[0] ; Missing drive strength and slew rate ;
-; HEX2[1] ; Missing drive strength and slew rate ;
-; HEX2[2] ; Missing drive strength and slew rate ;
-; HEX2[3] ; Missing drive strength and slew rate ;
-; HEX2[4] ; Missing drive strength and slew rate ;
-; HEX2[5] ; Missing drive strength and slew rate ;
-; HEX2[6] ; Missing drive strength and slew rate ;
-; HEX3[0] ; Missing drive strength and slew rate ;
-; HEX3[1] ; Missing drive strength and slew rate ;
-; HEX3[2] ; Missing drive strength and slew rate ;
-; HEX3[3] ; Missing drive strength and slew rate ;
-; HEX3[4] ; Missing drive strength and slew rate ;
-; HEX3[5] ; Missing drive strength and slew rate ;
-; HEX3[6] ; Missing drive strength and slew rate ;
-; HEX4[0] ; Missing drive strength and slew rate ;
-; HEX4[1] ; Missing drive strength and slew rate ;
-; HEX4[2] ; Missing drive strength and slew rate ;
-; HEX4[3] ; Missing drive strength and slew rate ;
-; HEX4[4] ; Missing drive strength and slew rate ;
-; HEX4[5] ; Missing drive strength and slew rate ;
-; HEX4[6] ; Missing drive strength and slew rate ;
-; HEX5[0] ; Missing drive strength and slew rate ;
-; HEX5[1] ; Missing drive strength and slew rate ;
-; HEX5[2] ; Missing drive strength and slew rate ;
-; HEX5[3] ; Missing drive strength and slew rate ;
-; HEX5[4] ; Missing drive strength and slew rate ;
-; HEX5[5] ; Missing drive strength and slew rate ;
-; HEX5[6] ; Missing drive strength and slew rate ;
-; LEDR[0] ; Missing drive strength and slew rate ;
-; LEDR[1] ; Missing drive strength and slew rate ;
-; LEDR[2] ; Missing drive strength and slew rate ;
-; LEDR[3] ; Missing drive strength and slew rate ;
-; LEDR[4] ; Missing drive strength and slew rate ;
-; LEDR[5] ; Missing drive strength and slew rate ;
-; LEDR[6] ; Missing drive strength and slew rate ;
-; LEDR[7] ; Missing drive strength and slew rate ;
-; LEDR[8] ; Missing drive strength and slew rate ;
-; LEDR[9] ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Netlist Optimizations ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
-; formula_fsm:FSM|count[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; formula_fsm:FSM|count[6]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[0]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[1]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[2]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[5]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[8]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[10]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[11]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[12]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[14]~DUPLICATE ; ; ;
-; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[15]~DUPLICATE ; ; ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Location ; ; ; ADC_CS ; PIN_AG20 ; QSF Assignment ;
-; Location ; ; ; ADC_SCK ; PIN_AF21 ; QSF Assignment ;
-; Location ; ; ; ADC_SDI ; PIN_AG21 ; QSF Assignment ;
-; Location ; ; ; ADC_SDO ; PIN_AJ21 ; QSF Assignment ;
-; Location ; ; ; DAC_CS ; PIN_AD20 ; QSF Assignment ;
-; Location ; ; ; DAC_LD ; PIN_AK21 ; QSF Assignment ;
-; Location ; ; ; DAC_SCK ; PIN_AF20 ; QSF Assignment ;
-; Location ; ; ; DAC_SDI ; PIN_AG18 ; QSF Assignment ;
-; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ;
-; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ;
-; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ;
-; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ;
-; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ;
-; Location ; ; ; PWM_OUT ; PIN_AJ20 ; QSF Assignment ;
-; Location ; ; ; SW[0] ; PIN_AB12 ; QSF Assignment ;
-; Location ; ; ; SW[1] ; PIN_AC12 ; QSF Assignment ;
-; Location ; ; ; SW[2] ; PIN_AF9 ; QSF Assignment ;
-; Location ; ; ; SW[3] ; PIN_AF10 ; QSF Assignment ;
-; Location ; ; ; SW[4] ; PIN_AD11 ; QSF Assignment ;
-; Location ; ; ; SW[5] ; PIN_AD12 ; QSF Assignment ;
-; Location ; ; ; SW[6] ; PIN_AE11 ; QSF Assignment ;
-; Location ; ; ; SW[7] ; PIN_AC9 ; QSF Assignment ;
-; Location ; ; ; SW[8] ; PIN_AD10 ; QSF Assignment ;
-; Location ; ; ; SW[9] ; PIN_AE12 ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; ADC_CS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; ADC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; ADC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; ADC_SDO ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; DAC_CS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; DAC_LD ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; DAC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; DAC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; PWM_OUT ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; SW[0] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; SW[1] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; SW[2] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; SW[3] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; SW[4] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; SW[5] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; SW[6] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; SW[7] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; SW[8] ; 3.3-V LVTTL ; QSF Assignment ;
-; I/O Standard ; ex9 ; ; SW[9] ; 3.3-V LVTTL ; QSF Assignment ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 ) ;
-; -- Achieved ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 489 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.pin.
-
-
-+------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+-------------------------------------------------------------+--------------------+-------+
-; Resource ; Usage ; % ;
-+-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 159 / 32,070 ; < 1 % ;
-; ALMs needed [=A-B+C] ; 159 ; ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 162 / 32,070 ; < 1 % ;
-; [a] ALMs used for LUT logic and registers ; 36 ; ;
-; [b] ALMs used for LUT logic ; 120 ; ;
-; [c] ALMs used for registers ; 6 ; ;
-; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
-; [B] Estimate of ALMs recoverable by dense packing ; 3 / 32,070 ; < 1 % ;
-; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ;
-; [a] Due to location constrained logic ; 0 ; ;
-; [b] Due to LAB-wide signal conflicts ; 0 ; ;
-; [c] Due to LAB input limits ; 0 ; ;
-; [d] Due to virtual I/Os ; 0 ; ;
-; ; ; ;
-; Difficulty packing design ; Low ; ;
-; ; ; ;
-; Total LABs: partially or completely used ; 19 / 3,207 ; < 1 % ;
-; -- Logic LABs ; 19 ; ;
-; -- Memory LABs (up to half of total LABs) ; 0 ; ;
-; ; ; ;
-; Combinational ALUT usage for logic ; 290 ; ;
-; -- 7 input functions ; 0 ; ;
-; -- 6 input functions ; 41 ; ;
-; -- 5 input functions ; 5 ; ;
-; -- 4 input functions ; 157 ; ;
-; -- <=3 input functions ; 87 ; ;
-; Combinational ALUT usage for route-throughs ; 1 ; ;
-; Dedicated logic registers ; 95 ; ;
-; -- By type: ; ; ;
-; -- Primary logic registers ; 84 / 64,140 ; < 1 % ;
-; -- Secondary logic registers ; 11 / 64,140 ; < 1 % ;
-; -- By function: ; ; ;
-; -- Design implementation registers ; 84 ; ;
-; -- Routing optimization registers ; 11 ; ;
-; ; ; ;
-; Virtual pins ; 0 ; ;
-; I/O pins ; 57 / 457 ; 12 % ;
-; -- Clock pins ; 4 / 8 ; 50 % ;
-; -- Dedicated input pins ; 0 / 21 ; 0 % ;
-; ; ; ;
-; Hard processor system peripheral utilization ; ; ;
-; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
-; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
-; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
-; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
-; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
-; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
-; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
-; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
-; -- JTAG ; 0 / 1 ( 0 % ) ; ;
-; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
-; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
-; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
-; -- STM event ; 0 / 1 ( 0 % ) ; ;
-; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
-; -- DMA ; 0 / 1 ( 0 % ) ; ;
-; -- CAN ; 0 / 2 ( 0 % ) ; ;
-; -- EMAC ; 0 / 2 ( 0 % ) ; ;
-; -- I2C ; 0 / 4 ( 0 % ) ; ;
-; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
-; -- QSPI ; 0 / 1 ( 0 % ) ; ;
-; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
-; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
-; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
-; -- UART ; 0 / 2 ( 0 % ) ; ;
-; -- USB ; 0 / 2 ( 0 % ) ; ;
-; ; ; ;
-; Global signals ; 1 ; ;
-; M10K blocks ; 0 / 397 ; 0 % ;
-; Total MLAB memory bits ; 0 ; ;
-; Total block memory bits ; 0 / 4,065,280 ; 0 % ;
-; Total block memory implementation bits ; 0 / 4,065,280 ; 0 % ;
-; ; ; ;
-; Total DSP Blocks ; 0 / 87 ; 0 % ;
-; ; ; ;
-; Fractional PLLs ; 0 / 6 ; 0 % ;
-; Global clocks ; 1 / 16 ; 6 % ;
-; Quadrant clocks ; 0 / 66 ; 0 % ;
-; Horizontal periphery clocks ; 0 / 18 ; 0 % ;
-; SERDES Transmitters ; 0 / 100 ; 0 % ;
-; SERDES Receivers ; 0 / 100 ; 0 % ;
-; JTAGs ; 0 / 1 ; 0 % ;
-; ASMI blocks ; 0 / 1 ; 0 % ;
-; CRC blocks ; 0 / 1 ; 0 % ;
-; Remote update blocks ; 0 / 1 ; 0 % ;
-; Oscillator blocks ; 0 / 1 ; 0 % ;
-; Impedance control blocks ; 0 / 4 ; 0 % ;
-; Hard Memory Controllers ; 0 / 2 ; 0 % ;
-; Average interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; ;
-; Peak interconnect usage (total/H/V) ; 2.7% / 3.0% / 1.9% ; ;
-; Maximum fan-out ; 68 ; ;
-; Highest non-global fan-out ; 68 ; ;
-; Total fan-out ; 1448 ; ;
-; Average fan-out ; 2.89 ; ;
-+-------------------------------------------------------------+--------------------+-------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 159 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; ALMs needed [=A-B+C] ; 159 ; 0 ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 162 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; [a] ALMs used for LUT logic and registers ; 36 ; 0 ;
-; [b] ALMs used for LUT logic ; 120 ; 0 ;
-; [c] ALMs used for registers ; 6 ; 0 ;
-; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
-; [B] Estimate of ALMs recoverable by dense packing ; 3 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
-; [a] Due to location constrained logic ; 0 ; 0 ;
-; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
-; [c] Due to LAB input limits ; 0 ; 0 ;
-; [d] Due to virtual I/Os ; 0 ; 0 ;
-; ; ; ;
-; Difficulty packing design ; Low ; Low ;
-; ; ; ;
-; Total LABs: partially or completely used ; 19 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ;
-; -- Logic LABs ; 19 ; 0 ;
-; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
-; ; ; ;
-; Combinational ALUT usage for logic ; 290 ; 0 ;
-; -- 7 input functions ; 0 ; 0 ;
-; -- 6 input functions ; 41 ; 0 ;
-; -- 5 input functions ; 5 ; 0 ;
-; -- 4 input functions ; 157 ; 0 ;
-; -- <=3 input functions ; 87 ; 0 ;
-; Combinational ALUT usage for route-throughs ; 1 ; 0 ;
-; Memory ALUT usage ; 0 ; 0 ;
-; -- 64-address deep ; 0 ; 0 ;
-; -- 32-address deep ; 0 ; 0 ;
-; ; ; ;
-; Dedicated logic registers ; 0 ; 0 ;
-; -- By type: ; ; ;
-; -- Primary logic registers ; 84 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
-; -- Secondary logic registers ; 11 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
-; -- By function: ; ; ;
-; -- Design implementation registers ; 84 ; 0 ;
-; -- Routing optimization registers ; 11 ; 0 ;
-; ; ; ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 57 ; 0 ;
-; I/O registers ; 0 ; 0 ;
-; Total block memory bits ; 0 ; 0 ;
-; Total block memory implementation bits ; 0 ; 0 ;
-; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 1448 ; 0 ;
-; -- Registered Connections ; 438 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 5 ; 0 ;
-; -- Output Ports ; 52 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; AF14 ; 3B ; 32 ; 0 ; 0 ; 27 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-; KEY[0] ; AA14 ; 3B ; 36 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-; KEY[1] ; AA15 ; 3B ; 36 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-; KEY[2] ; W15 ; 3B ; 40 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-; KEY[3] ; Y16 ; 3B ; 40 ; 0 ; 17 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[0] ; AJ29 ; 5A ; 89 ; 6 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[1] ; AH29 ; 5A ; 89 ; 6 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[2] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[3] ; AG30 ; 5A ; 89 ; 16 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[4] ; AF29 ; 5A ; 89 ; 15 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[5] ; AF30 ; 5A ; 89 ; 15 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX1[6] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[0] ; AB23 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[1] ; AE29 ; 5B ; 89 ; 23 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[2] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[3] ; AC28 ; 5B ; 89 ; 20 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[4] ; AD30 ; 5B ; 89 ; 25 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[5] ; AC29 ; 5B ; 89 ; 20 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX2[6] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[0] ; AD26 ; 5A ; 89 ; 16 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[1] ; AC27 ; 5A ; 89 ; 16 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[2] ; AD25 ; 5A ; 89 ; 4 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[3] ; AC25 ; 5A ; 89 ; 4 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[4] ; AB28 ; 5B ; 89 ; 21 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[5] ; AB25 ; 5A ; 89 ; 11 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX3[6] ; AB22 ; 5A ; 89 ; 9 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[0] ; AA24 ; 5A ; 89 ; 11 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[1] ; Y23 ; 5A ; 89 ; 13 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[2] ; Y24 ; 5A ; 89 ; 13 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[3] ; W22 ; 5A ; 89 ; 8 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[4] ; W24 ; 5A ; 89 ; 15 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[5] ; V23 ; 5A ; 89 ; 15 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX4[6] ; W25 ; 5B ; 89 ; 20 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX5[0] ; V25 ; 5B ; 89 ; 20 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX5[1] ; AA28 ; 5B ; 89 ; 21 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX5[2] ; Y27 ; 5B ; 89 ; 25 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX5[3] ; AB27 ; 5B ; 89 ; 23 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX5[4] ; AB26 ; 5A ; 89 ; 9 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX5[5] ; AA26 ; 5B ; 89 ; 23 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; HEX5[6] ; AA25 ; 5A ; 89 ; 9 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[0] ; V16 ; 4A ; 52 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[1] ; W16 ; 4A ; 52 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[2] ; V17 ; 4A ; 60 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[3] ; V18 ; 4A ; 80 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[4] ; W17 ; 4A ; 60 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[5] ; W19 ; 4A ; 80 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[6] ; Y19 ; 4A ; 84 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[7] ; W20 ; 5A ; 89 ; 6 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[8] ; W21 ; 5A ; 89 ; 8 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-; LEDR[9] ; Y21 ; 5A ; 89 ; 6 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-----------------------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+-------------------+---------------+--------------+---------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
-+----------+-------------------+---------------+--------------+---------------+
-; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
-; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
-; 3A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 3B ; 5 / 48 ( 10 % ) ; 3.3V ; -- ; 3.3V ;
-; 4A ; 7 / 80 ( 9 % ) ; 3.3V ; -- ; 3.3V ;
-; 5A ; 32 / 32 ( 100 % ) ; 3.3V ; -- ; 3.3V ;
-; 5B ; 13 / 16 ( 81 % ) ; 3.3V ; -- ; 3.3V ;
-; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-+----------+-------------------+---------------+--------------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
-; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
-; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA14 ; 122 ; 3B ; KEY[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AA15 ; 120 ; 3B ; KEY[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; AA24 ; 228 ; 5A ; HEX4[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AA25 ; 224 ; 5A ; HEX5[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AA26 ; 252 ; 5B ; HEX5[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AA27 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AA28 ; 251 ; 5B ; HEX5[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB12 ; 72 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB14 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 225 ; 5A ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AB23 ; 227 ; 5A ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AB25 ; 230 ; 5A ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AB26 ; 226 ; 5A ; HEX5[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AB27 ; 254 ; 5B ; HEX5[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AB28 ; 249 ; 5B ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC11 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC12 ; 82 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC21 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AC25 ; 215 ; 5A ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC27 ; 242 ; 5A ; HEX3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AC28 ; 245 ; 5B ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AC29 ; 247 ; 5B ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AC30 ; 259 ; 5B ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD10 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 80 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD18 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 213 ; 5A ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD26 ; 240 ; 5A ; HEX3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD27 ; 222 ; 5A ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AD29 ; 255 ; 5B ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AD30 ; 257 ; 5B ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE11 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE29 ; 253 ; 5B ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AE30 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 67 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 57 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 114 ; 3B ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AF29 ; 237 ; 5A ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AF30 ; 239 ; 5A ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AG30 ; 243 ; 5A ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH16 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH26 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AH29 ; 218 ; 5A ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AH30 ; 241 ; 5A ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ29 ; 216 ; 5A ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK10 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK20 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
-; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
-; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
-; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
-; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
-; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
-; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
-; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
-; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
-; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
-; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
-; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
-; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U23 ; ; 5B ; VCCPD5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V16 ; 138 ; 4A ; LEDR[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; V17 ; 154 ; 4A ; LEDR[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; V18 ; 194 ; 4A ; LEDR[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; V23 ; 236 ; 5A ; HEX4[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; V25 ; 246 ; 5B ; HEX5[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W15 ; 130 ; 3B ; KEY[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; W16 ; 136 ; 4A ; LEDR[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; W17 ; 152 ; 4A ; LEDR[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W19 ; 192 ; 4A ; LEDR[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; W20 ; 217 ; 5A ; LEDR[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; W21 ; 221 ; 5A ; LEDR[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; W22 ; 223 ; 5A ; HEX4[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; W24 ; 238 ; 5A ; HEX4[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; W25 ; 244 ; 5B ; HEX4[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y16 ; 128 ; 3B ; KEY[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y19 ; 202 ; 4A ; LEDR[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y21 ; 219 ; 5A ; LEDR[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y23 ; 232 ; 5A ; HEX4[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; Y24 ; 234 ; 5A ; HEX4[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 258 ; 5B ; HEX5[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex9 ; 158.5 (0.5) ; 161.5 (0.5) ; 3.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 290 (1) ; 95 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 57 ; 0 ; |ex9 ; ex9 ; work ;
-; |LFSR:LFSR0| ; 3.0 (3.0) ; 3.3 (3.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|LFSR:LFSR0 ; LFSR ; work ;
-; |bin2bcd_16:BCD| ; 67.7 (0.0) ; 68.0 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 124 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD ; bin2bcd_16 ; work ;
-; |add3_ge5:A1| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A1 ; add3_ge5 ; work ;
-; |add3_ge5:A10| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5 ; work ;
-; |add3_ge5:A11| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5 ; work ;
-; |add3_ge5:A12| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5 ; work ;
-; |add3_ge5:A13| ; 4.0 (4.0) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5 ; work ;
-; |add3_ge5:A14| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5 ; work ;
-; |add3_ge5:A15| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5 ; work ;
-; |add3_ge5:A16| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5 ; work ;
-; |add3_ge5:A17| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5 ; work ;
-; |add3_ge5:A18| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5 ; work ;
-; |add3_ge5:A19| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5 ; work ;
-; |add3_ge5:A2| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A2 ; add3_ge5 ; work ;
-; |add3_ge5:A20| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5 ; work ;
-; |add3_ge5:A21| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5 ; work ;
-; |add3_ge5:A22| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5 ; work ;
-; |add3_ge5:A23| ; 4.0 (4.0) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5 ; work ;
-; |add3_ge5:A24| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5 ; work ;
-; |add3_ge5:A25| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5 ; work ;
-; |add3_ge5:A26| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5 ; work ;
-; |add3_ge5:A27| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5 ; work ;
-; |add3_ge5:A28| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5 ; work ;
-; |add3_ge5:A29| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5 ; work ;
-; |add3_ge5:A3| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A3 ; add3_ge5 ; work ;
-; |add3_ge5:A30| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5 ; work ;
-; |add3_ge5:A32| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5 ; work ;
-; |add3_ge5:A33| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5 ; work ;
-; |add3_ge5:A34| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5 ; work ;
-; |add3_ge5:A35| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5 ; work ;
-; |add3_ge5:A4| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A4 ; add3_ge5 ; work ;
-; |add3_ge5:A5| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A5 ; add3_ge5 ; work ;
-; |add3_ge5:A6| ; 3.7 (3.7) ; 4.0 (4.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A6 ; add3_ge5 ; work ;
-; |add3_ge5:A7| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A7 ; add3_ge5 ; work ;
-; |add3_ge5:A8| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A8 ; add3_ge5 ; work ;
-; |add3_ge5:A9| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A9 ; add3_ge5 ; work ;
-; |counter_16:COUNT0| ; 8.5 (8.5) ; 8.6 (8.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|counter_16:COUNT0 ; counter_16 ; work ;
-; |delay:DEL0| ; 14.3 (14.3) ; 15.4 (15.4) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|delay:DEL0 ; delay ; work ;
-; |formula_fsm:FSM| ; 24.5 (24.5) ; 25.3 (25.3) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 43 (43) ; 26 (26) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|formula_fsm:FSM ; formula_fsm ; work ;
-; |hex_to_7seg:SEG0| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG1| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG2| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG3| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG3 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG4| ; 7.5 (7.5) ; 7.5 (7.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG4 ; hex_to_7seg ; work ;
-; |tick_50000:TICK0| ; 18.5 (18.5) ; 18.9 (18.9) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (36) ; 27 (27) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|tick_50000:TICK0 ; tick_50000 ; work ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; KEY[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; KEY[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX4[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX5[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX5[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX5[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX5[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX5[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX5[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX5[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; KEY[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; CLOCK_50 ; Input ; -- ; (0) ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; KEY[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+-------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+-------------------------------------------------+-------------------+---------+
-; KEY[1] ; ; ;
-; KEY[2] ; ; ;
-; KEY[0] ; ; ;
-; - counter_16:COUNT0|count~0 ; 1 ; 0 ;
-; CLOCK_50 ; ; ;
-; - tick_50000:TICK0|CLK_OUT ; 1 ; 0 ;
-; KEY[3] ; ; ;
-; - formula_fsm:FSM|Selector3~0 ; 1 ; 0 ;
-; - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~0 ; 1 ; 0 ;
-; - formula_fsm:FSM|Selector2~0 ; 1 ; 0 ;
-+-------------------------------------------------+-------------------+---------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 2 ; Clock ; no ; -- ; -- ; -- ;
-; CLOCK_50 ; PIN_AF14 ; 26 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ;
-; counter_16:COUNT0|count~0 ; LABCELL_X60_Y4_N30 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
-; counter_16:COUNT0|state ; FF_X59_Y4_N14 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ;
-; delay:DEL0|count[5]~0 ; LABCELL_X62_Y4_N51 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
-; delay:DEL0|state.COUNTING ; FF_X63_Y4_N56 ; 19 ; Sync. load ; no ; -- ; -- ; -- ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X62_Y4_N56 ; 26 ; Clock enable, Latch enable ; no ; -- ; -- ; -- ;
-; formula_fsm:FSM|state.WAIT_TRIGGER ; FF_X61_Y4_N2 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
-; tick_50000:TICK0|CLK_OUT ; FF_X60_Y4_N2 ; 68 ; Clock ; no ; -- ; -- ; -- ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 26 ; Global Clock ; GCLK6 ; -- ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------+
-; Routing Usage Summary ;
-+---------------------------------------------+-------------------------+
-; Routing Resource Type ; Usage ;
-+---------------------------------------------+-------------------------+
-; Block interconnects ; 375 / 289,320 ( < 1 % ) ;
-; C12 interconnects ; 2 / 13,420 ( < 1 % ) ;
-; C2 interconnects ; 132 / 119,108 ( < 1 % ) ;
-; C4 interconnects ; 84 / 56,300 ( < 1 % ) ;
-; DQS bus muxes ; 0 / 25 ( 0 % ) ;
-; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
-; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
-; Direct links ; 62 / 289,320 ( < 1 % ) ;
-; Global clocks ; 1 / 16 ( 6 % ) ;
-; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
-; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
-; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
-; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
-; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ;
-; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
-; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
-; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
-; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
-; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
-; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ;
-; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
-; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
-; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
-; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
-; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
-; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
-; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
-; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
-; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
-; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
-; Local interconnects ; 147 / 84,580 ( < 1 % ) ;
-; Quadrant clocks ; 0 / 66 ( 0 % ) ;
-; R14 interconnects ; 25 / 12,676 ( < 1 % ) ;
-; R14/C12 interconnect drivers ; 26 / 20,720 ( < 1 % ) ;
-; R3 interconnects ; 160 / 130,992 ( < 1 % ) ;
-; R6 interconnects ; 252 / 266,960 ( < 1 % ) ;
-; Spine clocks ; 1 / 360 ( < 1 % ) ;
-; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
-+---------------------------------------------+-------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 28 ;
-; Number of I/O Rules Passed ; 6 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 22 ;
-+----------------------------------+-------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-; Total Pass ; 57 ; 0 ; 57 ; 0 ; 0 ; 57 ; 57 ; 0 ; 57 ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 0 ; 57 ; 0 ; 57 ; 57 ; 0 ; 0 ; 57 ; 0 ; 0 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; KEY[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+-----------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+-----------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Passive Serial ;
-; Enable Error Detection CRC_ERROR pin ; Off ;
-; Enable CvP_CONFDONE pin ; Off ;
-; Enable open drain on CRC_ERROR pin ; On ;
-; Enable open drain on CvP_CONFDONE pin ; On ;
-; Enable open drain on INIT_DONE pin ; On ;
-; Enable open drain on Partial Reconfiguration pins ; Off ;
-; Enable open drain on nCEO pin ; On ;
-; Enable Partial Reconfiguration pins ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Enable internal scrubbing ; Off ;
-; Active Serial clock source ; 100 MHz Internal Oscillator ;
-; Device initialization clock source ; Internal Oscillator ;
-; Configuration via Protocol ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; Enable nCEO output ; Off ;
-; Data[15..8] ; Unreserved ;
-; Data[7..5] ; Unreserved ;
-; Base pin-out file on sameframe device ; Off ;
-+------------------------------------------------------------------+-----------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.10 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-------------------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 62.3 ;
-; CLOCK_50 ; CLOCK_50 ; 9.8 ;
-; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.7 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.2 ;
-; tick_50000:TICK0|CLK_OUT,I/O ; tick_50000:TICK0|CLK_OUT ; 1.6 ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
-
-
-+--------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details ;
-+----------------------------------------+-------------------------------------+-------------------+
-; Source Register ; Destination Register ; Delay Added in ns ;
-+----------------------------------------+-------------------------------------+-------------------+
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|ledr[3] ; 2.057 ;
-; formula_fsm:FSM|start_delay ; delay:DEL0|state.IDLE ; 1.568 ;
-; tick_50000:TICK0|count[5] ; tick_50000:TICK0|CLK_OUT ; 1.369 ;
-; tick_50000:TICK0|count[11] ; tick_50000:TICK0|CLK_OUT ; 1.341 ;
-; tick_50000:TICK0|count[14] ; tick_50000:TICK0|CLK_OUT ; 1.313 ;
-; tick_50000:TICK0|count[15] ; tick_50000:TICK0|CLK_OUT ; 1.313 ;
-; tick_50000:TICK0|count[6] ; tick_50000:TICK0|CLK_OUT ; 1.267 ;
-; tick_50000:TICK0|count[12] ; tick_50000:TICK0|CLK_OUT ; 1.232 ;
-; tick_50000:TICK0|count[3] ; tick_50000:TICK0|CLK_OUT ; 1.227 ;
-; tick_50000:TICK0|count[8] ; tick_50000:TICK0|CLK_OUT ; 1.224 ;
-; tick_50000:TICK0|count[13] ; tick_50000:TICK0|CLK_OUT ; 1.214 ;
-; tick_50000:TICK0|count[9] ; tick_50000:TICK0|CLK_OUT ; 1.207 ;
-; tick_50000:TICK0|count[4] ; tick_50000:TICK0|CLK_OUT ; 1.206 ;
-; tick_50000:TICK0|count[7] ; tick_50000:TICK0|CLK_OUT ; 1.192 ;
-; tick_50000:TICK0|count[0] ; tick_50000:TICK0|CLK_OUT ; 1.189 ;
-; tick_50000:TICK0|count[1] ; tick_50000:TICK0|CLK_OUT ; 1.170 ;
-; tick_50000:TICK0|count[2] ; tick_50000:TICK0|CLK_OUT ; 1.169 ;
-; tick_50000:TICK0|count[10] ; tick_50000:TICK0|CLK_OUT ; 1.155 ;
-; delay:DEL0|count[13] ; delay:DEL0|count[11] ; 0.995 ;
-; formula_fsm:FSM|count[1] ; formula_fsm:FSM|count[1] ; 0.879 ;
-; formula_fsm:FSM|count[6] ; formula_fsm:FSM|count[5] ; 0.876 ;
-; formula_fsm:FSM|count[9] ; formula_fsm:FSM|count[5] ; 0.866 ;
-; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[3] ; 0.865 ;
-; delay:DEL0|state.IDLE ; delay:DEL0|state.COUNTING ; 0.863 ;
-; formula_fsm:FSM|count[0] ; formula_fsm:FSM|count[1] ; 0.855 ;
-; formula_fsm:FSM|count[7] ; formula_fsm:FSM|count[5] ; 0.852 ;
-; delay:DEL0|count[0] ; delay:DEL0|count[11] ; 0.851 ;
-; delay:DEL0|count[3] ; delay:DEL0|count[11] ; 0.848 ;
-; delay:DEL0|count[9] ; delay:DEL0|count[11] ; 0.836 ;
-; delay:DEL0|count[8] ; delay:DEL0|count[11] ; 0.833 ;
-; delay:DEL0|count[1] ; delay:DEL0|count[11] ; 0.830 ;
-; formula_fsm:FSM|ledr[0] ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; formula_fsm:FSM|ledr[1] ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; formula_fsm:FSM|ledr[2] ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; formula_fsm:FSM|ledr[3] ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; formula_fsm:FSM|ledr[4] ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; formula_fsm:FSM|ledr[5] ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; formula_fsm:FSM|ledr[6] ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; formula_fsm:FSM|ledr[7] ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; formula_fsm:FSM|ledr[8] ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; formula_fsm:FSM|ledr[9] ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; KEY[3] ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; formula_fsm:FSM|state.WAIT_TRIGGER ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; delay:DEL0|state.TIME_OUT ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826 ;
-; delay:DEL0|count[6] ; delay:DEL0|count[11] ; 0.820 ;
-; delay:DEL0|state.COUNTING ; delay:DEL0|state.IDLE ; 0.805 ;
-; formula_fsm:FSM|count[4] ; formula_fsm:FSM|count[1] ; 0.801 ;
-; delay:DEL0|count[7] ; delay:DEL0|count[11] ; 0.800 ;
-; delay:DEL0|state.WAIT_LOW ; delay:DEL0|state.IDLE ; 0.784 ;
-; delay:DEL0|count[4] ; delay:DEL0|count[11] ; 0.779 ;
-; formula_fsm:FSM|count[8] ; formula_fsm:FSM|count[10] ; 0.751 ;
-; delay:DEL0|count[10] ; delay:DEL0|count[11] ; 0.743 ;
-; formula_fsm:FSM|count[2] ; formula_fsm:FSM|count[1] ; 0.743 ;
-; formula_fsm:FSM|count[3] ; formula_fsm:FSM|count[1] ; 0.743 ;
-; formula_fsm:FSM|count[5] ; formula_fsm:FSM|count[1] ; 0.743 ;
-; formula_fsm:FSM|count[10] ; formula_fsm:FSM|count[5] ; 0.741 ;
-; formula_fsm:FSM|count[11] ; formula_fsm:FSM|count[5] ; 0.741 ;
-; delay:DEL0|count[11] ; delay:DEL0|count[11] ; 0.720 ;
-; delay:DEL0|count[12] ; delay:DEL0|count[11] ; 0.714 ;
-; delay:DEL0|count[5] ; delay:DEL0|count[11] ; 0.714 ;
-; LFSR:LFSR0|COUNT[1] ; LFSR:LFSR0|COUNT[1] ; 0.700 ;
-; LFSR:LFSR0|COUNT[7] ; LFSR:LFSR0|COUNT[1] ; 0.700 ;
-; delay:DEL0|count[2] ; delay:DEL0|count[11] ; 0.673 ;
-; LFSR:LFSR0|COUNT[5] ; LFSR:LFSR0|COUNT[6] ; 0.631 ;
-; LFSR:LFSR0|COUNT[3] ; LFSR:LFSR0|COUNT[4] ; 0.626 ;
-; LFSR:LFSR0|COUNT[4] ; LFSR:LFSR0|COUNT[5] ; 0.613 ;
-; LFSR:LFSR0|COUNT[6] ; LFSR:LFSR0|COUNT[7] ; 0.613 ;
-; LFSR:LFSR0|COUNT[2] ; delay:DEL0|count[8] ; 0.610 ;
-; counter_16:COUNT0|count[7] ; counter_16:COUNT0|count[15] ; 0.249 ;
-; counter_16:COUNT0|count[1] ; counter_16:COUNT0|count[15] ; 0.239 ;
-; counter_16:COUNT0|count[12] ; counter_16:COUNT0|count[15] ; 0.238 ;
-; counter_16:COUNT0|count[0] ; counter_16:COUNT0|count[15] ; 0.237 ;
-; counter_16:COUNT0|count[8] ; counter_16:COUNT0|count[15] ; 0.236 ;
-; counter_16:COUNT0|count[5] ; counter_16:COUNT0|count[15] ; 0.236 ;
-; counter_16:COUNT0|count[3] ; counter_16:COUNT0|count[15] ; 0.232 ;
-; counter_16:COUNT0|count[13] ; counter_16:COUNT0|count[15] ; 0.231 ;
-; counter_16:COUNT0|count[6] ; counter_16:COUNT0|count[15] ; 0.228 ;
-; counter_16:COUNT0|count[9] ; counter_16:COUNT0|count[15] ; 0.227 ;
-; counter_16:COUNT0|state ; counter_16:COUNT0|state ; 0.140 ;
-; KEY[0] ; counter_16:COUNT0|state ; 0.089 ;
-; counter_16:COUNT0|count[11] ; counter_16:COUNT0|count[15] ; 0.053 ;
-; counter_16:COUNT0|count[14] ; counter_16:COUNT0|count[15] ; 0.047 ;
-; counter_16:COUNT0|count[2] ; counter_16:COUNT0|count[15] ; 0.046 ;
-; counter_16:COUNT0|count[10] ; counter_16:COUNT0|count[15] ; 0.043 ;
-; counter_16:COUNT0|count[4] ; counter_16:COUNT0|count[15] ; 0.043 ;
-; tick_50000:TICK0|CLK_OUT ; counter_16:COUNT0|state ; 0.036 ;
-+----------------------------------------+-------------------------------------+-------------------+
-Note: This table only shows the top 86 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device 5CSEMA5F31C6 for design "ex9"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Info (184020): Starting Fitter periphery placement operations
-Info (11191): Automatically promoted 1 clock (1 global)
- Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
-Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
-Info (176233): Starting register packing
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
- Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
- Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
-Info (11798): Fitter preparation operations ending: elapsed time is 00:00:12
-Info (170189): Fitter placement preparation operations beginning
-Info (14951): The Fitter is using Advanced Physical Optimization.
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:02
-Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 30 warnings
- Info: Peak virtual memory: 2593 megabytes
- Info: Processing ended: Wed Dec 07 12:08:09 2016
- Info: Elapsed time: 00:00:37
- Info: Total CPU time (on all processors): 00:01:02
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg.
-
-
+Fitter report for ex9
+Sun Dec 11 20:30:51 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Fitter Netlist Optimizations
+ 6. Ignored Assignments
+ 7. Incremental Compilation Preservation Summary
+ 8. Incremental Compilation Partition Settings
+ 9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. I/O Assignment Warnings
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Routing Usage Summary
+ 24. I/O Rules Summary
+ 25. I/O Rules Details
+ 26. I/O Rules Matrix
+ 27. Fitter Device Options
+ 28. Operating Settings and Conditions
+ 29. Estimated Delay Added for Hold Timing Summary
+ 30. Estimated Delay Added for Hold Timing Details
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-------------------------------------------------------------------------------+
+; Fitter Summary ;
++---------------------------------+---------------------------------------------+
+; Fitter Status ; Successful - Sun Dec 11 20:30:51 2016 ;
+; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Revision Name ; ex9 ;
+; Top-level Entity Name ; ex9 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 154 / 32,070 ( < 1 % ) ;
+; Total registers ; 94 ;
+; Total pins ; 57 / 457 ( 12 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total RAM Blocks ; 0 / 397 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
+; Optimize Hold Timing ; All Paths ; All Paths ;
+; Optimize Multi-Corner Timing ; On ; On ;
+; Auto RAM to MLAB Conversion ; On ; On ;
+; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
+; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
+; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
+; SSN Optimization ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
+; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification ; Auto ; Auto ;
+; Enable Beneficial Skew Optimization ; On ; On ;
+; Optimize Design for Metastability ; On ; On ;
+; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+; Clamping Diode ; Off ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
+; Advanced Physical Optimization ; On ; On ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.03 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.9% ;
+; Processor 3 ; 0.9% ;
+; Processor 4 ; 0.9% ;
++----------------------------+-------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
+; formula_fsm:FSM|count[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; formula_fsm:FSM|count[1]~DUPLICATE ; ; ;
+; formula_fsm:FSM|count[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; formula_fsm:FSM|count[4]~DUPLICATE ; ; ;
+; formula_fsm:FSM|count[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; formula_fsm:FSM|count[6]~DUPLICATE ; ; ;
+; formula_fsm:FSM|count[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; formula_fsm:FSM|count[8]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[0]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[1]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[3]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[5]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[8]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[9]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[11]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[13]~DUPLICATE ; ; ;
+; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; tick_50000:TICK0|count[15]~DUPLICATE ; ; ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location ; ; ; ADC_CS ; PIN_AG20 ; QSF Assignment ;
+; Location ; ; ; ADC_SCK ; PIN_AF21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDI ; PIN_AG21 ; QSF Assignment ;
+; Location ; ; ; ADC_SDO ; PIN_AJ21 ; QSF Assignment ;
+; Location ; ; ; DAC_CS ; PIN_AD20 ; QSF Assignment ;
+; Location ; ; ; DAC_LD ; PIN_AK21 ; QSF Assignment ;
+; Location ; ; ; DAC_SCK ; PIN_AF20 ; QSF Assignment ;
+; Location ; ; ; DAC_SDI ; PIN_AG18 ; QSF Assignment ;
+; Location ; ; ; OLED_CLK ; PIN_AJ19 ; QSF Assignment ;
+; Location ; ; ; OLED_CS ; PIN_Y17 ; QSF Assignment ;
+; Location ; ; ; OLED_DATA ; PIN_AJ16 ; QSF Assignment ;
+; Location ; ; ; OLED_DC ; PIN_AK18 ; QSF Assignment ;
+; Location ; ; ; OLED_RST ; PIN_Y18 ; QSF Assignment ;
+; Location ; ; ; PWM_OUT ; PIN_AJ20 ; QSF Assignment ;
+; Location ; ; ; SW[0] ; PIN_AB12 ; QSF Assignment ;
+; Location ; ; ; SW[1] ; PIN_AC12 ; QSF Assignment ;
+; Location ; ; ; SW[2] ; PIN_AF9 ; QSF Assignment ;
+; Location ; ; ; SW[3] ; PIN_AF10 ; QSF Assignment ;
+; Location ; ; ; SW[4] ; PIN_AD11 ; QSF Assignment ;
+; Location ; ; ; SW[5] ; PIN_AD12 ; QSF Assignment ;
+; Location ; ; ; SW[6] ; PIN_AE11 ; QSF Assignment ;
+; Location ; ; ; SW[7] ; PIN_AC9 ; QSF Assignment ;
+; Location ; ; ; SW[8] ; PIN_AD10 ; QSF Assignment ;
+; Location ; ; ; SW[9] ; PIN_AE12 ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; ADC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; ADC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; ADC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; ADC_SDO ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; DAC_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; DAC_LD ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; DAC_SCK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; DAC_SDI ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; OLED_CLK ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; OLED_CS ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; OLED_DATA ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; OLED_DC ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; OLED_RST ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; PWM_OUT ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; SW[0] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; SW[1] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; SW[2] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; SW[3] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; SW[4] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; SW[5] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; SW[6] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; SW[7] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; SW[8] ; 3.3-V LVTTL ; QSF Assignment ;
+; I/O Standard ; ex9 ; ; SW[9] ; 3.3-V LVTTL ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 477 ) ; 0.00 % ( 0 / 477 ) ; 0.00 % ( 0 / 477 ) ;
+; -- Achieved ; 0.00 % ( 0 / 477 ) ; 0.00 % ( 0 / 477 ) ; 0.00 % ( 0 / 477 ) ;
+; ; ; ; ;
+; Routing (by net) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
+; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top ; 0.00 % ( 0 / 477 ) ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource ; Usage ; % ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 154 / 32,070 ; < 1 % ;
+; ALMs needed [=A-B+C] ; 154 ; ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 160 / 32,070 ; < 1 % ;
+; [a] ALMs used for LUT logic and registers ; 34 ; ;
+; [b] ALMs used for LUT logic ; 119 ; ;
+; [c] ALMs used for registers ; 7 ; ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
+; [B] Estimate of ALMs recoverable by dense packing ; 6 / 32,070 ; < 1 % ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32,070 ; 0 % ;
+; [a] Due to location constrained logic ; 0 ; ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; ;
+; [c] Due to LAB input limits ; 0 ; ;
+; [d] Due to virtual I/Os ; 0 ; ;
+; ; ; ;
+; Difficulty packing design ; Low ; ;
+; ; ; ;
+; Total LABs: partially or completely used ; 21 / 3,207 ; < 1 % ;
+; -- Logic LABs ; 21 ; ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 281 ; ;
+; -- 7 input functions ; 2 ; ;
+; -- 6 input functions ; 35 ; ;
+; -- 5 input functions ; 5 ; ;
+; -- 4 input functions ; 154 ; ;
+; -- <=3 input functions ; 85 ; ;
+; Combinational ALUT usage for route-throughs ; 3 ; ;
+; ; ; ;
+; Dedicated logic registers ; 94 ; ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 81 / 64,140 ; < 1 % ;
+; -- Secondary logic registers ; 13 / 64,140 ; < 1 % ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 81 ; ;
+; -- Routing optimization registers ; 13 ; ;
+; ; ; ;
+; Virtual pins ; 0 ; ;
+; I/O pins ; 57 / 457 ; 12 % ;
+; -- Clock pins ; 4 / 8 ; 50 % ;
+; -- Dedicated input pins ; 0 / 21 ; 0 % ;
+; ; ; ;
+; Hard processor system peripheral utilization ; ; ;
+; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
+; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
+; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
+; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
+; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
+; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
+; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
+; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
+; -- JTAG ; 0 / 1 ( 0 % ) ; ;
+; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
+; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
+; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
+; -- STM event ; 0 / 1 ( 0 % ) ; ;
+; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
+; -- DMA ; 0 / 1 ( 0 % ) ; ;
+; -- CAN ; 0 / 2 ( 0 % ) ; ;
+; -- EMAC ; 0 / 2 ( 0 % ) ; ;
+; -- I2C ; 0 / 4 ( 0 % ) ; ;
+; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
+; -- QSPI ; 0 / 1 ( 0 % ) ; ;
+; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
+; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
+; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
+; -- UART ; 0 / 2 ( 0 % ) ; ;
+; -- USB ; 0 / 2 ( 0 % ) ; ;
+; ; ; ;
+; M10K blocks ; 0 / 397 ; 0 % ;
+; Total MLAB memory bits ; 0 ; ;
+; Total block memory bits ; 0 / 4,065,280 ; 0 % ;
+; Total block memory implementation bits ; 0 / 4,065,280 ; 0 % ;
+; ; ; ;
+; Total DSP Blocks ; 0 / 87 ; 0 % ;
+; ; ; ;
+; Fractional PLLs ; 0 / 6 ; 0 % ;
+; Global signals ; 1 ; ;
+; -- Global clocks ; 1 / 16 ; 6 % ;
+; -- Quadrant clocks ; 0 / 66 ; 0 % ;
+; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ;
+; SERDES Transmitters ; 0 / 100 ; 0 % ;
+; SERDES Receivers ; 0 / 100 ; 0 % ;
+; JTAGs ; 0 / 1 ; 0 % ;
+; ASMI blocks ; 0 / 1 ; 0 % ;
+; CRC blocks ; 0 / 1 ; 0 % ;
+; Remote update blocks ; 0 / 1 ; 0 % ;
+; Oscillator blocks ; 0 / 1 ; 0 % ;
+; Impedance control blocks ; 0 / 4 ; 0 % ;
+; Hard Memory Controllers ; 0 / 2 ; 0 % ;
+; Average interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.1% ; ;
+; Peak interconnect usage (total/H/V) ; 2.1% / 2.5% / 1.2% ; ;
+; Maximum fan-out ; 68 ; ;
+; Highest non-global fan-out ; 68 ; ;
+; Total fan-out ; 1416 ; ;
+; Average fan-out ; 2.87 ; ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Statistic ; Top ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device) ; 154 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; ALMs needed [=A-B+C] ; 154 ; 0 ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 160 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] ALMs used for LUT logic and registers ; 34 ; 0 ;
+; [b] ALMs used for LUT logic ; 119 ; 0 ;
+; [c] ALMs used for registers ; 7 ; 0 ;
+; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
+; [B] Estimate of ALMs recoverable by dense packing ; 6 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 32070 ( 0 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] Due to location constrained logic ; 0 ; 0 ;
+; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
+; [c] Due to LAB input limits ; 0 ; 0 ;
+; [d] Due to virtual I/Os ; 0 ; 0 ;
+; ; ; ;
+; Difficulty packing design ; Low ; Low ;
+; ; ; ;
+; Total LABs: partially or completely used ; 21 / 3207 ( < 1 % ) ; 0 / 3207 ( 0 % ) ;
+; -- Logic LABs ; 21 ; 0 ;
+; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
+; ; ; ;
+; Combinational ALUT usage for logic ; 281 ; 0 ;
+; -- 7 input functions ; 2 ; 0 ;
+; -- 6 input functions ; 35 ; 0 ;
+; -- 5 input functions ; 5 ; 0 ;
+; -- 4 input functions ; 154 ; 0 ;
+; -- <=3 input functions ; 85 ; 0 ;
+; Combinational ALUT usage for route-throughs ; 3 ; 0 ;
+; Memory ALUT usage ; 0 ; 0 ;
+; -- 64-address deep ; 0 ; 0 ;
+; -- 32-address deep ; 0 ; 0 ;
+; ; ; ;
+; Dedicated logic registers ; 0 ; 0 ;
+; -- By type: ; ; ;
+; -- Primary logic registers ; 81 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
+; -- Secondary logic registers ; 13 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
+; -- By function: ; ; ;
+; -- Design implementation registers ; 81 ; 0 ;
+; -- Routing optimization registers ; 13 ; 0 ;
+; ; ; ;
+; ; ; ;
+; Virtual pins ; 0 ; 0 ;
+; I/O pins ; 57 ; 0 ;
+; I/O registers ; 0 ; 0 ;
+; Total block memory bits ; 0 ; 0 ;
+; Total block memory implementation bits ; 0 ; 0 ;
+; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ;
+; ; ; ;
+; Connections ; ; ;
+; -- Input Connections ; 0 ; 0 ;
+; -- Registered Input Connections ; 0 ; 0 ;
+; -- Output Connections ; 0 ; 0 ;
+; -- Registered Output Connections ; 0 ; 0 ;
+; ; ; ;
+; Internal Connections ; ; ;
+; -- Total Connections ; 1416 ; 0 ;
+; -- Registered Connections ; 424 ; 0 ;
+; ; ; ;
+; External Connections ; ; ;
+; -- Top ; 0 ; 0 ;
+; -- hard_block:auto_generated_inst ; 0 ; 0 ;
+; ; ; ;
+; Partition Interface ; ; ;
+; -- Input Ports ; 5 ; 0 ;
+; -- Output Ports ; 52 ; 0 ;
+; -- Bidir Ports ; 0 ; 0 ;
+; ; ; ;
+; Registered Ports ; ; ;
+; -- Registered Input Ports ; 0 ; 0 ;
+; -- Registered Output Ports ; 0 ; 0 ;
+; ; ; ;
+; Port Connectivity ; ; ;
+; -- Input Ports driven by GND ; 0 ; 0 ;
+; -- Output Ports driven by GND ; 0 ; 0 ;
+; -- Input Ports driven by VCC ; 0 ; 0 ;
+; -- Output Ports driven by VCC ; 0 ; 0 ;
+; -- Input Ports with no Source ; 0 ; 0 ;
+; -- Output Ports with no Source ; 0 ; 0 ;
+; -- Input Ports with no Fanout ; 0 ; 0 ;
+; -- Output Ports with no Fanout ; 0 ; 0 ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; CLOCK_50 ; AF14 ; 3B ; 32 ; 0 ; 0 ; 26 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; KEY[0] ; AA14 ; 3B ; 36 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; KEY[1] ; AA15 ; 3B ; 36 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; KEY[2] ; W15 ; 3B ; 40 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+; KEY[3] ; Y16 ; 3B ; 40 ; 0 ; 17 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[1] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[2] ; AE28 ; 5A ; 89 ; 11 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[3] ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[4] ; AF28 ; 5A ; 89 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[5] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX0[6] ; AH28 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[0] ; AJ29 ; 5A ; 89 ; 6 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[1] ; AH29 ; 5A ; 89 ; 6 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[2] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[3] ; AG30 ; 5A ; 89 ; 16 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[4] ; AF29 ; 5A ; 89 ; 15 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[5] ; AF30 ; 5A ; 89 ; 15 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX1[6] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[0] ; AB23 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[1] ; AE29 ; 5B ; 89 ; 23 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[2] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[3] ; AC28 ; 5B ; 89 ; 20 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[4] ; AD30 ; 5B ; 89 ; 25 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[5] ; AC29 ; 5B ; 89 ; 20 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX2[6] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[0] ; AD26 ; 5A ; 89 ; 16 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[1] ; AC27 ; 5A ; 89 ; 16 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[2] ; AD25 ; 5A ; 89 ; 4 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[3] ; AC25 ; 5A ; 89 ; 4 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[4] ; AB28 ; 5B ; 89 ; 21 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[5] ; AB25 ; 5A ; 89 ; 11 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX3[6] ; AB22 ; 5A ; 89 ; 9 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[0] ; AA24 ; 5A ; 89 ; 11 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[1] ; Y23 ; 5A ; 89 ; 13 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[2] ; Y24 ; 5A ; 89 ; 13 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[3] ; W22 ; 5A ; 89 ; 8 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[4] ; W24 ; 5A ; 89 ; 15 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[5] ; V23 ; 5A ; 89 ; 15 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX4[6] ; W25 ; 5B ; 89 ; 20 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX5[0] ; V25 ; 5B ; 89 ; 20 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX5[1] ; AA28 ; 5B ; 89 ; 21 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX5[2] ; Y27 ; 5B ; 89 ; 25 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX5[3] ; AB27 ; 5B ; 89 ; 23 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX5[4] ; AB26 ; 5A ; 89 ; 9 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX5[5] ; AA26 ; 5B ; 89 ; 23 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; HEX5[6] ; AA25 ; 5A ; 89 ; 9 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[0] ; V16 ; 4A ; 52 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[1] ; W16 ; 4A ; 52 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[2] ; V17 ; 4A ; 60 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[3] ; V18 ; 4A ; 80 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[4] ; W17 ; 4A ; 60 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[5] ; W19 ; 4A ; 80 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[6] ; Y19 ; 4A ; 84 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[7] ; W20 ; 5A ; 89 ; 6 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[8] ; W21 ; 5A ; 89 ; 8 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+; LEDR[9] ; Y21 ; 5A ; 89 ; 6 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-----------------------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+-------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+-------------------+---------------+--------------+---------------+
+; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
+; 3A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 3B ; 5 / 48 ( 10 % ) ; 3.3V ; -- ; 3.3V ;
+; 4A ; 7 / 80 ( 9 % ) ; 3.3V ; -- ; 3.3V ;
+; 5A ; 32 / 32 ( 100 % ) ; 3.3V ; -- ; 3.3V ;
+; 5B ; 13 / 16 ( 81 % ) ; 3.3V ; -- ; 3.3V ;
+; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
+; 8A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
++----------+-------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A8 ; 473 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
+; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
+; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA13 ; 90 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA14 ; 122 ; 3B ; KEY[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA15 ; 120 ; 3B ; KEY[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA17 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AA24 ; 228 ; 5A ; HEX4[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AA25 ; 224 ; 5A ; HEX5[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AA26 ; 252 ; 5B ; HEX5[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AA27 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA28 ; 251 ; 5B ; HEX5[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB12 ; 72 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB14 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB17 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB22 ; 225 ; 5A ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB23 ; 227 ; 5A ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB24 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB25 ; 230 ; 5A ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB26 ; 226 ; 5A ; HEX5[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB27 ; 254 ; 5B ; HEX5[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB28 ; 249 ; 5B ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC11 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AC12 ; 82 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC14 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC20 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC21 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AC25 ; 215 ; 5A ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC27 ; 242 ; 5A ; HEX3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC28 ; 245 ; 5B ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC29 ; 247 ; 5B ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AC30 ; 259 ; 5B ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD8 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD10 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD11 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD12 ; 80 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD17 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD18 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD20 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD25 ; 213 ; 5A ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD26 ; 240 ; 5A ; HEX3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD27 ; 222 ; 5A ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD28 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AD29 ; 255 ; 5B ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AD30 ; 257 ; 5B ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE7 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; AE9 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE11 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE12 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE13 ; 95 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE15 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AE16 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE17 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AE22 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE25 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AE26 ; 220 ; 5A ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE27 ; 229 ; 5A ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE28 ; 231 ; 5A ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE29 ; 253 ; 5B ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AE30 ; ; 5B ; VCCIO5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF5 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF9 ; 67 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF10 ; 57 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF14 ; 114 ; 3B ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF18 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF22 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AF23 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF28 ; 235 ; 5A ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AF29 ; 237 ; 5A ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AF30 ; 239 ; 5A ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG2 ; 83 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG4 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG8 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG10 ; 86 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG19 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG27 ; 212 ; 5A ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG28 ; 233 ; 5A ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AG29 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AG30 ; 243 ; 5A ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH8 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH10 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH15 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH16 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH19 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH23 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH25 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH26 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH28 ; 214 ; 5A ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH29 ; 218 ; 5A ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AH30 ; 241 ; 5A ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ2 ; 77 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ5 ; 99 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ10 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ22 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AJ24 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ26 ; 187 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AJ29 ; 216 ; 5A ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK4 ; 92 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK10 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK12 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK20 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AK21 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK22 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AK26 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AK29 ; 196 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B1 ; 509 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B7 ; 477 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
+; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
+; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
+; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C4 ; 501 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
+; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D4 ; 521 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D9 ; 480 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D10 ; 472 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
+; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
+; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E2 ; 525 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E6 ; 533 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
+; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F10 ; 528 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F14 ; 468 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
+; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
+; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
+; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
+; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
+; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G8 ; 492 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G12 ; 518 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
+; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H12 ; 500 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
+; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J14 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
+; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
+; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K12 ; 514 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
+; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
+; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
+; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U23 ; ; 5B ; VCCPD5B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; V16 ; 138 ; 4A ; LEDR[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V17 ; 154 ; 4A ; LEDR[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V18 ; 194 ; 4A ; LEDR[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V22 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V23 ; 236 ; 5A ; HEX4[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; V24 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V25 ; 246 ; 5B ; HEX5[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; W15 ; 130 ; 3B ; KEY[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W16 ; 136 ; 4A ; LEDR[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W17 ; 152 ; 4A ; LEDR[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W19 ; 192 ; 4A ; LEDR[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W20 ; 217 ; 5A ; LEDR[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W21 ; 221 ; 5A ; LEDR[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W22 ; 223 ; 5A ; HEX4[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W23 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; W24 ; 238 ; 5A ; HEX4[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W25 ; 244 ; 5B ; HEX4[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
+; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
+; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y16 ; 128 ; 3B ; KEY[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y17 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y19 ; 202 ; 4A ; LEDR[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y21 ; 219 ; 5A ; LEDR[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; Y23 ; 232 ; 5A ; HEX4[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y24 ; 234 ; 5A ; HEX4[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y27 ; 258 ; 5B ; HEX5[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings ;
++----------+--------------------------------------+
+; Pin Name ; Reason ;
++----------+--------------------------------------+
+; HEX0[0] ; Missing drive strength and slew rate ;
+; HEX0[1] ; Missing drive strength and slew rate ;
+; HEX0[2] ; Missing drive strength and slew rate ;
+; HEX0[3] ; Missing drive strength and slew rate ;
+; HEX0[4] ; Missing drive strength and slew rate ;
+; HEX0[5] ; Missing drive strength and slew rate ;
+; HEX0[6] ; Missing drive strength and slew rate ;
+; HEX1[0] ; Missing drive strength and slew rate ;
+; HEX1[1] ; Missing drive strength and slew rate ;
+; HEX1[2] ; Missing drive strength and slew rate ;
+; HEX1[3] ; Missing drive strength and slew rate ;
+; HEX1[4] ; Missing drive strength and slew rate ;
+; HEX1[5] ; Missing drive strength and slew rate ;
+; HEX1[6] ; Missing drive strength and slew rate ;
+; HEX2[0] ; Missing drive strength and slew rate ;
+; HEX2[1] ; Missing drive strength and slew rate ;
+; HEX2[2] ; Missing drive strength and slew rate ;
+; HEX2[3] ; Missing drive strength and slew rate ;
+; HEX2[4] ; Missing drive strength and slew rate ;
+; HEX2[5] ; Missing drive strength and slew rate ;
+; HEX2[6] ; Missing drive strength and slew rate ;
+; HEX3[0] ; Missing drive strength and slew rate ;
+; HEX3[1] ; Missing drive strength and slew rate ;
+; HEX3[2] ; Missing drive strength and slew rate ;
+; HEX3[3] ; Missing drive strength and slew rate ;
+; HEX3[4] ; Missing drive strength and slew rate ;
+; HEX3[5] ; Missing drive strength and slew rate ;
+; HEX3[6] ; Missing drive strength and slew rate ;
+; HEX4[0] ; Missing drive strength and slew rate ;
+; HEX4[1] ; Missing drive strength and slew rate ;
+; HEX4[2] ; Missing drive strength and slew rate ;
+; HEX4[3] ; Missing drive strength and slew rate ;
+; HEX4[4] ; Missing drive strength and slew rate ;
+; HEX4[5] ; Missing drive strength and slew rate ;
+; HEX4[6] ; Missing drive strength and slew rate ;
+; HEX5[0] ; Missing drive strength and slew rate ;
+; HEX5[1] ; Missing drive strength and slew rate ;
+; HEX5[2] ; Missing drive strength and slew rate ;
+; HEX5[3] ; Missing drive strength and slew rate ;
+; HEX5[4] ; Missing drive strength and slew rate ;
+; HEX5[5] ; Missing drive strength and slew rate ;
+; HEX5[6] ; Missing drive strength and slew rate ;
+; LEDR[0] ; Missing drive strength and slew rate ;
+; LEDR[1] ; Missing drive strength and slew rate ;
+; LEDR[2] ; Missing drive strength and slew rate ;
+; LEDR[3] ; Missing drive strength and slew rate ;
+; LEDR[4] ; Missing drive strength and slew rate ;
+; LEDR[5] ; Missing drive strength and slew rate ;
+; LEDR[6] ; Missing drive strength and slew rate ;
+; LEDR[7] ; Missing drive strength and slew rate ;
+; LEDR[8] ; Missing drive strength and slew rate ;
+; LEDR[9] ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+; |ex9 ; 154.0 (0.5) ; 159.0 (0.5) ; 5.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 281 (1) ; 94 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 57 ; 0 ; |ex9 ; ex9 ; work ;
+; |LFSR:LFSR0| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|LFSR:LFSR0 ; LFSR ; work ;
+; |bin2bcd_16:BCD| ; 67.2 (0.0) ; 67.5 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 123 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD ; bin2bcd_16 ; work ;
+; |add3_ge5:A1| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A1 ; add3_ge5 ; work ;
+; |add3_ge5:A10| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5 ; work ;
+; |add3_ge5:A11| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5 ; work ;
+; |add3_ge5:A12| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5 ; work ;
+; |add3_ge5:A13| ; 4.0 (4.0) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5 ; work ;
+; |add3_ge5:A14| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5 ; work ;
+; |add3_ge5:A15| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5 ; work ;
+; |add3_ge5:A16| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5 ; work ;
+; |add3_ge5:A17| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5 ; work ;
+; |add3_ge5:A18| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5 ; work ;
+; |add3_ge5:A19| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5 ; work ;
+; |add3_ge5:A2| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A2 ; add3_ge5 ; work ;
+; |add3_ge5:A20| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5 ; work ;
+; |add3_ge5:A21| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5 ; work ;
+; |add3_ge5:A22| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5 ; work ;
+; |add3_ge5:A23| ; 4.0 (4.0) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5 ; work ;
+; |add3_ge5:A24| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5 ; work ;
+; |add3_ge5:A25| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5 ; work ;
+; |add3_ge5:A26| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5 ; work ;
+; |add3_ge5:A27| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5 ; work ;
+; |add3_ge5:A28| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5 ; work ;
+; |add3_ge5:A29| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5 ; work ;
+; |add3_ge5:A3| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A3 ; add3_ge5 ; work ;
+; |add3_ge5:A30| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5 ; work ;
+; |add3_ge5:A32| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5 ; work ;
+; |add3_ge5:A33| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5 ; work ;
+; |add3_ge5:A34| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5 ; work ;
+; |add3_ge5:A35| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5 ; work ;
+; |add3_ge5:A4| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A4 ; add3_ge5 ; work ;
+; |add3_ge5:A5| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A5 ; add3_ge5 ; work ;
+; |add3_ge5:A6| ; 3.7 (3.7) ; 4.0 (4.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A6 ; add3_ge5 ; work ;
+; |add3_ge5:A7| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A7 ; add3_ge5 ; work ;
+; |add3_ge5:A8| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A8 ; add3_ge5 ; work ;
+; |add3_ge5:A9| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A9 ; add3_ge5 ; work ;
+; |counter_16:COUNT0| ; 8.5 (8.5) ; 9.0 (9.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|counter_16:COUNT0 ; counter_16 ; work ;
+; |delay:DEL0| ; 13.3 (13.3) ; 13.8 (13.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (23) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|delay:DEL0 ; delay ; work ;
+; |formula_fsm:FSM| ; 21.5 (21.5) ; 24.2 (24.2) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (37) ; 26 (26) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|formula_fsm:FSM ; formula_fsm ; work ;
+; |hex_to_7seg:SEG0| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG1| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG2| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG3| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG3 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG4| ; 7.5 (7.5) ; 7.5 (7.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG4 ; hex_to_7seg ; work ;
+; |tick_50000:TICK0| ; 18.5 (18.5) ; 19.0 (19.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (36) ; 26 (26) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |ex9|tick_50000:TICK0 ; tick_50000 ; work ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; KEY[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; KEY[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX4[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX5[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX5[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX5[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX5[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX5[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX5[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; HEX5[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
+; KEY[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; CLOCK_50 ; Input ; -- ; (0) ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; KEY[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++-------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++-------------------------------------------------+-------------------+---------+
+; KEY[1] ; ; ;
+; KEY[2] ; ; ;
+; KEY[0] ; ; ;
+; - counter_16:COUNT0|count~0 ; 0 ; 0 ;
+; CLOCK_50 ; ; ;
+; - tick_50000:TICK0|CLK_OUT ; 1 ; 0 ;
+; KEY[3] ; ; ;
+; - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~1 ; 1 ; 0 ;
+; - formula_fsm:FSM|Selector2~0 ; 1 ; 0 ;
+; - formula_fsm:FSM|Selector3~0 ; 1 ; 0 ;
++-------------------------------------------------+-------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 2 ; Clock ; no ; -- ; -- ; -- ;
+; CLOCK_50 ; PIN_AF14 ; 25 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ;
+; counter_16:COUNT0|count~0 ; LABCELL_X18_Y3_N57 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
+; counter_16:COUNT0|state ; FF_X18_Y3_N53 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ;
+; delay:DEL0|count[1]~0 ; MLABCELL_X34_Y3_N48 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
+; delay:DEL0|state.COUNTING ; FF_X34_Y3_N5 ; 18 ; Sync. load ; no ; -- ; -- ; -- ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X34_Y3_N14 ; 22 ; Clock enable, Latch enable ; no ; -- ; -- ; -- ;
+; formula_fsm:FSM|state.WAIT_TRIGGER ; FF_X34_Y3_N35 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
+; tick_50000:TICK0|CLK_OUT ; FF_X4_Y3_N23 ; 68 ; Clock ; no ; -- ; -- ; -- ;
++-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 25 ; Global Clock ; GCLK6 ; -- ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type ; Usage ;
++---------------------------------------------+-------------------------+
+; Block interconnects ; 366 / 289,320 ( < 1 % ) ;
+; C12 interconnects ; 7 / 13,420 ( < 1 % ) ;
+; C2 interconnects ; 62 / 119,108 ( < 1 % ) ;
+; C4 interconnects ; 96 / 56,300 ( < 1 % ) ;
+; DQS bus muxes ; 0 / 25 ( 0 % ) ;
+; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
+; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
+; Direct links ; 78 / 289,320 ( < 1 % ) ;
+; Global clocks ; 1 / 16 ( 6 % ) ;
+; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
+; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
+; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
+; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
+; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
+; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
+; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
+; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
+; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
+; Local interconnects ; 128 / 84,580 ( < 1 % ) ;
+; Quadrant clocks ; 0 / 66 ( 0 % ) ;
+; R14 interconnects ; 95 / 12,676 ( < 1 % ) ;
+; R14/C12 interconnect drivers ; 100 / 20,720 ( < 1 % ) ;
+; R3 interconnects ; 176 / 130,992 ( < 1 % ) ;
+; R6 interconnects ; 289 / 266,960 ( < 1 % ) ;
+; Spine clocks ; 1 / 360 ( < 1 % ) ;
+; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary ;
++----------------------------------+-------+
+; I/O Rules Statistic ; Total ;
++----------------------------------+-------+
+; Total I/O Rules ; 28 ;
+; Number of I/O Rules Passed ; 6 ;
+; Number of I/O Rules Failed ; 0 ;
+; Number of I/O Rules Unchecked ; 0 ;
+; Number of I/O Rules Inapplicable ; 22 ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
+; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
+; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+; Pin/Rules ; IO_000002 ; IO_000003 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000022 ; IO_000021 ; IO_000046 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000047 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+; Total Pass ; 0 ; 57 ; 57 ; 0 ; 0 ; 57 ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 57 ; 57 ; 0 ;
+; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Inapplicable ; 57 ; 0 ; 0 ; 57 ; 57 ; 0 ; 0 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 57 ; 0 ; 0 ; 57 ;
+; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; KEY[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX0[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX1[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX2[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX3[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX4[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX5[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX5[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX5[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX5[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX5[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX5[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; HEX5[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; LEDR[9] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; CLOCK_50 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
+; KEY[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options ;
++------------------------------------------------------------------+-----------------------------+
+; Option ; Setting ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Passive Serial ;
+; Enable Error Detection CRC_ERROR pin ; Off ;
+; Enable CvP_CONFDONE pin ; Off ;
+; Enable open drain on CRC_ERROR pin ; On ;
+; Enable open drain on CvP_CONFDONE pin ; On ;
+; Enable open drain on INIT_DONE pin ; On ;
+; Enable open drain on Partial Reconfiguration pins ; Off ;
+; Enable open drain on nCEO pin ; On ;
+; Enable Partial Reconfiguration pins ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ;
+; Enable internal scrubbing ; Off ;
+; Active Serial clock source ; 100 MHz Internal Oscillator ;
+; Device initialization clock source ; Internal Oscillator ;
+; Configuration via Protocol ; Off ;
+; Configuration Voltage Level ; Auto ;
+; Force Configuration Voltage Level ; Off ;
+; Enable nCEO output ; Off ;
+; Data[15..8] ; Unreserved ;
+; Data[7..5] ; Unreserved ;
+; Base pin-out file on sameframe device ; Off ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.10 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary ;
++--------------------------------------------------------------+--------------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++--------------------------------------------------------------+--------------------------+-------------------+
+; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 89.8 ;
+; CLOCK_50 ; CLOCK_50 ; 11.0 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 6.9 ;
+; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.8 ;
++--------------------------------------------------------------+--------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++-----------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details ;
++----------------------------------------+----------------------------------------+-------------------+
+; Source Register ; Destination Register ; Delay Added in ns ;
++----------------------------------------+----------------------------------------+-------------------+
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 3.263 ;
+; formula_fsm:FSM|start_delay ; delay:DEL0|state.COUNTING ; 3.060 ;
+; formula_fsm:FSM|count[6] ; formula_fsm:FSM|ledr[8] ; 1.663 ;
+; formula_fsm:FSM|count[7] ; formula_fsm:FSM|ledr[8] ; 1.638 ;
+; formula_fsm:FSM|count[8] ; formula_fsm:FSM|ledr[8] ; 1.633 ;
+; delay:DEL0|count[8] ; delay:DEL0|state.IDLE ; 1.617 ;
+; formula_fsm:FSM|count[1] ; formula_fsm:FSM|ledr[8] ; 1.586 ;
+; delay:DEL0|count[6] ; delay:DEL0|state.IDLE ; 1.573 ;
+; formula_fsm:FSM|count[0] ; formula_fsm:FSM|ledr[8] ; 1.564 ;
+; formula_fsm:FSM|count[3] ; formula_fsm:FSM|ledr[8] ; 1.562 ;
+; formula_fsm:FSM|count[2] ; formula_fsm:FSM|ledr[8] ; 1.560 ;
+; delay:DEL0|count[2] ; delay:DEL0|state.IDLE ; 1.551 ;
+; delay:DEL0|count[3] ; delay:DEL0|state.IDLE ; 1.546 ;
+; delay:DEL0|count[13] ; delay:DEL0|state.IDLE ; 1.535 ;
+; delay:DEL0|count[10] ; delay:DEL0|state.IDLE ; 1.532 ;
+; formula_fsm:FSM|count[4] ; formula_fsm:FSM|ledr[8] ; 1.513 ;
+; tick_50000:TICK0|count[5] ; tick_50000:TICK0|CLK_OUT ; 1.470 ;
+; tick_50000:TICK0|count[11] ; tick_50000:TICK0|CLK_OUT ; 1.445 ;
+; formula_fsm:FSM|ledr[7] ; formula_fsm:FSM|ledr[8] ; 1.443 ;
+; formula_fsm:FSM|ledr[8] ; formula_fsm:FSM|ledr[8] ; 1.443 ;
+; formula_fsm:FSM|count[5] ; formula_fsm:FSM|ledr[8] ; 1.443 ;
+; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[8] ; 1.443 ;
+; formula_fsm:FSM|ledr[9] ; formula_fsm:FSM|ledr[9] ; 1.427 ;
+; delay:DEL0|count[7] ; delay:DEL0|state.IDLE ; 1.419 ;
+; delay:DEL0|count[4] ; delay:DEL0|state.IDLE ; 1.418 ;
+; delay:DEL0|count[11] ; delay:DEL0|state.IDLE ; 1.409 ;
+; tick_50000:TICK0|count[9] ; tick_50000:TICK0|CLK_OUT ; 1.404 ;
+; tick_50000:TICK0|count[8] ; tick_50000:TICK0|CLK_OUT ; 1.402 ;
+; delay:DEL0|count[9] ; delay:DEL0|state.IDLE ; 1.381 ;
+; tick_50000:TICK0|count[14] ; tick_50000:TICK0|CLK_OUT ; 1.365 ;
+; tick_50000:TICK0|count[6] ; tick_50000:TICK0|CLK_OUT ; 1.364 ;
+; tick_50000:TICK0|count[2] ; tick_50000:TICK0|CLK_OUT ; 1.361 ;
+; tick_50000:TICK0|count[12] ; tick_50000:TICK0|CLK_OUT ; 1.355 ;
+; tick_50000:TICK0|count[15] ; tick_50000:TICK0|CLK_OUT ; 1.349 ;
+; delay:DEL0|count[5] ; delay:DEL0|state.IDLE ; 1.346 ;
+; tick_50000:TICK0|count[3] ; tick_50000:TICK0|CLK_OUT ; 1.346 ;
+; tick_50000:TICK0|count[13] ; tick_50000:TICK0|CLK_OUT ; 1.343 ;
+; delay:DEL0|state.WAIT_LOW ; delay:DEL0|state.IDLE ; 1.332 ;
+; delay:DEL0|count[12] ; delay:DEL0|state.IDLE ; 1.332 ;
+; delay:DEL0|count[1] ; delay:DEL0|state.IDLE ; 1.332 ;
+; delay:DEL0|count[0] ; delay:DEL0|state.IDLE ; 1.332 ;
+; delay:DEL0|state.IDLE ; delay:DEL0|state.IDLE ; 1.332 ;
+; delay:DEL0|state.COUNTING ; delay:DEL0|state.IDLE ; 1.332 ;
+; delay:DEL0|state.TIME_OUT ; delay:DEL0|state.IDLE ; 1.332 ;
+; tick_50000:TICK0|count[4] ; tick_50000:TICK0|CLK_OUT ; 1.317 ;
+; tick_50000:TICK0|count[0] ; tick_50000:TICK0|CLK_OUT ; 1.306 ;
+; tick_50000:TICK0|count[7] ; tick_50000:TICK0|CLK_OUT ; 1.305 ;
+; tick_50000:TICK0|count[1] ; tick_50000:TICK0|CLK_OUT ; 1.278 ;
+; tick_50000:TICK0|count[10] ; tick_50000:TICK0|CLK_OUT ; 1.263 ;
+; formula_fsm:FSM|ledr[0] ; formula_fsm:FSM|ledr[0] ; 1.241 ;
+; formula_fsm:FSM|ledr[6] ; formula_fsm:FSM|ledr[7] ; 1.231 ;
+; formula_fsm:FSM|ledr[2] ; formula_fsm:FSM|ledr[3] ; 1.161 ;
+; formula_fsm:FSM|ledr[3] ; formula_fsm:FSM|ledr[3] ; 1.161 ;
+; formula_fsm:FSM|ledr[5] ; formula_fsm:FSM|ledr[6] ; 1.161 ;
+; formula_fsm:FSM|ledr[4] ; formula_fsm:FSM|ledr[4] ; 1.154 ;
+; formula_fsm:FSM|ledr[1] ; formula_fsm:FSM|ledr[1] ; 1.150 ;
+; LFSR:LFSR0|COUNT[1] ; LFSR:LFSR0|COUNT[2] ; 1.098 ;
+; formula_fsm:FSM|state.WAIT_TRIGGER ; formula_fsm:FSM|count[2] ; 1.077 ;
+; LFSR:LFSR0|COUNT[7] ; LFSR:LFSR0|COUNT[1] ; 1.044 ;
+; LFSR:LFSR0|COUNT[2] ; LFSR:LFSR0|COUNT[3] ; 0.755 ;
+; LFSR:LFSR0|COUNT[3] ; LFSR:LFSR0|COUNT[4] ; 0.755 ;
+; LFSR:LFSR0|COUNT[4] ; LFSR:LFSR0|COUNT[5] ; 0.755 ;
+; LFSR:LFSR0|COUNT[5] ; LFSR:LFSR0|COUNT[6] ; 0.755 ;
+; counter_16:COUNT0|state ; counter_16:COUNT0|state ; 0.736 ;
+; LFSR:LFSR0|COUNT[6] ; LFSR:LFSR0|COUNT[7] ; 0.602 ;
+; tick_50000:TICK0|CLK_OUT ; counter_16:COUNT0|state ; 0.577 ;
+; counter_16:COUNT0|count[7] ; counter_16:COUNT0|count[15] ; 0.354 ;
+; counter_16:COUNT0|count[12] ; counter_16:COUNT0|count[15] ; 0.343 ;
+; counter_16:COUNT0|count[1] ; counter_16:COUNT0|count[15] ; 0.343 ;
+; counter_16:COUNT0|count[0] ; counter_16:COUNT0|count[15] ; 0.342 ;
+; counter_16:COUNT0|count[8] ; counter_16:COUNT0|count[15] ; 0.341 ;
+; counter_16:COUNT0|count[5] ; counter_16:COUNT0|count[15] ; 0.341 ;
+; counter_16:COUNT0|count[13] ; counter_16:COUNT0|count[15] ; 0.337 ;
+; counter_16:COUNT0|count[6] ; counter_16:COUNT0|count[15] ; 0.332 ;
+; counter_16:COUNT0|count[9] ; counter_16:COUNT0|count[15] ; 0.331 ;
+; counter_16:COUNT0|count[3] ; counter_16:COUNT0|count[15] ; 0.328 ;
+; KEY[0] ; counter_16:COUNT0|state ; 0.308 ;
+; KEY[3] ; formula_fsm:FSM|state.WAIT_TRIGGER ; 0.226 ;
+; counter_16:COUNT0|count[11] ; counter_16:COUNT0|count[15] ; 0.160 ;
+; counter_16:COUNT0|count[14] ; counter_16:COUNT0|count[15] ; 0.151 ;
+; counter_16:COUNT0|count[10] ; counter_16:COUNT0|count[15] ; 0.147 ;
+; counter_16:COUNT0|count[4] ; counter_16:COUNT0|count[15] ; 0.147 ;
+; counter_16:COUNT0|count[2] ; counter_16:COUNT0|count[15] ; 0.137 ;
++----------------------------------------+----------------------------------------+-------------------+
+Note: This table only shows the top 83 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex9"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+ Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176235): Finished register packing
+ Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+ Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:13
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X33_Y0 to location X44_Y10
+Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:04
+Info (11888): Total time spent on timing analysis during the Fitter is 0.54 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 31 warnings
+ Info: Peak virtual memory: 2145 megabytes
+ Info: Processing ended: Sun Dec 11 20:30:52 2016
+ Info: Elapsed time: 00:00:37
+ Info: Total CPU time (on all processors): 00:01:04
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.fit.smsg.
+
+
diff --git a/part_2/ex9/output_files/ex9.fit.smsg b/part_2/ex9/output_files/ex9.fit.smsg
index 43eead5..9302919 100644
--- a/part_2/ex9/output_files/ex9.fit.smsg
+++ b/part_2/ex9/output_files/ex9.fit.smsg
@@ -1,6 +1,6 @@
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
-Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_2/ex9/output_files/ex9.fit.summary b/part_2/ex9/output_files/ex9.fit.summary
index 496001c..47aeb86 100644
--- a/part_2/ex9/output_files/ex9.fit.summary
+++ b/part_2/ex9/output_files/ex9.fit.summary
@@ -1,20 +1,20 @@
-Fitter Status : Successful - Wed Dec 07 12:08:07 2016
-Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex9
-Top-level Entity Name : ex9
-Family : Cyclone V
-Device : 5CSEMA5F31C6
-Timing Models : Final
-Logic utilization (in ALMs) : 159 / 32,070 ( < 1 % )
-Total registers : 95
-Total pins : 57 / 457 ( 12 % )
-Total virtual pins : 0
-Total block memory bits : 0 / 4,065,280 ( 0 % )
-Total RAM Blocks : 0 / 397 ( 0 % )
-Total DSP Blocks : 0 / 87 ( 0 % )
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0 / 6 ( 0 % )
-Total DLLs : 0 / 4 ( 0 % )
+Fitter Status : Successful - Sun Dec 11 20:30:51 2016
+Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Revision Name : ex9
+Top-level Entity Name : ex9
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 154 / 32,070 ( < 1 % )
+Total registers : 94
+Total pins : 57 / 457 ( 12 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_2/ex9/output_files/ex9.flow.rpt b/part_2/ex9/output_files/ex9.flow.rpt
index 1f2bee6..f289207 100644
--- a/part_2/ex9/output_files/ex9.flow.rpt
+++ b/part_2/ex9/output_files/ex9.flow.rpt
@@ -1,128 +1,128 @@
-Flow report for ex9
-Wed Dec 07 12:08:29 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Flow Summary ;
-+---------------------------------+-------------------------------------------------+
-; Flow Status ; Successful - Wed Dec 07 12:08:20 2016 ;
-; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name ; ex9 ;
-; Top-level Entity Name ; ex9 ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Logic utilization (in ALMs) ; 159 / 32,070 ( < 1 % ) ;
-; Total registers ; 95 ;
-; Total pins ; 57 / 457 ( 12 % ) ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
-; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 / 6 ( 0 % ) ;
-; Total DLLs ; 0 / 4 ( 0 % ) ;
-+---------------------------------+-------------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 12/07/2016 12:07:14 ;
-; Main task ; Compilation ;
-; Revision Name ; ex9 ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID ; 260248564297098.148111243406576 ; -- ; -- ; -- ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 918 MB ; 00:00:23 ;
-; Fitter ; 00:00:35 ; 1.0 ; 2593 MB ; 00:01:01 ;
-; Assembler ; 00:00:08 ; 1.0 ; 895 MB ; 00:00:06 ;
-; TimeQuest Timing Analyzer ; 00:00:08 ; 1.1 ; 1213 MB ; 00:00:06 ;
-; Total ; 00:01:03 ; -- ; -- ; 00:01:36 ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Analysis & Synthesis ; eews104a-017 ; Windows 7 ; 6.1 ; x86_64 ;
-; Fitter ; eews104a-017 ; Windows 7 ; 6.1 ; x86_64 ;
-; Assembler ; eews104a-017 ; Windows 7 ; 6.1 ; x86_64 ;
-; TimeQuest Timing Analyzer ; eews104a-017 ; Windows 7 ; 6.1 ; x86_64 ;
-+---------------------------+------------------+-----------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
-quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9
-quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
-quartus_sta ex9 -c ex9
-
-
-
+Flow report for ex9
+Sun Dec 11 20:31:05 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+ 8. Flow Messages
+ 9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-------------------------------------------------------------------------------+
+; Flow Summary ;
++---------------------------------+---------------------------------------------+
+; Flow Status ; Successful - Sun Dec 11 20:30:59 2016 ;
+; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Revision Name ; ex9 ;
+; Top-level Entity Name ; ex9 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; 154 / 32,070 ( < 1 % ) ;
+; Total registers ; 94 ;
+; Total pins ; 57 / 457 ( 12 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 / 4,065,280 ( 0 % ) ;
+; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
++---------------------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 12/11/2016 20:30:05 ;
+; Main task ; Compilation ;
+; Revision Name ; ex9 ;
++-------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 158515234070422.148148820510331 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
+; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 1024 MB ; 00:00:24 ;
+; Fitter ; 00:00:36 ; 1.0 ; 2145 MB ; 00:01:04 ;
+; Assembler ; 00:00:06 ; 1.0 ; 979 MB ; 00:00:06 ;
+; TimeQuest Timing Analyzer ; 00:00:05 ; 1.2 ; 1216 MB ; 00:00:06 ;
+; Total ; 00:00:57 ; -- ; -- ; 00:01:40 ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++-----------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++---------------------------+------------------+------------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++---------------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
+; Fitter ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
+; Assembler ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
+; TimeQuest Timing Analyzer ; arch-desktop ; Arch Linux ; Arch Linux ; x86_64 ;
++---------------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
+quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9
+quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
+quartus_sta ex9 -c ex9
+
+
+
diff --git a/part_2/ex9/output_files/ex9.jdi b/part_2/ex9/output_files/ex9.jdi
index 63b9c30..6278af0 100644
--- a/part_2/ex9/output_files/ex9.jdi
+++ b/part_2/ex9/output_files/ex9.jdi
@@ -1,8 +1,8 @@
-<sld_project_info>
- <project>
- <hash md5_digest_80b="814875341ee80fb3b165"/>
- </project>
- <file_info>
- <file device="5CSEMA5F31C6" path="ex9.sof" usercode="0xFFFFFFFF"/>
- </file_info>
-</sld_project_info>
+<sld_project_info>
+ <project>
+ <hash md5_digest_80b="5235bbf031d88b76e07a"/>
+ </project>
+ <file_info>
+ <file device="5CSEMA5F31C6" path="ex9.sof" usercode="0xFFFFFFFF"/>
+ </file_info>
+</sld_project_info>
diff --git a/part_2/ex9/output_files/ex9.map.rpt b/part_2/ex9/output_files/ex9.map.rpt
index c0ed2ee..d47b4f5 100644
--- a/part_2/ex9/output_files/ex9.map.rpt
+++ b/part_2/ex9/output_files/ex9.map.rpt
@@ -1,615 +1,617 @@
-Analysis & Synthesis report for ex9
-Wed Dec 07 12:07:26 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. State Machine - |ex9|delay:DEL0|state
- 9. State Machine - |ex9|formula_fsm:FSM|state
- 10. User-Specified and Inferred Latches
- 11. Registers Removed During Synthesis
- 12. General Register Statistics
- 13. Inverted Register Statistics
- 14. Multiplexer Restructuring Statistics (Restructuring Performed)
- 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
- 16. Parameter Settings for User Entity Instance: formula_fsm:FSM
- 17. Parameter Settings for User Entity Instance: delay:DEL0
- 18. Parameter Settings for User Entity Instance: counter_16:COUNT0
- 19. Port Connectivity Checks: "hex_to_7seg:SEG5"
- 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
- 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
- 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
- 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
- 24. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
- 25. Port Connectivity Checks: "delay:DEL0"
- 26. Post-Synthesis Netlist Statistics for Top Partition
- 27. Elapsed Time Per Partition
- 28. Analysis & Synthesis Messages
- 29. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+---------------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Dec 07 12:07:26 2016 ;
-; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name ; ex9 ;
-; Top-level Entity Name ; ex9 ;
-; Family ; Cyclone V ;
-; Logic utilization (in ALMs) ; N/A ;
-; Total registers ; 84 ;
-; Total pins ; 57 ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 0 ;
-; Total DSP Blocks ; 0 ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 ;
-; Total DLLs ; 0 ;
-+---------------------------------+-------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Device ; 5CSEMA5F31C6 ; ;
-; Top-level entity name ; ex9 ; ex9 ;
-; Family name ; Cyclone V ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 3 ; 3 ;
-; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-; Synthesis Seed ; 1 ; 1 ;
-; Automatic Parallel Synthesis ; On ; On ;
-; Partial Reconfiguration Bitstream ID ; Off ; Off ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.0% ;
-; Processors 3-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
-; verilog_files/tick_50000.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v ; ;
-; verilog_files/LFSR.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v ; ;
-; verilog_files/hex_to_7seg.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v ; ;
-; verilog_files/formula_fsm.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v ; ;
-; verilog_files/delay.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v ; ;
-; verilog_files/counter_16.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v ; ;
-; verilog_files/bin2bcd_16.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v ; ;
-; verilog_files/add3_ge5.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v ; ;
-; verilog_files/ex9.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v ; ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
-
-
-+------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+--------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+--------------------------+
-; Estimate of Logic utilization (ALMs needed) ; 166 ;
-; ; ;
-; Combinational ALUT usage for logic ; 290 ;
-; -- 7 input functions ; 0 ;
-; -- 6 input functions ; 41 ;
-; -- 5 input functions ; 5 ;
-; -- 4 input functions ; 157 ;
-; -- <=3 input functions ; 87 ;
-; ; ;
-; Dedicated logic registers ; 84 ;
-; ; ;
-; I/O pins ; 57 ;
-; ; ;
-; Total DSP Blocks ; 0 ;
-; ; ;
-; Maximum fan-out node ; tick_50000:TICK0|CLK_OUT ;
-; Maximum fan-out ; 67 ;
-; Total fan-out ; 1423 ;
-; Average fan-out ; 2.92 ;
-+---------------------------------------------+--------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex9 ; 290 (1) ; 84 (0) ; 0 ; 0 ; 57 ; 0 ; |ex9 ; ex9 ; work ;
-; |LFSR:LFSR0| ; 3 (3) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |ex9|LFSR:LFSR0 ; LFSR ; work ;
-; |bin2bcd_16:BCD| ; 124 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD ; bin2bcd_16 ; work ;
-; |add3_ge5:A10| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5 ; work ;
-; |add3_ge5:A11| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5 ; work ;
-; |add3_ge5:A12| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5 ; work ;
-; |add3_ge5:A13| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5 ; work ;
-; |add3_ge5:A14| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5 ; work ;
-; |add3_ge5:A15| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5 ; work ;
-; |add3_ge5:A16| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5 ; work ;
-; |add3_ge5:A17| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5 ; work ;
-; |add3_ge5:A18| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5 ; work ;
-; |add3_ge5:A19| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5 ; work ;
-; |add3_ge5:A1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A1 ; add3_ge5 ; work ;
-; |add3_ge5:A20| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5 ; work ;
-; |add3_ge5:A21| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5 ; work ;
-; |add3_ge5:A22| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5 ; work ;
-; |add3_ge5:A23| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5 ; work ;
-; |add3_ge5:A24| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5 ; work ;
-; |add3_ge5:A25| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5 ; work ;
-; |add3_ge5:A26| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5 ; work ;
-; |add3_ge5:A27| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5 ; work ;
-; |add3_ge5:A28| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5 ; work ;
-; |add3_ge5:A29| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5 ; work ;
-; |add3_ge5:A2| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A2 ; add3_ge5 ; work ;
-; |add3_ge5:A30| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5 ; work ;
-; |add3_ge5:A32| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5 ; work ;
-; |add3_ge5:A33| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5 ; work ;
-; |add3_ge5:A34| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5 ; work ;
-; |add3_ge5:A35| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5 ; work ;
-; |add3_ge5:A3| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A3 ; add3_ge5 ; work ;
-; |add3_ge5:A4| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A4 ; add3_ge5 ; work ;
-; |add3_ge5:A5| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A5 ; add3_ge5 ; work ;
-; |add3_ge5:A6| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A6 ; add3_ge5 ; work ;
-; |add3_ge5:A7| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A7 ; add3_ge5 ; work ;
-; |add3_ge5:A8| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A8 ; add3_ge5 ; work ;
-; |add3_ge5:A9| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A9 ; add3_ge5 ; work ;
-; |counter_16:COUNT0| ; 17 (17) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex9|counter_16:COUNT0 ; counter_16 ; work ;
-; |delay:DEL0| ; 25 (25) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |ex9|delay:DEL0 ; delay ; work ;
-; |formula_fsm:FSM| ; 43 (43) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; |ex9|formula_fsm:FSM ; formula_fsm ; work ;
-; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG3 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG4| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG4 ; hex_to_7seg ; work ;
-; |tick_50000:TICK0| ; 36 (36) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex9|tick_50000:TICK0 ; tick_50000 ; work ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-Encoding Type: One-Hot
-+--------------------------------------------------------------------------------+
-; State Machine - |ex9|delay:DEL0|state ;
-+----------------+----------------+----------------+----------------+------------+
-; Name ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
-+----------------+----------------+----------------+----------------+------------+
-; state.IDLE ; 0 ; 0 ; 0 ; 0 ;
-; state.COUNTING ; 0 ; 0 ; 1 ; 1 ;
-; state.TIME_OUT ; 0 ; 1 ; 0 ; 1 ;
-; state.WAIT_LOW ; 1 ; 0 ; 0 ; 1 ;
-+----------------+----------------+----------------+----------------+------------+
-
-
-Encoding Type: One-Hot
-+--------------------------------------------------------------------------------------------+
-; State Machine - |ex9|formula_fsm:FSM|state ;
-+------------------------+--------------------+------------------------+---------------------+
-; Name ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
-+------------------------+--------------------+------------------------+---------------------+
-; state.WAIT_TRIGGER ; 0 ; 0 ; 0 ;
-; state.LIGHT_UP_LEDS ; 1 ; 0 ; 1 ;
-; state.WAIT_FOR_TIMEOUT ; 1 ; 1 ; 0 ;
-+------------------------+--------------------+------------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; User-Specified and Inferred Latches ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; formula_fsm:FSM|start_delay ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes ;
-; Number of user-specified and inferred latches = 1 ; ; ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
-
-
-+------------------------------------------------------------+
-; Registers Removed During Synthesis ;
-+---------------------------------------+--------------------+
-; Register name ; Reason for Removal ;
-+---------------------------------------+--------------------+
-; delay:DEL0|state~5 ; Lost fanout ;
-; delay:DEL0|state~6 ; Lost fanout ;
-; Total Number of Removed Registers = 2 ; ;
-+---------------------------------------+--------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 84 ;
-; Number of registers using Synchronous Clear ; 16 ;
-; Number of registers using Synchronous Load ; 15 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 42 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+---------------------------------------------------+
-; Inverted Register Statistics ;
-+-----------------------------------------+---------+
-; Inverted Register ; Fan out ;
-+-----------------------------------------+---------+
-; formula_fsm:FSM|count[1] ; 2 ;
-; formula_fsm:FSM|count[0] ; 2 ;
-; formula_fsm:FSM|count[6] ; 2 ;
-; formula_fsm:FSM|count[7] ; 2 ;
-; formula_fsm:FSM|count[8] ; 2 ;
-; formula_fsm:FSM|count[11] ; 2 ;
-; tick_50000:TICK0|count[14] ; 2 ;
-; tick_50000:TICK0|count[15] ; 2 ;
-; tick_50000:TICK0|count[0] ; 2 ;
-; tick_50000:TICK0|count[1] ; 2 ;
-; tick_50000:TICK0|count[2] ; 2 ;
-; tick_50000:TICK0|count[3] ; 2 ;
-; tick_50000:TICK0|count[6] ; 2 ;
-; tick_50000:TICK0|count[8] ; 2 ;
-; tick_50000:TICK0|count[9] ; 2 ;
-; LFSR:LFSR0|COUNT[1] ; 3 ;
-; Total number of inverted registers = 16 ; ;
-+-----------------------------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-; 3:1 ; 16 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |ex9|counter_16:COUNT0|count[0] ;
-; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex9|delay:DEL0|count[5] ;
-; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex9|delay:DEL0|count[13] ;
-; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |ex9|formula_fsm:FSM|count[0] ;
-; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |ex9|formula_fsm:FSM|Selector3 ;
-; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |ex9|delay:DEL0|Selector16 ;
-; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |ex9|delay:DEL0|Selector17 ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-
-
-+---------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
-+----------------+-------+--------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+--------------------------------------+
-; NBIT ; 16 ; Signed Integer ;
-+----------------+-------+--------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
-+------------------+-------+-----------------------------------+
-; Parameter Name ; Value ; Type ;
-+------------------+-------+-----------------------------------+
-; WAIT_TRIGGER ; 00 ; Unsigned Binary ;
-; LIGHT_UP_LEDS ; 01 ; Unsigned Binary ;
-; WAIT_FOR_TIMEOUT ; 10 ; Unsigned Binary ;
-+------------------+-------+-----------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------+
-; Parameter Settings for User Entity Instance: delay:DEL0 ;
-+----------------+-------+--------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+--------------------------------+
-; BIT_SZ ; 14 ; Signed Integer ;
-; IDLE ; 00 ; Unsigned Binary ;
-; COUNTING ; 01 ; Unsigned Binary ;
-; TIME_OUT ; 10 ; Unsigned Binary ;
-; WAIT_LOW ; 11 ; Unsigned Binary ;
-+----------------+-------+--------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: counter_16:COUNT0 ;
-+----------------+-------+---------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+---------------------------------------+
-; BIT_SZ ; 16 ; Signed Integer ;
-; COUNTING ; 1 ; Unsigned Binary ;
-; IDLE ; 0 ; Unsigned Binary ;
-+----------------+-------+---------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------+
-; Port Connectivity Checks: "hex_to_7seg:SEG5" ;
-+------+-------+----------+--------------------+
-; Port ; Type ; Severity ; Details ;
-+------+-------+----------+--------------------+
-; in ; Input ; Info ; Stuck at GND ;
-+------+-------+----------+--------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31" ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-; oA[3] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
-+-------+-------+----------+------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
-+-------+-------+----------+------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+------------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
-+-------+-------+----------+-----------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+-----------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
-+-------+-------+----------+-----------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+-----------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "delay:DEL0" ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; N ; Input ; Warning ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives. Extra input bit(s) "N[13..7]" will be connected to GND. ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; arriav_ff ; 84 ;
-; ENA ; 12 ;
-; ENA SCLR ; 16 ;
-; ENA SLD ; 14 ;
-; SLD ; 1 ;
-; plain ; 41 ;
-; arriav_lcell_comb ; 308 ;
-; arith ; 58 ;
-; 1 data inputs ; 58 ;
-; normal ; 250 ;
-; 0 data inputs ; 2 ;
-; 1 data inputs ; 28 ;
-; 2 data inputs ; 8 ;
-; 3 data inputs ; 9 ;
-; 4 data inputs ; 157 ;
-; 5 data inputs ; 5 ;
-; 6 data inputs ; 41 ;
-; boundary_port ; 57 ;
-; ; ;
-; Max LUT depth ; 15.00 ;
-; Average LUT depth ; 7.32 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:01 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
- Info: Processing started: Wed Dec 07 12:07:13 2016
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
- Info (12023): Found entity 1: tick_50000 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v
- Info (12023): Found entity 1: LFSR File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
- Info (12023): Found entity 1: hex_to_7seg File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
- Info (12023): Found entity 1: formula_fsm File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
- Info (12023): Found entity 1: delay File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
- Info (12023): Found entity 1: counter_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
- Info (12023): Found entity 1: bin2bcd_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 12
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
- Info (12023): Found entity 1: add3_ge5 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v Line: 9
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex9.v
- Info (12023): Found entity 1: ex9 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 1
-Info (12127): Elaborating entity "ex9" for the top level hierarchy
-Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 14
-Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 16
-Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 39
-Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 58
-Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 58
-Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 18
-Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 20
-Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 24
-Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:COUNT0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 22
-Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 24
-Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 26
-Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 26
-Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
-Warning (13024): Output pins are stuck at VCC or GND
- Warning (13410): Pin "HEX5[0]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
- Warning (13410): Pin "HEX5[1]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
- Warning (13410): Pin "HEX5[2]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
- Warning (13410): Pin "HEX5[3]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
- Warning (13410): Pin "HEX5[4]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
- Warning (13410): Pin "HEX5[5]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
- Warning (13410): Pin "HEX5[6]" is stuck at VCC File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
-Info (286030): Timing-Driven Synthesis is running
-Info (17049): 2 registers lost all their fanouts during netlist optimizations.
-Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 2 input pin(s) that do not drive logic
- Warning (15610): No output dependent on input pin "KEY[1]" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 4
- Warning (15610): No output dependent on input pin "KEY[2]" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 4
-Info (21057): Implemented 354 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 5 input pins
- Info (21059): Implemented 52 output pins
- Info (21061): Implemented 297 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
- Info: Peak virtual memory: 918 megabytes
- Info: Processing ended: Wed Dec 07 12:07:26 2016
- Info: Elapsed time: 00:00:13
- Info: Total CPU time (on all processors): 00:00:23
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg.
-
-
+Analysis & Synthesis report for ex9
+Sun Dec 11 20:30:15 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Source Files Read
+ 6. Analysis & Synthesis Resource Usage Summary
+ 7. Analysis & Synthesis Resource Utilization by Entity
+ 8. State Machine - |ex9|delay:DEL0|state
+ 9. State Machine - |ex9|formula_fsm:FSM|state
+ 10. User-Specified and Inferred Latches
+ 11. Registers Removed During Synthesis
+ 12. General Register Statistics
+ 13. Inverted Register Statistics
+ 14. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
+ 16. Parameter Settings for User Entity Instance: formula_fsm:FSM
+ 17. Parameter Settings for User Entity Instance: delay:DEL0
+ 18. Parameter Settings for User Entity Instance: counter_16:COUNT0
+ 19. Port Connectivity Checks: "hex_to_7seg:SEG5"
+ 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
+ 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
+ 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
+ 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
+ 24. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
+ 25. Port Connectivity Checks: "delay:DEL0"
+ 26. Post-Synthesis Netlist Statistics for Top Partition
+ 27. Elapsed Time Per Partition
+ 28. Analysis & Synthesis Messages
+ 29. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++---------------------------------+---------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Sun Dec 11 20:30:15 2016 ;
+; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Revision Name ; ex9 ;
+; Top-level Entity Name ; ex9 ;
+; Family ; Cyclone V ;
+; Logic utilization (in ALMs) ; N/A ;
+; Total registers ; 81 ;
+; Total pins ; 57 ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 ;
+; Total DSP Blocks ; 0 ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++---------------------------------+---------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Top-level entity name ; ex9 ; ex9 ;
+; Family name ; Cyclone V ; Cyclone V ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; OpenCore Plus hardware evaluation ; Enable ; Enable ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Infer RAMs from Raw Logic ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; On ; On ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 3 ; 3 ;
+; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
+; Automatic Parallel Synthesis ; On ; On ;
+; Partial Reconfiguration Bitstream ID ; Off ; Off ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.0% ;
+; Processors 3-4 ; 0.0% ;
++----------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
+; verilog_files/tick_50000.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/tick_50000.v ; ;
+; verilog_files/LFSR.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/LFSR.v ; ;
+; verilog_files/hex_to_7seg.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/hex_to_7seg.v ; ;
+; verilog_files/formula_fsm.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v ; ;
+; verilog_files/delay.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v ; ;
+; verilog_files/counter_16.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/counter_16.v ; ;
+; verilog_files/bin2bcd_16.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v ; ;
+; verilog_files/add3_ge5.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/add3_ge5.v ; ;
+; verilog_files/ex9.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v ; ;
++----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
+
+
++------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+--------------------------+
+; Resource ; Usage ;
++---------------------------------------------+--------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 160 ;
+; ; ;
+; Combinational ALUT usage for logic ; 281 ;
+; -- 7 input functions ; 2 ;
+; -- 6 input functions ; 35 ;
+; -- 5 input functions ; 5 ;
+; -- 4 input functions ; 154 ;
+; -- <=3 input functions ; 85 ;
+; ; ;
+; Dedicated logic registers ; 81 ;
+; ; ;
+; I/O pins ; 57 ;
+; ; ;
+; Total DSP Blocks ; 0 ;
+; ; ;
+; Maximum fan-out node ; tick_50000:TICK0|CLK_OUT ;
+; Maximum fan-out ; 64 ;
+; Total fan-out ; 1382 ;
+; Average fan-out ; 2.90 ;
++---------------------------------------------+--------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; |ex9 ; 281 (1) ; 81 (0) ; 0 ; 0 ; 57 ; 0 ; |ex9 ; ex9 ; work ;
+; |LFSR:LFSR0| ; 3 (3) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |ex9|LFSR:LFSR0 ; LFSR ; work ;
+; |bin2bcd_16:BCD| ; 123 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD ; bin2bcd_16 ; work ;
+; |add3_ge5:A10| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5 ; work ;
+; |add3_ge5:A11| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5 ; work ;
+; |add3_ge5:A12| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5 ; work ;
+; |add3_ge5:A13| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5 ; work ;
+; |add3_ge5:A14| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5 ; work ;
+; |add3_ge5:A15| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5 ; work ;
+; |add3_ge5:A16| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5 ; work ;
+; |add3_ge5:A17| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5 ; work ;
+; |add3_ge5:A18| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5 ; work ;
+; |add3_ge5:A19| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5 ; work ;
+; |add3_ge5:A1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A1 ; add3_ge5 ; work ;
+; |add3_ge5:A20| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5 ; work ;
+; |add3_ge5:A21| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5 ; work ;
+; |add3_ge5:A22| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5 ; work ;
+; |add3_ge5:A23| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5 ; work ;
+; |add3_ge5:A24| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5 ; work ;
+; |add3_ge5:A25| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5 ; work ;
+; |add3_ge5:A26| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5 ; work ;
+; |add3_ge5:A27| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5 ; work ;
+; |add3_ge5:A28| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5 ; work ;
+; |add3_ge5:A29| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5 ; work ;
+; |add3_ge5:A2| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A2 ; add3_ge5 ; work ;
+; |add3_ge5:A30| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5 ; work ;
+; |add3_ge5:A32| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5 ; work ;
+; |add3_ge5:A33| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5 ; work ;
+; |add3_ge5:A34| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5 ; work ;
+; |add3_ge5:A35| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5 ; work ;
+; |add3_ge5:A3| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A3 ; add3_ge5 ; work ;
+; |add3_ge5:A4| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A4 ; add3_ge5 ; work ;
+; |add3_ge5:A5| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A5 ; add3_ge5 ; work ;
+; |add3_ge5:A6| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A6 ; add3_ge5 ; work ;
+; |add3_ge5:A7| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A7 ; add3_ge5 ; work ;
+; |add3_ge5:A8| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A8 ; add3_ge5 ; work ;
+; |add3_ge5:A9| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|bin2bcd_16:BCD|add3_ge5:A9 ; add3_ge5 ; work ;
+; |counter_16:COUNT0| ; 17 (17) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex9|counter_16:COUNT0 ; counter_16 ; work ;
+; |delay:DEL0| ; 23 (23) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |ex9|delay:DEL0 ; delay ; work ;
+; |formula_fsm:FSM| ; 37 (37) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |ex9|formula_fsm:FSM ; formula_fsm ; work ;
+; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG3 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG4| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex9|hex_to_7seg:SEG4 ; hex_to_7seg ; work ;
+; |tick_50000:TICK0| ; 36 (36) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex9|tick_50000:TICK0 ; tick_50000 ; work ;
++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
+Encoding Type: One-Hot
++--------------------------------------------------------------------------------+
+; State Machine - |ex9|delay:DEL0|state ;
++----------------+----------------+----------------+----------------+------------+
+; Name ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
++----------------+----------------+----------------+----------------+------------+
+; state.IDLE ; 0 ; 0 ; 0 ; 0 ;
+; state.COUNTING ; 0 ; 0 ; 1 ; 1 ;
+; state.TIME_OUT ; 0 ; 1 ; 0 ; 1 ;
+; state.WAIT_LOW ; 1 ; 0 ; 0 ; 1 ;
++----------------+----------------+----------------+----------------+------------+
+
+
+Encoding Type: One-Hot
++--------------------------------------------------------------------------------------------+
+; State Machine - |ex9|formula_fsm:FSM|state ;
++------------------------+--------------------+------------------------+---------------------+
+; Name ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
++------------------------+--------------------+------------------------+---------------------+
+; state.WAIT_TRIGGER ; 0 ; 0 ; 0 ;
+; state.LIGHT_UP_LEDS ; 1 ; 0 ; 1 ;
+; state.WAIT_FOR_TIMEOUT ; 1 ; 1 ; 0 ;
++------------------------+--------------------+------------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; User-Specified and Inferred Latches ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; formula_fsm:FSM|start_delay ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes ;
+; Number of user-specified and inferred latches = 1 ; ; ;
++----------------------------------------------------+-------------------------------------+------------------------+
+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+
+
++------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++---------------------------------------+--------------------+
+; Register name ; Reason for Removal ;
++---------------------------------------+--------------------+
+; delay:DEL0|state~5 ; Lost fanout ;
+; delay:DEL0|state~6 ; Lost fanout ;
+; Total Number of Removed Registers = 2 ; ;
++---------------------------------------+--------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 81 ;
+; Number of registers using Synchronous Clear ; 16 ;
+; Number of registers using Synchronous Load ; 15 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 43 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++---------------------------------------------------+
+; Inverted Register Statistics ;
++-----------------------------------------+---------+
+; Inverted Register ; Fan out ;
++-----------------------------------------+---------+
+; formula_fsm:FSM|count[1] ; 2 ;
+; formula_fsm:FSM|count[0] ; 2 ;
+; formula_fsm:FSM|count[4] ; 2 ;
+; formula_fsm:FSM|count[5] ; 2 ;
+; formula_fsm:FSM|count[6] ; 2 ;
+; formula_fsm:FSM|count[7] ; 2 ;
+; formula_fsm:FSM|count[8] ; 2 ;
+; tick_50000:TICK0|count[14] ; 2 ;
+; tick_50000:TICK0|count[15] ; 2 ;
+; tick_50000:TICK0|count[0] ; 2 ;
+; tick_50000:TICK0|count[1] ; 2 ;
+; tick_50000:TICK0|count[2] ; 2 ;
+; tick_50000:TICK0|count[3] ; 2 ;
+; tick_50000:TICK0|count[6] ; 2 ;
+; tick_50000:TICK0|count[8] ; 2 ;
+; tick_50000:TICK0|count[9] ; 2 ;
+; LFSR:LFSR0|COUNT[1] ; 3 ;
+; Total number of inverted registers = 17 ; ;
++-----------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+; 3:1 ; 16 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |ex9|counter_16:COUNT0|count[7] ;
+; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex9|delay:DEL0|count[1] ;
+; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex9|delay:DEL0|count[13] ;
+; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |ex9|formula_fsm:FSM|count[1] ;
+; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |ex9|formula_fsm:FSM|Selector4 ;
+; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |ex9|delay:DEL0|Selector16 ;
+; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |ex9|delay:DEL0|Selector17 ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+
+
++---------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
++----------------+-------+--------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------------+
+; NBIT ; 16 ; Signed Integer ;
++----------------+-------+--------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
++------------------+-------+-----------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------+-------+-----------------------------------+
+; WAIT_TRIGGER ; 00 ; Unsigned Binary ;
+; LIGHT_UP_LEDS ; 01 ; Unsigned Binary ;
+; WAIT_FOR_TIMEOUT ; 10 ; Unsigned Binary ;
++------------------+-------+-----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------+
+; Parameter Settings for User Entity Instance: delay:DEL0 ;
++----------------+-------+--------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------+
+; BIT_SZ ; 14 ; Signed Integer ;
+; IDLE ; 00 ; Unsigned Binary ;
+; COUNTING ; 01 ; Unsigned Binary ;
+; TIME_OUT ; 10 ; Unsigned Binary ;
+; WAIT_LOW ; 11 ; Unsigned Binary ;
++----------------+-------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: counter_16:COUNT0 ;
++----------------+-------+---------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+---------------------------------------+
+; BIT_SZ ; 16 ; Signed Integer ;
+; COUNTING ; 1 ; Unsigned Binary ;
+; IDLE ; 0 ; Unsigned Binary ;
++----------------+-------+---------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------+
+; Port Connectivity Checks: "hex_to_7seg:SEG5" ;
++------+-------+----------+--------------------+
+; Port ; Type ; Severity ; Details ;
++------+-------+----------+--------------------+
+; in ; Input ; Info ; Stuck at GND ;
++------+-------+----------+--------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31" ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
+; oA[3] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
++-------+-------+----------+------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
++-------+-------+----------+------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
++-------+-------+----------+-----------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+-----------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
++-------+-------+----------+-----------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+-----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "delay:DEL0" ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; N ; Input ; Warning ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives. Extra input bit(s) "N[13..7]" will be connected to GND. ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type ; Count ;
++-----------------------+-----------------------------+
+; arriav_ff ; 81 ;
+; ENA ; 13 ;
+; ENA SCLR ; 16 ;
+; ENA SLD ; 14 ;
+; SLD ; 1 ;
+; plain ; 37 ;
+; arriav_lcell_comb ; 299 ;
+; arith ; 55 ;
+; 1 data inputs ; 55 ;
+; extend ; 2 ;
+; 7 data inputs ; 2 ;
+; normal ; 242 ;
+; 0 data inputs ; 2 ;
+; 1 data inputs ; 28 ;
+; 2 data inputs ; 7 ;
+; 3 data inputs ; 11 ;
+; 4 data inputs ; 154 ;
+; 5 data inputs ; 5 ;
+; 6 data inputs ; 35 ;
+; boundary_port ; 57 ;
+; ; ;
+; Max LUT depth ; 15.00 ;
+; Average LUT depth ; 7.46 ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top ; 00:00:00 ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+ Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+ Info: Processing started: Sun Dec 11 20:30:05 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
+ Info (12023): Found entity 1: tick_50000 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/tick_50000.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/LFSR.v
+ Info (12023): Found entity 1: LFSR File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/LFSR.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+ Info (12023): Found entity 1: hex_to_7seg File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
+ Info (12023): Found entity 1: formula_fsm File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
+ Info (12023): Found entity 1: delay File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
+ Info (12023): Found entity 1: counter_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/counter_16.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+ Info (12023): Found entity 1: bin2bcd_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+ Info (12023): Found entity 1: add3_ge5 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/add3_ge5.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex9.v
+ Info (12023): Found entity 1: ex9 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 1
+Info (12127): Elaborating entity "ex9" for the top level hierarchy
+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 14
+Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 16
+Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v Line: 39
+Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v Line: 58
+Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v Line: 58
+Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 18
+Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 20
+Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v Line: 24
+Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:COUNT0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 22
+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 24
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 26
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 26
+Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+ Warning (13410): Pin "HEX5[0]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
+ Warning (13410): Pin "HEX5[1]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
+ Warning (13410): Pin "HEX5[2]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
+ Warning (13410): Pin "HEX5[3]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
+ Warning (13410): Pin "HEX5[4]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
+ Warning (13410): Pin "HEX5[5]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
+ Warning (13410): Pin "HEX5[6]" is stuck at VCC File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 2 registers lost all their fanouts during netlist optimizations.
+Info (144001): Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+ Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 2 input pin(s) that do not drive logic
+ Warning (15610): No output dependent on input pin "KEY[1]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 4
+ Warning (15610): No output dependent on input pin "KEY[2]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 4
+Info (21057): Implemented 345 device resources after synthesis - the final resource count might be different
+ Info (21058): Implemented 5 input pins
+ Info (21059): Implemented 52 output pins
+ Info (21061): Implemented 288 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
+ Info: Peak virtual memory: 1067 megabytes
+ Info: Processing ended: Sun Dec 11 20:30:15 2016
+ Info: Elapsed time: 00:00:10
+ Info: Total CPU time (on all processors): 00:00:25
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.map.smsg.
+
+
diff --git a/part_2/ex9/output_files/ex9.map.smsg b/part_2/ex9/output_files/ex9.map.smsg
index f6657db..d9920c4 100644
--- a/part_2/ex9/output_files/ex9.map.smsg
+++ b/part_2/ex9/output_files/ex9.map.smsg
@@ -1,37 +1,37 @@
-Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 38
-Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 7
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v Line: 38
+Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
diff --git a/part_2/ex9/output_files/ex9.map.summary b/part_2/ex9/output_files/ex9.map.summary
index e668523..0cf8b66 100644
--- a/part_2/ex9/output_files/ex9.map.summary
+++ b/part_2/ex9/output_files/ex9.map.summary
@@ -1,17 +1,17 @@
-Analysis & Synthesis Status : Successful - Wed Dec 07 12:07:26 2016
-Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex9
-Top-level Entity Name : ex9
-Family : Cyclone V
-Logic utilization (in ALMs) : N/A
-Total registers : 84
-Total pins : 57
-Total virtual pins : 0
-Total block memory bits : 0
-Total DSP Blocks : 0
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0
-Total DLLs : 0
+Analysis & Synthesis Status : Successful - Sun Dec 11 20:30:15 2016
+Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+Revision Name : ex9
+Top-level Entity Name : ex9
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 81
+Total pins : 57
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_2/ex9/output_files/ex9.pin b/part_2/ex9/output_files/ex9.pin
index 6b2c6db..2ad3820 100644
--- a/part_2/ex9/output_files/ex9.pin
+++ b/part_2/ex9/output_files/ex9.pin
@@ -1,976 +1,977 @@
- -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
- -- Your use of Altera Corporation's design tools, logic functions
- -- and other software and tools, and its AMPP partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Altera Program License
- -- Subscription Agreement, the Altera Quartus Prime License Agreement,
- -- the Altera MegaCore Function License Agreement, or other
- -- applicable license agreement, including, without limitation,
- -- that your use is for the sole purpose of programming logic
- -- devices manufactured by Altera and sold by Altera or its
- -- authorized distributors. Please refer to the applicable
- -- agreement for further details.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 3A: 2.5V
- -- Bank 3B: 3.3V
- -- Bank 4A: 3.3V
- -- Bank 5A: 3.3V
- -- Bank 5B: 3.3V
- -- Bank 6B: 2.5V
- -- Bank 6A: 2.5V
- -- Bank 7A: 2.5V
- -- Bank 7B: 2.5V
- -- Bank 7C: 2.5V
- -- Bank 7D: 2.5V
- -- Bank 8A: 2.5V
- -- RREF : External reference resistor for the quad, MUST be connected to
- -- GND via a 2k Ohm resistor.
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
- -- must not be connected.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-CHIP "ex9" ASSIGNED TO AN: 5CSEMA5F31C6
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND : A2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A :
-VCCIO8A : A7 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A :
-GND : A12 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C :
-GND : A17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B :
-GND : A22 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A :
-GND : A26 : : : : 7A :
-GND : A27 : gnd : : : :
-HPS_TRST : A28 : : : : 7A :
-HPS_TMS : A29 : : : : 7A :
-GND : AA1 : gnd : : : :
-GND : AA2 : gnd : : : :
-GND : AA3 : gnd : : : :
-GND : AA4 : gnd : : : :
-VCC : AA5 : power : : 1.1V : :
-GND : AA6 : gnd : : : :
-DNU : AA7 : : : : :
-VCCA_FPLL : AA8 : power : : 2.5V : :
-GND : AA9 : gnd : : : :
-VCCPD3A : AA10 : power : : 2.5V : 3A :
-GND : AA11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3B :
-KEY[0] : AA14 : input : 3.3-V LVTTL : : 3B : Y
-KEY[1] : AA15 : input : 3.3-V LVTTL : : 3B : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
-VCCIO4A : AA17 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
-GND : AA22 : gnd : : : :
-VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : :
-HEX4[0] : AA24 : output : 3.3-V LVTTL : : 5A : Y
-HEX5[6] : AA25 : output : 3.3-V LVTTL : : 5A : Y
-HEX5[5] : AA26 : output : 3.3-V LVTTL : : 5B : Y
-VCCIO5B : AA27 : power : : 3.3V : 5B :
-HEX5[1] : AA28 : output : 3.3-V LVTTL : : 5B : Y
-VREFB5BN0 : AA29 : power : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B :
-GND : AB1 : gnd : : : :
-GND : AB2 : gnd : : : :
-DNU : AB3 : : : : :
-DNU : AB4 : : : : :
-GND : AB5 : gnd : : : :
-VCCA_FPLL : AB6 : power : : 2.5V : :
-GND : AB7 : gnd : : : :
-nCSO, DATA4 : AB8 : : : : 3A :
-TDO : AB9 : output : : : 3A :
-VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : :
-VCC_AUX : AB11 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B :
-VCCIO3B : AB14 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B :
-VCC_AUX : AB16 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
-VCCPD3B4A : AB18 : power : : 3.3V : 3B, 4A :
-GND : AB19 : gnd : : : :
-VCCPD3B4A : AB20 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A :
-HEX3[6] : AB22 : output : 3.3-V LVTTL : : 5A : Y
-HEX2[0] : AB23 : output : 3.3-V LVTTL : : 5A : Y
-VCCIO5A : AB24 : power : : 3.3V : 5A :
-HEX3[5] : AB25 : output : 3.3-V LVTTL : : 5A : Y
-HEX5[4] : AB26 : output : 3.3-V LVTTL : : 5A : Y
-HEX5[3] : AB27 : output : 3.3-V LVTTL : : 5B : Y
-HEX3[4] : AB28 : output : 3.3-V LVTTL : : 5B : Y
-GND : AB29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B :
-GND : AC1 : gnd : : : :
-GND : AC2 : gnd : : : :
-GND : AC3 : gnd : : : :
-GND : AC4 : gnd : : : :
-TCK : AC5 : input : : : 3A :
-GND : AC6 : gnd : : : :
-AS_DATA3, DATA3 : AC7 : : : : 3A :
-GND : AC8 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3A :
-VCCPD3A : AC10 : power : : 2.5V : 3A :
-VCCIO3A : AC11 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3A :
-VCCPD3B4A : AC13 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3B :
-VCCPD3B4A : AC15 : power : : 3.3V : 3B, 4A :
-GND : AC16 : gnd : : : :
-VCCPD3B4A : AC17 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
-VCCPD3B4A : AC19 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
-VCCIO4A : AC21 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
-VREFB5AN0 : AC24 : power : : : 5A :
-HEX3[3] : AC25 : output : 3.3-V LVTTL : : 5A : Y
-GND : AC26 : gnd : : : :
-HEX3[1] : AC27 : output : 3.3-V LVTTL : : 5A : Y
-HEX2[3] : AC28 : output : 3.3-V LVTTL : : 5B : Y
-HEX2[5] : AC29 : output : 3.3-V LVTTL : : 5B : Y
-HEX2[6] : AC30 : output : 3.3-V LVTTL : : 5B : Y
-GND : AD1 : gnd : : : :
-GND : AD2 : gnd : : : :
-DNU : AD3 : : : : :
-DNU : AD4 : : : : :
-GND : AD5 : gnd : : : :
-VREFB3AN0 : AD6 : power : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
-VCCIO3A : AD8 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3A :
-VCCIO3B : AD13 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B :
-DNU : AD15 : : : : :
-VCCPD3B4A : AD16 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
-VCCIO4A : AD18 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
-VCC_AUX : AD22 : power : : 2.5V : :
-GND : AD23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A :
-HEX3[2] : AD25 : output : 3.3-V LVTTL : : 5A : Y
-HEX3[0] : AD26 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[6] : AD27 : output : 3.3-V LVTTL : : 5A : Y
-VCCIO5A : AD28 : power : : 3.3V : 5A :
-HEX2[2] : AD29 : output : 3.3-V LVTTL : : 5B : Y
-HEX2[4] : AD30 : output : 3.3-V LVTTL : : 5B : Y
-GND : AE1 : gnd : : : :
-GND : AE2 : gnd : : : :
-GND : AE3 : gnd : : : :
-GND : AE4 : gnd : : : :
-AS_DATA1, DATA1 : AE5 : : : : 3A :
-AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3A :
-AS_DATA2, DATA2 : AE8 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3A :
-GND : AE10 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B :
-VCCIO3B : AE15 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
-GND : AE20 : gnd : : : :
-VCCPD3B4A : AE21 : power : : 3.3V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
-VCCIO4A : AE25 : power : : 3.3V : 4A :
-HEX0[0] : AE26 : output : 3.3-V LVTTL : : 5A : Y
-HEX0[1] : AE27 : output : 3.3-V LVTTL : : 5A : Y
-HEX0[2] : AE28 : output : 3.3-V LVTTL : : 5A : Y
-HEX2[1] : AE29 : output : 3.3-V LVTTL : : 5B : Y
-VCCIO5B : AE30 : power : : 3.3V : 5B :
-GND : AF1 : gnd : : : :
-GND : AF2 : gnd : : : :
-GND : AF3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A :
-VCCIO3A : AF7 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
-GND : AF12 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B :
-CLOCK_50 : AF14 : input : 3.3-V LVTTL : : 3B : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
-GND : AF17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
-VCCIO4A : AF22 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A :
-GND : AF27 : gnd : : : :
-HEX0[4] : AF28 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[4] : AF29 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[5] : AF30 : output : 3.3-V LVTTL : : 5A : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A :
-VCCIO3A : AG4 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3A :
-GND : AG9 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B :
-GND : AG14 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
-VCCIO4A : AG19 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
-HEX0[3] : AG27 : output : 3.3-V LVTTL : : 5A : Y
-HEX0[5] : AG28 : output : 3.3-V LVTTL : : 5A : Y
-VCCIO5A : AG29 : power : : 3.3V : 5A :
-HEX1[3] : AG30 : output : 3.3-V LVTTL : : 5A : Y
-GND : AH1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A :
-GND : AH6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3B :
-GND : AH11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH15 : : : : 3B :
-VCCIO4A : AH16 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A :
-GND : AH21 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4A :
-VCCIO4A : AH26 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
-HEX0[6] : AH28 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[1] : AH29 : output : 3.3-V LVTTL : : 5A : Y
-HEX1[2] : AH30 : output : 3.3-V LVTTL : : 5A : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2 : : : : 3A :
-GND : AJ3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B :
-VCCIO3B : AJ8 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B :
-VCCIO3B : AJ13 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B :
-VREFB3BN0 : AJ15 : power : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A :
-GND : AJ18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 4A :
-VCCIO4A : AJ23 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A :
-GND : AJ28 : gnd : : : :
-HEX1[0] : AJ29 : output : 3.3-V LVTTL : : 5A : Y
-GND : AJ30 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK4 : : : : 3B :
-GND : AK5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B :
-VCCIO3B : AK10 : power : : 3.3V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B :
-GND : AK15 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A :
-VREFB4AN0 : AK17 : power : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A :
-VCCIO4A : AK20 : power : : 3.3V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A :
-GND : AK25 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK29 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A :
-VCCIO8A : B4 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A :
-GND : B9 : gnd : : : :
-VREFB8AN0 : B10 : power : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A :
-GND : B14 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B :
-GND : B19 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A :
-HPS_TDI : B27 : : : : 7A :
-HPS_TDO : B28 : : : : 7A :
-GND : B29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A :
-GND : C6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A :
-VCCIO8A : C11 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D :
-GND : C16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B :
-GND : C21 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A :
-GND : C26 : gnd : : : :
-HPS_nRST : C27 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A :
-GND : D3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
-VCCIO8A : D8 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
-GND : D13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C :
-VCCIO7C_HPS : D18 : power : : 2.5V : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A :
-GND : D23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A :
-HPS_CLK1 : D25 : : : : 7A :
-GND : D26 : : : : 7A :
-HPS_RZQ_0 : D27 : : : : 6A :
-VCCIO6A_HPS : D28 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A :
-VCCIO8A : E5 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
-GND : E10 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D :
-VCCIO7D_HPS : E15 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B :
-VCCIO7B_HPS : E20 : power : : 2.5V : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B :
-VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A :
-GND : E25 : gnd : : : :
-DNU : E26 : : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A :
-GND : E30 : gnd : : : :
-DNU : F1 : : : : :
-GND : F2 : gnd : : : :
-CONF_DONE : F3 : : : : 9A :
-nSTATUS : F4 : : : : 9A :
-GND : F5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
-GND : F7 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A :
-VCCIO8A : F12 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D :
-GND : F17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B :
-VCCIO7A_HPS : F22 : power : : 2.5V : 7A :
-HPS_nPOR : F23 : : : : 7A :
-HPS_PORSEL : F24 : : : : 7A :
-HPS_CLK2 : F25 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
-GND : F27 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A :
-GND : G1 : : : : :
-DNU : G2 : : : : :
-GND : G3 : gnd : : : :
-GND : G4 : gnd : : : :
-nCE : G5 : : : : 9A :
-MSEL2 : G6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8A :
-VCCIO8A : G9 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A :
-VCCIO8A : G14 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C :
-VCCIO7B_HPS : G19 : power : : 2.5V : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A :
-VCCRSTCLK_HPS : G23 : : : : 7A :
-GND : G24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
-VCCIO6A_HPS : G29 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A :
-GND : H1 : gnd : : : :
-GND : H2 : gnd : : : :
-DNU : H3 : : : : :
-DNU : H4 : : : : :
-GND : H5 : gnd : : : :
-VCCIO8A : H6 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
-VCCBAT : H9 : power : : 1.2V : :
-VCC_AUX : H10 : power : : 2.5V : :
-GND : H11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A :
-VCCIO7D_HPS : H16 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A :
-VCCIO7A_HPS : H21 : power : : 2.5V : 7A :
-HPS_TCK : H22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
-VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A :
-GND : J1 : gnd : : : :
-GND : J2 : gnd : : : :
-GND : J3 : gnd : : : :
-GND : J4 : gnd : : : :
-nCONFIG : J5 : : : : 9A :
-GND : J6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
-GND : J8 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
-VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A :
-VCCIO8A : J13 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8A :
-DNU : J15 : : : : :
-VCC_AUX : J16 : power : : 2.5V : :
-VCCPD7C_HPS : J17 : power : : 2.5V : 7C :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B :
-VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : :
-VCC_AUX_SHARED : J21 : power : : 2.5V : :
-GND : J22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
-GND : J28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A :
-GND : K1 : gnd : : : :
-GND : K2 : gnd : : : :
-DNU : K3 : : : : :
-DNU : K4 : : : : :
-GND : K5 : gnd : : : :
-MSEL1 : K6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
-VCCA_FPLL : K9 : power : : 2.5V : :
-GND : K10 : gnd : : : :
-VCCPD8A : K11 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 8A :
-VCCPD8A : K13 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A :
-GND : K15 : gnd : : : :
-VCCPD7D_HPS : K16 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B :
-VCCPD7B_HPS : K18 : power : : 2.5V : 7B :
-VCCPD7A_HPS : K19 : power : : 2.5V : 7A :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
-VCCIO6A_HPS : K24 : power : : 2.5V : 6A :
-GND : K25 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A :
-VCCIO6A_HPS : K30 : power : : 2.5V : 6A :
-GND : L1 : gnd : : : :
-GND : L2 : gnd : : : :
-GND : L3 : gnd : : : :
-GND : L4 : gnd : : : :
-VCC : L5 : power : : 1.1V : :
-GND : L6 : gnd : : : :
-MSEL3 : L7 : : : : 9A :
-MSEL0 : L8 : : : : 9A :
-MSEL4 : L9 : : : : 9A :
-VCCPD8A : L10 : power : : 2.5V : 8A :
-GND : L11 : gnd : : : :
-VCCPD8A : L12 : power : : 2.5V : 8A :
-GND : L13 : gnd : : : :
-VCCPD8A : L14 : power : : 2.5V : 8A :
-GND : L15 : gnd : : : :
-VCC_HPS : L16 : power : : 1.1V : :
-GND : L17 : gnd : : : :
-VCC_HPS : L18 : power : : 1.1V : :
-GND : L19 : gnd : : : :
-VCC_HPS : L20 : power : : 1.1V : :
-VCCPLL_HPS : L21 : power : : 2.5V : :
-GND : L22 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A :
-VCCIO6A_HPS : L27 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A :
-GND : M1 : gnd : : : :
-GND : M2 : gnd : : : :
-DNU : M3 : : : : :
-DNU : M4 : : : : :
-GND : M5 : gnd : : : :
-VCC : M6 : power : : 1.1V : :
-GND : M7 : gnd : : : :
-GND : M8 : gnd : : : :
-VCC : M9 : power : : 1.1V : :
-GND : M10 : gnd : : : :
-VCC : M11 : power : : 1.1V : :
-GND : M12 : gnd : : : :
-VCC : M13 : power : : 1.1V : :
-GND : M14 : gnd : : : :
-VCC_HPS : M15 : power : : 1.1V : :
-GND : M16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D :
-GND : M18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A :
-GND : M20 : gnd : : : :
-VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A :
-VCCIO6A_HPS : M24 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
-GND : M29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A :
-GND : N1 : gnd : : : :
-GND : N2 : gnd : : : :
-GND : N3 : gnd : : : :
-GND : N4 : gnd : : : :
-VCC : N5 : power : : 1.1V : :
-GND : N6 : gnd : : : :
-VCCA_FPLL : N7 : power : : 2.5V : :
-GND : N8 : gnd : : : :
-GND : N9 : gnd : : : :
-VCC : N10 : power : : 1.1V : :
-GND : N11 : gnd : : : :
-VCC : N12 : power : : 1.1V : :
-GND : N13 : gnd : : : :
-VCC : N14 : power : : 1.1V : :
-GND : N15 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D :
-GND : N17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A :
-GND : N19 : gnd : : : :
-VCC_HPS : N20 : power : : 1.1V : :
-VCCIO6A_HPS : N21 : power : : 2.5V : 6A :
-VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A :
-GND : N26 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B :
-GND : P1 : gnd : : : :
-GND : P2 : gnd : : : :
-DNU : P3 : : : : :
-DNU : P4 : : : : :
-GND : P5 : gnd : : : :
-VCCA_FPLL : P6 : power : : 2.5V : :
-GND : P7 : gnd : : : :
-GND : P8 : gnd : : : :
-GND : P9 : gnd : : : :
-GND : P10 : gnd : : : :
-VCC : P11 : power : : 1.1V : :
-GND : P12 : gnd : : : :
-VCC : P13 : power : : 1.1V : :
-GND : P14 : gnd : : : :
-VCC_HPS : P15 : power : : 1.1V : :
-GND : P16 : gnd : : : :
-VCC_HPS : P17 : power : : 1.1V : :
-GND : P18 : gnd : : : :
-VCC_HPS : P19 : power : : 1.1V : :
-GND : P20 : gnd : : : :
-VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B :
-VCCIO6B_HPS : P23 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B :
-VCCIO6B_HPS : P28 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B :
-GND : R1 : gnd : : : :
-GND : R2 : gnd : : : :
-GND : R3 : gnd : : : :
-GND : R4 : gnd : : : :
-VCC : R5 : power : : 1.1V : :
-GND : R6 : gnd : : : :
-VCCA_FPLL : R7 : power : : 2.5V : :
-GND : R8 : gnd : : : :
-GND : R9 : gnd : : : :
-VCC : R10 : power : : 1.1V : :
-GND : R11 : gnd : : : :
-VCC : R12 : power : : 1.1V : :
-GND : R13 : gnd : : : :
-VCC : R14 : power : : 1.1V : :
-GND : R15 : gnd : : : :
-VCC_HPS : R16 : power : : 1.1V : :
-GND : R17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B :
-VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B :
-VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
-VCCIO6B_HPS : R25 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B :
-GND : R30 : gnd : : : :
-GND : T1 : gnd : : : :
-GND : T2 : gnd : : : :
-DNU : T3 : : : : :
-DNU : T4 : : : : :
-GND : T5 : gnd : : : :
-VCC : T6 : power : : 1.1V : :
-GND : T7 : gnd : : : :
-GND : T8 : gnd : : : :
-GND : T9 : gnd : : : :
-GND : T10 : gnd : : : :
-VCC : T11 : power : : 1.1V : :
-GND : T12 : gnd : : : :
-VCC : T13 : power : : 1.1V : :
-GND : T14 : gnd : : : :
-GND : T15 : gnd : : : :
-GND : T16 : gnd : : : :
-VCC_HPS : T17 : power : : 1.1V : :
-GND : T18 : gnd : : : :
-VCC_HPS : T19 : power : : 1.1V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B :
-VCCIO6B_HPS : T22 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
-GND : T27 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B :
-GND : U1 : gnd : : : :
-GND : U2 : gnd : : : :
-GND : U3 : gnd : : : :
-GND : U4 : gnd : : : :
-VCC : U5 : power : : 1.1V : :
-GND : U6 : gnd : : : :
-DCLK : U7 : : : : 3A :
-TDI : U8 : input : : : 3A :
-GND : U9 : gnd : : : :
-VCC : U10 : power : : 1.1V : :
-GND : U11 : gnd : : : :
-VCC : U12 : power : : 1.1V : :
-GND : U13 : gnd : : : :
-VCC : U14 : power : : 1.1V : :
-GND : U15 : gnd : : : :
-VCC_HPS : U16 : power : : 1.1V : :
-GND : U17 : gnd : : : :
-VCC_HPS : U18 : power : : 1.1V : :
-VCCIO6B_HPS : U19 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B :
-VCC : U21 : power : : 1.1V : :
-GND : U22 : gnd : : : :
-VCCPD5B : U23 : power : : 3.3V : 5B :
-GND : U24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
-GND : U29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B :
-GND : V1 : gnd : : : :
-GND : V2 : gnd : : : :
-DNU : V3 : : : : :
-DNU : V4 : : : : :
-GND : V5 : gnd : : : :
-VCCA_FPLL : V6 : power : : 2.5V : :
-GND : V7 : gnd : : : :
-VCCA_FPLL : V8 : power : : 2.5V : :
-TMS : V9 : input : : : 3A :
-GND : V10 : gnd : : : :
-VCC : V11 : power : : 1.1V : :
-GND : V12 : gnd : : : :
-VCC : V13 : power : : 1.1V : :
-GND : V14 : gnd : : : :
-VCC : V15 : power : : 1.1V : :
-LEDR[0] : V16 : output : 3.3-V LVTTL : : 4A : Y
-LEDR[2] : V17 : output : 3.3-V LVTTL : : 4A : Y
-LEDR[3] : V18 : output : 3.3-V LVTTL : : 4A : Y
-GND : V19 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
-GND : V21 : gnd : : : :
-VCCPD5A : V22 : power : : 3.3V : 5A :
-HEX4[5] : V23 : output : 3.3-V LVTTL : : 5A : Y
-VCCPD5A : V24 : power : : 3.3V : 5A :
-HEX5[0] : V25 : output : 3.3-V LVTTL : : 5B : Y
-VCCIO6B_HPS : V26 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B :
-GND : W1 : gnd : : : :
-GND : W2 : gnd : : : :
-GND : W3 : gnd : : : :
-GND : W4 : gnd : : : :
-VCC : W5 : power : : 1.1V : :
-GND : W6 : gnd : : : :
-GND : W7 : gnd : : : :
-GND : W8 : gnd : : : :
-GND : W9 : gnd : : : :
-VCC : W10 : power : : 1.1V : :
-GND : W11 : gnd : : : :
-VCC : W12 : power : : 1.1V : :
-GND : W13 : gnd : : : :
-VCC : W14 : power : : 1.1V : :
-KEY[2] : W15 : input : 3.3-V LVTTL : : 3B : Y
-LEDR[1] : W16 : output : 3.3-V LVTTL : : 4A : Y
-LEDR[4] : W17 : output : 3.3-V LVTTL : : 4A : Y
-GND : W18 : gnd : : : :
-LEDR[5] : W19 : output : 3.3-V LVTTL : : 4A : Y
-LEDR[7] : W20 : output : 3.3-V LVTTL : : 5A : Y
-LEDR[8] : W21 : output : 3.3-V LVTTL : : 5A : Y
-HEX4[3] : W22 : output : 3.3-V LVTTL : : 5A : Y
-VCCIO5A : W23 : power : : 3.3V : 5A :
-HEX4[4] : W24 : output : 3.3-V LVTTL : : 5A : Y
-HEX4[6] : W25 : output : 3.3-V LVTTL : : 5B : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B :
-GND : W28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B :
-GND : Y1 : gnd : : : :
-GND : Y2 : gnd : : : :
-DNU : Y3 : : : : :
-DNU : Y4 : : : : :
-GND : Y5 : gnd : : : :
-VCC : Y6 : power : : 1.1V : :
-GND : Y7 : gnd : : : :
-GND : Y8 : gnd : : : :
-VCC : Y9 : power : : 1.1V : :
-GND : Y10 : gnd : : : :
-VCC : Y11 : power : : 1.1V : :
-GND : Y12 : gnd : : : :
-VCC : Y13 : power : : 1.1V : :
-GND : Y14 : gnd : : : :
-GND : Y15 : gnd : : : :
-KEY[3] : Y16 : input : 3.3-V LVTTL : : 3B : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
-LEDR[6] : Y19 : output : 3.3-V LVTTL : : 4A : Y
-GND : Y20 : gnd : : : :
-LEDR[9] : Y21 : output : 3.3-V LVTTL : : 5A : Y
-VCCA_FPLL : Y22 : power : : 2.5V : :
-HEX4[1] : Y23 : output : 3.3-V LVTTL : : 5A : Y
-HEX4[2] : Y24 : output : 3.3-V LVTTL : : 5A : Y
-GND : Y25 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
-HEX5[2] : Y27 : output : 3.3-V LVTTL : : 5B : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B :
-GND : Y30 : gnd : : : :
+ -- Copyright (C) 2016 Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Intel Program License
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel MegaCore Function License Agreement, or other
+ -- applicable license agreement, including, without limitation,
+ -- that your use is for the sole purpose of programming logic
+ -- devices manufactured by Intel and sold by Intel or its
+ -- authorized distributors. Please refer to the applicable
+ -- agreement for further details.
+ --
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 3A: 2.5V
+ -- Bank 3B: 3.3V
+ -- Bank 4A: 3.3V
+ -- Bank 5A: 3.3V
+ -- Bank 5B: 3.3V
+ -- Bank 6B: 2.5V
+ -- Bank 6A: 2.5V
+ -- Bank 7A: 2.5V
+ -- Bank 7B: 2.5V
+ -- Bank 7C: 2.5V
+ -- Bank 7D: 2.5V
+ -- Bank 8A: 2.5V
+ -- Bank 9A: Dedicated configuration pins only, no VCCIO required.
+ -- RREF : External reference resistor for the quad, MUST be connected to
+ -- GND via a 2k Ohm resistor.
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
+ -- must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+CHIP "ex9" ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A :
+VCCIO8A : A7 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A :
+GND : A12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C :
+GND : A17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B :
+GND : A22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A :
+GND : A26 : : : : 7A :
+GND : A27 : gnd : : : :
+HPS_TRST : A28 : : : : 7A :
+HPS_TMS : A29 : : : : 7A :
+GND : AA1 : gnd : : : :
+GND : AA2 : gnd : : : :
+GND : AA3 : gnd : : : :
+GND : AA4 : gnd : : : :
+VCC : AA5 : power : : 1.1V : :
+GND : AA6 : gnd : : : :
+DNU : AA7 : : : : :
+VCCA_FPLL : AA8 : power : : 2.5V : :
+GND : AA9 : gnd : : : :
+VCCPD3A : AA10 : power : : 2.5V : 3A :
+GND : AA11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3B :
+KEY[0] : AA14 : input : 3.3-V LVTTL : : 3B : Y
+KEY[1] : AA15 : input : 3.3-V LVTTL : : 3B : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
+VCCIO4A : AA17 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
+GND : AA22 : gnd : : : :
+VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : :
+HEX4[0] : AA24 : output : 3.3-V LVTTL : : 5A : Y
+HEX5[6] : AA25 : output : 3.3-V LVTTL : : 5A : Y
+HEX5[5] : AA26 : output : 3.3-V LVTTL : : 5B : Y
+VCCIO5B : AA27 : power : : 3.3V : 5B :
+HEX5[1] : AA28 : output : 3.3-V LVTTL : : 5B : Y
+VREFB5BN0 : AA29 : power : : : 5B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B :
+GND : AB1 : gnd : : : :
+GND : AB2 : gnd : : : :
+DNU : AB3 : : : : :
+DNU : AB4 : : : : :
+GND : AB5 : gnd : : : :
+VCCA_FPLL : AB6 : power : : 2.5V : :
+GND : AB7 : gnd : : : :
+nCSO, DATA4 : AB8 : : : : 3A :
+TDO : AB9 : output : : : 3A :
+VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX : AB11 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B :
+VCCIO3B : AB14 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B :
+VCC_AUX : AB16 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
+VCCPD3B4A : AB18 : power : : 3.3V : 3B, 4A :
+GND : AB19 : gnd : : : :
+VCCPD3B4A : AB20 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A :
+HEX3[6] : AB22 : output : 3.3-V LVTTL : : 5A : Y
+HEX2[0] : AB23 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AB24 : power : : 3.3V : 5A :
+HEX3[5] : AB25 : output : 3.3-V LVTTL : : 5A : Y
+HEX5[4] : AB26 : output : 3.3-V LVTTL : : 5A : Y
+HEX5[3] : AB27 : output : 3.3-V LVTTL : : 5B : Y
+HEX3[4] : AB28 : output : 3.3-V LVTTL : : 5B : Y
+GND : AB29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B :
+GND : AC1 : gnd : : : :
+GND : AC2 : gnd : : : :
+GND : AC3 : gnd : : : :
+GND : AC4 : gnd : : : :
+TCK : AC5 : input : : : 3A :
+GND : AC6 : gnd : : : :
+AS_DATA3, DATA3 : AC7 : : : : 3A :
+GND : AC8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3A :
+VCCPD3A : AC10 : power : : 2.5V : 3A :
+VCCIO3A : AC11 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3A :
+VCCPD3B4A : AC13 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3B :
+VCCPD3B4A : AC15 : power : : 3.3V : 3B, 4A :
+GND : AC16 : gnd : : : :
+VCCPD3B4A : AC17 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
+VCCPD3B4A : AC19 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
+VCCIO4A : AC21 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
+VREFB5AN0 : AC24 : power : : : 5A :
+HEX3[3] : AC25 : output : 3.3-V LVTTL : : 5A : Y
+GND : AC26 : gnd : : : :
+HEX3[1] : AC27 : output : 3.3-V LVTTL : : 5A : Y
+HEX2[3] : AC28 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[5] : AC29 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[6] : AC30 : output : 3.3-V LVTTL : : 5B : Y
+GND : AD1 : gnd : : : :
+GND : AD2 : gnd : : : :
+DNU : AD3 : : : : :
+DNU : AD4 : : : : :
+GND : AD5 : gnd : : : :
+VREFB3AN0 : AD6 : power : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
+VCCIO3A : AD8 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3A :
+VCCIO3B : AD13 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B :
+DNU : AD15 : : : : :
+VCCPD3B4A : AD16 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
+VCCIO4A : AD18 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
+VCC_AUX : AD22 : power : : 2.5V : :
+GND : AD23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A :
+HEX3[2] : AD25 : output : 3.3-V LVTTL : : 5A : Y
+HEX3[0] : AD26 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[6] : AD27 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AD28 : power : : 3.3V : 5A :
+HEX2[2] : AD29 : output : 3.3-V LVTTL : : 5B : Y
+HEX2[4] : AD30 : output : 3.3-V LVTTL : : 5B : Y
+GND : AE1 : gnd : : : :
+GND : AE2 : gnd : : : :
+GND : AE3 : gnd : : : :
+GND : AE4 : gnd : : : :
+AS_DATA1, DATA1 : AE5 : : : : 3A :
+AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3A :
+AS_DATA2, DATA2 : AE8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3A :
+GND : AE10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B :
+VCCIO3B : AE15 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
+GND : AE20 : gnd : : : :
+VCCPD3B4A : AE21 : power : : 3.3V : 3B, 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
+VCCIO4A : AE25 : power : : 3.3V : 4A :
+HEX0[0] : AE26 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[1] : AE27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[2] : AE28 : output : 3.3-V LVTTL : : 5A : Y
+HEX2[1] : AE29 : output : 3.3-V LVTTL : : 5B : Y
+VCCIO5B : AE30 : power : : 3.3V : 5B :
+GND : AF1 : gnd : : : :
+GND : AF2 : gnd : : : :
+GND : AF3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A :
+VCCIO3A : AF7 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
+GND : AF12 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B :
+CLOCK_50 : AF14 : input : 3.3-V LVTTL : : 3B : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
+GND : AF17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
+VCCIO4A : AF22 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A :
+GND : AF27 : gnd : : : :
+HEX0[4] : AF28 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[4] : AF29 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[5] : AF30 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A :
+VCCIO3A : AG4 : power : : 2.5V : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3A :
+GND : AG9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B :
+GND : AG14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
+VCCIO4A : AG19 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
+GND : AG24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
+HEX0[3] : AG27 : output : 3.3-V LVTTL : : 5A : Y
+HEX0[5] : AG28 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : AG29 : power : : 3.3V : 5A :
+HEX1[3] : AG30 : output : 3.3-V LVTTL : : 5A : Y
+GND : AH1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A :
+GND : AH6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3B :
+GND : AH11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15 : : : : 3B :
+VCCIO4A : AH16 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A :
+GND : AH21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4A :
+VCCIO4A : AH26 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
+HEX0[6] : AH28 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[1] : AH29 : output : 3.3-V LVTTL : : 5A : Y
+HEX1[2] : AH30 : output : 3.3-V LVTTL : : 5A : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2 : : : : 3A :
+GND : AJ3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B :
+VCCIO3B : AJ8 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B :
+VCCIO3B : AJ13 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B :
+VREFB3BN0 : AJ15 : power : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A :
+GND : AJ18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 4A :
+VCCIO4A : AJ23 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A :
+GND : AJ28 : gnd : : : :
+HEX1[0] : AJ29 : output : 3.3-V LVTTL : : 5A : Y
+GND : AJ30 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4 : : : : 3B :
+GND : AK5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B :
+VCCIO3B : AK10 : power : : 3.3V : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B :
+GND : AK15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A :
+VREFB4AN0 : AK17 : power : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A :
+VCCIO4A : AK20 : power : : 3.3V : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A :
+GND : AK25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A :
+VCCIO8A : B4 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A :
+GND : B9 : gnd : : : :
+VREFB8AN0 : B10 : power : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A :
+GND : B14 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B :
+GND : B19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A :
+GND : B24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A :
+HPS_TDI : B27 : : : : 7A :
+HPS_TDO : B28 : : : : 7A :
+GND : B29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A :
+GND : C1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A :
+GND : C6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A :
+VCCIO8A : C11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D :
+GND : C16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B :
+GND : C21 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A :
+GND : C26 : gnd : : : :
+HPS_nRST : C27 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A :
+GND : D3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
+VCCIO8A : D8 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
+GND : D13 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C :
+VCCIO7C_HPS : D18 : power : : 2.5V : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A :
+GND : D23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A :
+HPS_CLK1 : D25 : : : : 7A :
+GND : D26 : : : : 7A :
+HPS_RZQ_0 : D27 : : : : 6A :
+VCCIO6A_HPS : D28 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A :
+VCCIO8A : E5 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
+GND : E10 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D :
+VCCIO7D_HPS : E15 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B :
+VCCIO7B_HPS : E20 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B :
+VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A :
+GND : E25 : gnd : : : :
+DNU : E26 : : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A :
+GND : E30 : gnd : : : :
+DNU : F1 : : : : :
+GND : F2 : gnd : : : :
+CONF_DONE : F3 : : : : 9A :
+nSTATUS : F4 : : : : 9A :
+GND : F5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
+GND : F7 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A :
+VCCIO8A : F12 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D :
+GND : F17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B :
+VCCIO7A_HPS : F22 : power : : 2.5V : 7A :
+HPS_nPOR : F23 : : : : 7A :
+HPS_PORSEL : F24 : : : : 7A :
+HPS_CLK2 : F25 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
+GND : F27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A :
+GND : G1 : : : : :
+DNU : G2 : : : : :
+GND : G3 : gnd : : : :
+GND : G4 : gnd : : : :
+nCE : G5 : : : : 9A :
+MSEL2 : G6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8A :
+VCCIO8A : G9 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A :
+VCCIO8A : G14 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C :
+VCCIO7B_HPS : G19 : power : : 2.5V : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A :
+VCCRSTCLK_HPS : G23 : : : : 7A :
+GND : G24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
+VCCIO6A_HPS : G29 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A :
+GND : H1 : gnd : : : :
+GND : H2 : gnd : : : :
+DNU : H3 : : : : :
+DNU : H4 : : : : :
+GND : H5 : gnd : : : :
+VCCIO8A : H6 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
+VCCBAT : H9 : power : : 1.2V : :
+VCC_AUX : H10 : power : : 2.5V : :
+GND : H11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A :
+VCCIO7D_HPS : H16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A :
+VCCIO7A_HPS : H21 : power : : 2.5V : 7A :
+HPS_TCK : H22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
+VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A :
+GND : J1 : gnd : : : :
+GND : J2 : gnd : : : :
+GND : J3 : gnd : : : :
+GND : J4 : gnd : : : :
+nCONFIG : J5 : : : : 9A :
+GND : J6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
+GND : J8 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
+VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A :
+VCCIO8A : J13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8A :
+DNU : J15 : : : : :
+VCC_AUX : J16 : power : : 2.5V : :
+VCCPD7C_HPS : J17 : power : : 2.5V : 7C :
+GND : J18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B :
+VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : :
+VCC_AUX_SHARED : J21 : power : : 2.5V : :
+GND : J22 : : : : 7A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
+GND : J28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A :
+GND : K1 : gnd : : : :
+GND : K2 : gnd : : : :
+DNU : K3 : : : : :
+DNU : K4 : : : : :
+GND : K5 : gnd : : : :
+MSEL1 : K6 : : : : 9A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
+VCCA_FPLL : K9 : power : : 2.5V : :
+GND : K10 : gnd : : : :
+VCCPD8A : K11 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 8A :
+VCCPD8A : K13 : power : : 2.5V : 8A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A :
+GND : K15 : gnd : : : :
+VCCPD7D_HPS : K16 : power : : 2.5V : 7D :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B :
+VCCPD7B_HPS : K18 : power : : 2.5V : 7B :
+VCCPD7A_HPS : K19 : power : : 2.5V : 7A :
+GND : K20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
+VCCIO6A_HPS : K24 : power : : 2.5V : 6A :
+GND : K25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A :
+VCCIO6A_HPS : K30 : power : : 2.5V : 6A :
+GND : L1 : gnd : : : :
+GND : L2 : gnd : : : :
+GND : L3 : gnd : : : :
+GND : L4 : gnd : : : :
+VCC : L5 : power : : 1.1V : :
+GND : L6 : gnd : : : :
+MSEL3 : L7 : : : : 9A :
+MSEL0 : L8 : : : : 9A :
+MSEL4 : L9 : : : : 9A :
+VCCPD8A : L10 : power : : 2.5V : 8A :
+GND : L11 : gnd : : : :
+VCCPD8A : L12 : power : : 2.5V : 8A :
+GND : L13 : gnd : : : :
+VCCPD8A : L14 : power : : 2.5V : 8A :
+GND : L15 : gnd : : : :
+VCC_HPS : L16 : power : : 1.1V : :
+GND : L17 : gnd : : : :
+VCC_HPS : L18 : power : : 1.1V : :
+GND : L19 : gnd : : : :
+VCC_HPS : L20 : power : : 1.1V : :
+VCCPLL_HPS : L21 : power : : 2.5V : :
+GND : L22 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A :
+VCCIO6A_HPS : L27 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A :
+GND : M1 : gnd : : : :
+GND : M2 : gnd : : : :
+DNU : M3 : : : : :
+DNU : M4 : : : : :
+GND : M5 : gnd : : : :
+VCC : M6 : power : : 1.1V : :
+GND : M7 : gnd : : : :
+GND : M8 : gnd : : : :
+VCC : M9 : power : : 1.1V : :
+GND : M10 : gnd : : : :
+VCC : M11 : power : : 1.1V : :
+GND : M12 : gnd : : : :
+VCC : M13 : power : : 1.1V : :
+GND : M14 : gnd : : : :
+VCC_HPS : M15 : power : : 1.1V : :
+GND : M16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D :
+GND : M18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A :
+GND : M20 : gnd : : : :
+VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A :
+VCCIO6A_HPS : M24 : power : : 2.5V : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
+GND : M29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A :
+GND : N1 : gnd : : : :
+GND : N2 : gnd : : : :
+GND : N3 : gnd : : : :
+GND : N4 : gnd : : : :
+VCC : N5 : power : : 1.1V : :
+GND : N6 : gnd : : : :
+VCCA_FPLL : N7 : power : : 2.5V : :
+GND : N8 : gnd : : : :
+GND : N9 : gnd : : : :
+VCC : N10 : power : : 1.1V : :
+GND : N11 : gnd : : : :
+VCC : N12 : power : : 1.1V : :
+GND : N13 : gnd : : : :
+VCC : N14 : power : : 1.1V : :
+GND : N15 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D :
+GND : N17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A :
+GND : N19 : gnd : : : :
+VCC_HPS : N20 : power : : 1.1V : :
+VCCIO6A_HPS : N21 : power : : 2.5V : 6A :
+VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A :
+GND : N26 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B :
+GND : P1 : gnd : : : :
+GND : P2 : gnd : : : :
+DNU : P3 : : : : :
+DNU : P4 : : : : :
+GND : P5 : gnd : : : :
+VCCA_FPLL : P6 : power : : 2.5V : :
+GND : P7 : gnd : : : :
+GND : P8 : gnd : : : :
+GND : P9 : gnd : : : :
+GND : P10 : gnd : : : :
+VCC : P11 : power : : 1.1V : :
+GND : P12 : gnd : : : :
+VCC : P13 : power : : 1.1V : :
+GND : P14 : gnd : : : :
+VCC_HPS : P15 : power : : 1.1V : :
+GND : P16 : gnd : : : :
+VCC_HPS : P17 : power : : 1.1V : :
+GND : P18 : gnd : : : :
+VCC_HPS : P19 : power : : 1.1V : :
+GND : P20 : gnd : : : :
+VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B :
+VCCIO6B_HPS : P23 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B :
+VCCIO6B_HPS : P28 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B :
+GND : R1 : gnd : : : :
+GND : R2 : gnd : : : :
+GND : R3 : gnd : : : :
+GND : R4 : gnd : : : :
+VCC : R5 : power : : 1.1V : :
+GND : R6 : gnd : : : :
+VCCA_FPLL : R7 : power : : 2.5V : :
+GND : R8 : gnd : : : :
+GND : R9 : gnd : : : :
+VCC : R10 : power : : 1.1V : :
+GND : R11 : gnd : : : :
+VCC : R12 : power : : 1.1V : :
+GND : R13 : gnd : : : :
+VCC : R14 : power : : 1.1V : :
+GND : R15 : gnd : : : :
+VCC_HPS : R16 : power : : 1.1V : :
+GND : R17 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B :
+VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B :
+VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
+VCCIO6B_HPS : R25 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B :
+GND : R30 : gnd : : : :
+GND : T1 : gnd : : : :
+GND : T2 : gnd : : : :
+DNU : T3 : : : : :
+DNU : T4 : : : : :
+GND : T5 : gnd : : : :
+VCC : T6 : power : : 1.1V : :
+GND : T7 : gnd : : : :
+GND : T8 : gnd : : : :
+GND : T9 : gnd : : : :
+GND : T10 : gnd : : : :
+VCC : T11 : power : : 1.1V : :
+GND : T12 : gnd : : : :
+VCC : T13 : power : : 1.1V : :
+GND : T14 : gnd : : : :
+GND : T15 : gnd : : : :
+GND : T16 : gnd : : : :
+VCC_HPS : T17 : power : : 1.1V : :
+GND : T18 : gnd : : : :
+VCC_HPS : T19 : power : : 1.1V : :
+GND : T20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B :
+VCCIO6B_HPS : T22 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
+GND : T27 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B :
+GND : U1 : gnd : : : :
+GND : U2 : gnd : : : :
+GND : U3 : gnd : : : :
+GND : U4 : gnd : : : :
+VCC : U5 : power : : 1.1V : :
+GND : U6 : gnd : : : :
+DCLK : U7 : : : : 3A :
+TDI : U8 : input : : : 3A :
+GND : U9 : gnd : : : :
+VCC : U10 : power : : 1.1V : :
+GND : U11 : gnd : : : :
+VCC : U12 : power : : 1.1V : :
+GND : U13 : gnd : : : :
+VCC : U14 : power : : 1.1V : :
+GND : U15 : gnd : : : :
+VCC_HPS : U16 : power : : 1.1V : :
+GND : U17 : gnd : : : :
+VCC_HPS : U18 : power : : 1.1V : :
+VCCIO6B_HPS : U19 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B :
+VCC : U21 : power : : 1.1V : :
+GND : U22 : gnd : : : :
+VCCPD5B : U23 : power : : 3.3V : 5B :
+GND : U24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
+GND : U29 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B :
+GND : V1 : gnd : : : :
+GND : V2 : gnd : : : :
+DNU : V3 : : : : :
+DNU : V4 : : : : :
+GND : V5 : gnd : : : :
+VCCA_FPLL : V6 : power : : 2.5V : :
+GND : V7 : gnd : : : :
+VCCA_FPLL : V8 : power : : 2.5V : :
+TMS : V9 : input : : : 3A :
+GND : V10 : gnd : : : :
+VCC : V11 : power : : 1.1V : :
+GND : V12 : gnd : : : :
+VCC : V13 : power : : 1.1V : :
+GND : V14 : gnd : : : :
+VCC : V15 : power : : 1.1V : :
+LEDR[0] : V16 : output : 3.3-V LVTTL : : 4A : Y
+LEDR[2] : V17 : output : 3.3-V LVTTL : : 4A : Y
+LEDR[3] : V18 : output : 3.3-V LVTTL : : 4A : Y
+GND : V19 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
+GND : V21 : gnd : : : :
+VCCPD5A : V22 : power : : 3.3V : 5A :
+HEX4[5] : V23 : output : 3.3-V LVTTL : : 5A : Y
+VCCPD5A : V24 : power : : 3.3V : 5A :
+HEX5[0] : V25 : output : 3.3-V LVTTL : : 5B : Y
+VCCIO6B_HPS : V26 : power : : 2.5V : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B :
+GND : W1 : gnd : : : :
+GND : W2 : gnd : : : :
+GND : W3 : gnd : : : :
+GND : W4 : gnd : : : :
+VCC : W5 : power : : 1.1V : :
+GND : W6 : gnd : : : :
+GND : W7 : gnd : : : :
+GND : W8 : gnd : : : :
+GND : W9 : gnd : : : :
+VCC : W10 : power : : 1.1V : :
+GND : W11 : gnd : : : :
+VCC : W12 : power : : 1.1V : :
+GND : W13 : gnd : : : :
+VCC : W14 : power : : 1.1V : :
+KEY[2] : W15 : input : 3.3-V LVTTL : : 3B : Y
+LEDR[1] : W16 : output : 3.3-V LVTTL : : 4A : Y
+LEDR[4] : W17 : output : 3.3-V LVTTL : : 4A : Y
+GND : W18 : gnd : : : :
+LEDR[5] : W19 : output : 3.3-V LVTTL : : 4A : Y
+LEDR[7] : W20 : output : 3.3-V LVTTL : : 5A : Y
+LEDR[8] : W21 : output : 3.3-V LVTTL : : 5A : Y
+HEX4[3] : W22 : output : 3.3-V LVTTL : : 5A : Y
+VCCIO5A : W23 : power : : 3.3V : 5A :
+HEX4[4] : W24 : output : 3.3-V LVTTL : : 5A : Y
+HEX4[6] : W25 : output : 3.3-V LVTTL : : 5B : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B :
+GND : W28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B :
+GND : Y1 : gnd : : : :
+GND : Y2 : gnd : : : :
+DNU : Y3 : : : : :
+DNU : Y4 : : : : :
+GND : Y5 : gnd : : : :
+VCC : Y6 : power : : 1.1V : :
+GND : Y7 : gnd : : : :
+GND : Y8 : gnd : : : :
+VCC : Y9 : power : : 1.1V : :
+GND : Y10 : gnd : : : :
+VCC : Y11 : power : : 1.1V : :
+GND : Y12 : gnd : : : :
+VCC : Y13 : power : : 1.1V : :
+GND : Y14 : gnd : : : :
+GND : Y15 : gnd : : : :
+KEY[3] : Y16 : input : 3.3-V LVTTL : : 3B : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4A :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
+LEDR[6] : Y19 : output : 3.3-V LVTTL : : 4A : Y
+GND : Y20 : gnd : : : :
+LEDR[9] : Y21 : output : 3.3-V LVTTL : : 5A : Y
+VCCA_FPLL : Y22 : power : : 2.5V : :
+HEX4[1] : Y23 : output : 3.3-V LVTTL : : 5A : Y
+HEX4[2] : Y24 : output : 3.3-V LVTTL : : 5A : Y
+GND : Y25 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
+HEX5[2] : Y27 : output : 3.3-V LVTTL : : 5B : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B :
+GND : Y30 : gnd : : : :
diff --git a/part_2/ex9/output_files/ex9.sld b/part_2/ex9/output_files/ex9.sld
index 41a6030..f7d3ed7 100644
--- a/part_2/ex9/output_files/ex9.sld
+++ b/part_2/ex9/output_files/ex9.sld
@@ -1 +1 @@
-<sld_project_info/>
+<sld_project_info/>
diff --git a/part_2/ex9/output_files/ex9.sof b/part_2/ex9/output_files/ex9.sof
index 8d40e59..227b29f 100644
--- a/part_2/ex9/output_files/ex9.sof
+++ b/part_2/ex9/output_files/ex9.sof
Binary files differ
diff --git a/part_2/ex9/output_files/ex9.sta.rpt b/part_2/ex9/output_files/ex9.sta.rpt
index 1c3b355..8331403 100644
--- a/part_2/ex9/output_files/ex9.sta.rpt
+++ b/part_2/ex9/output_files/ex9.sta.rpt
@@ -1,1005 +1,1005 @@
-TimeQuest Timing Analyzer report for ex9
-Wed Dec 07 12:08:30 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. TimeQuest Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1100mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1100mV 85C Model Setup Summary
- 8. Slow 1100mV 85C Model Hold Summary
- 9. Slow 1100mV 85C Model Recovery Summary
- 10. Slow 1100mV 85C Model Removal Summary
- 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1100mV 85C Model Metastability Summary
- 13. Slow 1100mV 0C Model Fmax Summary
- 14. Slow 1100mV 0C Model Setup Summary
- 15. Slow 1100mV 0C Model Hold Summary
- 16. Slow 1100mV 0C Model Recovery Summary
- 17. Slow 1100mV 0C Model Removal Summary
- 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1100mV 0C Model Metastability Summary
- 20. Fast 1100mV 85C Model Setup Summary
- 21. Fast 1100mV 85C Model Hold Summary
- 22. Fast 1100mV 85C Model Recovery Summary
- 23. Fast 1100mV 85C Model Removal Summary
- 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
- 25. Fast 1100mV 85C Model Metastability Summary
- 26. Fast 1100mV 0C Model Setup Summary
- 27. Fast 1100mV 0C Model Hold Summary
- 28. Fast 1100mV 0C Model Recovery Summary
- 29. Fast 1100mV 0C Model Removal Summary
- 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
- 31. Fast 1100mV 0C Model Metastability Summary
- 32. Multicorner Timing Analysis Summary
- 33. Board Trace Model Assignments
- 34. Input Transition Times
- 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
- 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
- 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
- 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
- 39. Setup Transfers
- 40. Hold Transfers
- 41. Report TCCS
- 42. Report RSKM
- 43. Unconstrained Paths Summary
- 44. Clock Status Summary
- 45. Unconstrained Input Ports
- 46. Unconstrained Output Ports
- 47. Unconstrained Input Ports
- 48. Unconstrained Output Ports
- 49. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary ;
-+-----------------------+---------------------------------------------------------+
-; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Timing Analyzer ; TimeQuest ;
-; Revision Name ; ex9 ;
-; Device Family ; Cyclone V ;
-; Device Name ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+---------------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.10 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 3.3% ;
-; Processor 3 ; 3.3% ;
-; Processor 4 ; 3.2% ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; CLOCK_50 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
-; tick_50000:TICK0|CLK_OUT ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { tick_50000:TICK0|CLK_OUT } ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-
-
-+----------------------------------------------------------------+
-; Slow 1100mV 85C Model Fmax Summary ;
-+------------+-----------------+--------------------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+--------------------------+------+
-; 224.11 MHz ; 224.11 MHz ; tick_50000:TICK0|CLK_OUT ; ;
-; 328.19 MHz ; 328.19 MHz ; CLOCK_50 ; ;
-+------------+-----------------+--------------------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Setup Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT ; -3.462 ; -161.413 ;
-; CLOCK_50 ; -2.047 ; -40.775 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675 ; -1.675 ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Slow 1100mV 85C Model Hold Summary ;
-+-------------------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT ; 0.179 ; 0.000 ;
-; CLOCK_50 ; 0.385 ; 0.000 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.629 ; 0.000 ;
-+-------------------------------------+-------+---------------+
-
-
-------------------------------------------
-; Slow 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50 ; -0.637 ; -18.132 ;
-; tick_50000:TICK0|CLK_OUT ; -0.394 ; -38.762 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.459 ; 0.000 ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------------
-; Slow 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------+
-; Slow 1100mV 0C Model Fmax Summary ;
-+------------+-----------------+--------------------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+--------------------------+------+
-; 226.45 MHz ; 226.45 MHz ; tick_50000:TICK0|CLK_OUT ; ;
-; 300.93 MHz ; 300.93 MHz ; CLOCK_50 ; ;
-+------------+-----------------+--------------------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Setup Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT ; -3.416 ; -157.230 ;
-; CLOCK_50 ; -2.323 ; -41.799 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.568 ; -1.568 ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Slow 1100mV 0C Model Hold Summary ;
-+-------------------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT ; 0.193 ; 0.000 ;
-; CLOCK_50 ; 0.405 ; 0.000 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.501 ; 0.000 ;
-+-------------------------------------+-------+---------------+
-
-
------------------------------------------
-; Slow 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50 ; -0.689 ; -16.816 ;
-; tick_50000:TICK0|CLK_OUT ; -0.394 ; -38.286 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.412 ; 0.000 ;
-+-------------------------------------+--------+---------------+
-
-
-----------------------------------------------
-; Slow 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Setup Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT ; -1.794 ; -79.872 ;
-; CLOCK_50 ; -0.918 ; -13.912 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.572 ; -0.572 ;
-+-------------------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Hold Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT ; -0.020 ; -0.037 ;
-; CLOCK_50 ; 0.185 ; 0.000 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.202 ; 0.000 ;
-+-------------------------------------+--------+---------------+
-
-
-------------------------------------------
-; Fast 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50 ; -0.740 ; -12.957 ;
-; tick_50000:TICK0|CLK_OUT ; -0.012 ; -0.190 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.478 ; 0.000 ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------------
-; Fast 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Setup Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT ; -1.581 ; -69.264 ;
-; CLOCK_50 ; -0.868 ; -11.639 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.462 ; -0.462 ;
-+-------------------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Hold Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT ; -0.021 ; -0.052 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.122 ; 0.000 ;
-; CLOCK_50 ; 0.177 ; 0.000 ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------
-; Fast 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
-+-------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50 ; -0.789 ; -15.486 ;
-; tick_50000:TICK0|CLK_OUT ; 0.024 ; 0.000 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.468 ; 0.000 ;
-+-------------------------------------+--------+---------------+
-
-
-----------------------------------------------
-; Fast 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-; Worst-case Slack ; -3.462 ; -0.021 ; N/A ; N/A ; -0.789 ;
-; CLOCK_50 ; -2.323 ; 0.177 ; N/A ; N/A ; -0.789 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675 ; 0.122 ; N/A ; N/A ; 0.412 ;
-; tick_50000:TICK0|CLK_OUT ; -3.462 ; -0.021 ; N/A ; N/A ; -0.394 ;
-; Design-wide TNS ; -203.863 ; -0.052 ; 0.0 ; 0.0 ; -56.894 ;
-; CLOCK_50 ; -41.799 ; 0.000 ; N/A ; N/A ; -18.132 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675 ; 0.000 ; N/A ; N/A ; 0.000 ;
-; tick_50000:TICK0|CLK_OUT ; -161.413 ; -0.052 ; N/A ; N/A ; -38.762 ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX4[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX5[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX5[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX5[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX5[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX5[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX5[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX5[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+-------------------------------------------------------------+
-; Input Transition Times ;
-+----------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+----------+--------------+-----------------+-----------------+
-; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; KEY[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; KEY[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-+----------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
-; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
-; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
-; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
-; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
-; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
-; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
-; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
-; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
-; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Setup Transfers ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 416 ; 0 ; 0 ; 0 ;
-; tick_50000:TICK0|CLK_OUT ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1 ; 0 ; 0 ; 0 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 43 ; 25 ; 0 ; 0 ;
-; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 1042 ; 0 ; 0 ; 0 ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Hold Transfers ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 416 ; 0 ; 0 ; 0 ;
-; tick_50000:TICK0|CLK_OUT ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1 ; 0 ; 0 ; 0 ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 43 ; 25 ; 0 ; 0 ;
-; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 1042 ; 0 ; 0 ; 0 ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 2 ; 2 ;
-; Unconstrained Input Port Paths ; 20 ; 20 ;
-; Unconstrained Output Ports ; 45 ; 45 ;
-; Unconstrained Output Port Paths ; 500 ; 500 ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Clock Status Summary ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; Target ; Clock ; Type ; Status ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
-; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; Base ; Constrained ;
-+-------------------------------------+-------------------------------------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime TimeQuest Timing Analyzer
- Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
- Info: Processing started: Wed Dec 07 12:08:21 2016
-Info: Command: quartus_sta ex9 -c ex9
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
- Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
- Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
- Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1100mV 85C Model
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.462
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.462 -161.413 tick_50000:TICK0|CLK_OUT
- Info (332119): -2.047 -40.775 CLOCK_50
- Info (332119): -1.675 -1.675 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332146): Worst-case hold slack is 0.179
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.179 0.000 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.385 0.000 CLOCK_50
- Info (332119): 0.629 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.637
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -0.637 -18.132 CLOCK_50
- Info (332119): -0.394 -38.762 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.459 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info: Analyzing Slow 1100mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.416
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.416 -157.230 tick_50000:TICK0|CLK_OUT
- Info (332119): -2.323 -41.799 CLOCK_50
- Info (332119): -1.568 -1.568 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332146): Worst-case hold slack is 0.193
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.193 0.000 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.405 0.000 CLOCK_50
- Info (332119): 0.501 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.689
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -0.689 -16.816 CLOCK_50
- Info (332119): -0.394 -38.286 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.412 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info: Analyzing Fast 1100mV 85C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.794
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -1.794 -79.872 tick_50000:TICK0|CLK_OUT
- Info (332119): -0.918 -13.912 CLOCK_50
- Info (332119): -0.572 -0.572 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332146): Worst-case hold slack is -0.020
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -0.020 -0.037 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.185 0.000 CLOCK_50
- Info (332119): 0.202 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.740
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -0.740 -12.957 CLOCK_50
- Info (332119): -0.012 -0.190 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.478 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info: Analyzing Fast 1100mV 0C Model
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.581
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -1.581 -69.264 tick_50000:TICK0|CLK_OUT
- Info (332119): -0.868 -11.639 CLOCK_50
- Info (332119): -0.462 -0.462 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332146): Worst-case hold slack is -0.021
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -0.021 -0.052 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.122 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
- Info (332119): 0.177 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.789
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -0.789 -15.486 CLOCK_50
- Info (332119): 0.024 0.000 tick_50000:TICK0|CLK_OUT
- Info (332119): 0.468 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
- Info: Peak virtual memory: 1213 megabytes
- Info: Processing ended: Wed Dec 07 12:08:30 2016
- Info: Elapsed time: 00:00:09
- Info: Total CPU time (on all processors): 00:00:06
-
-
+TimeQuest Timing Analyzer report for ex9
+Sun Dec 11 20:31:05 2016
+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. TimeQuest Timing Analyzer Summary
+ 3. Parallel Compilation
+ 4. Clocks
+ 5. Slow 1100mV 85C Model Fmax Summary
+ 6. Timing Closure Recommendations
+ 7. Slow 1100mV 85C Model Setup Summary
+ 8. Slow 1100mV 85C Model Hold Summary
+ 9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Setup Transfers
+ 40. Hold Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths Summary
+ 44. Clock Status Summary
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Unconstrained Input Ports
+ 48. Unconstrained Output Ports
+ 49. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2016 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Intel and sold by Intel or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary ;
++-----------------------+-----------------------------------------------------+
+; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
+; Timing Analyzer ; TimeQuest ;
+; Revision Name ; ex9 ;
+; Device Family ; Cyclone V ;
+; Device Name ; 5CSEMA5F31C6 ;
+; Timing Models ; Final ;
+; Delay Model ; Combined ;
+; Rise/Fall Delays ; Enabled ;
++-----------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.19 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 6.2% ;
+; Processor 3 ; 6.2% ;
+; Processor 4 ; 6.1% ;
++----------------------------+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+; CLOCK_50 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
+; tick_50000:TICK0|CLK_OUT ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { tick_50000:TICK0|CLK_OUT } ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary ;
++------------+-----------------+--------------------------+------+
+; Fmax ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+--------------------------+------+
+; 202.72 MHz ; 202.72 MHz ; tick_50000:TICK0|CLK_OUT ; ;
+; 312.7 MHz ; 312.7 MHz ; CLOCK_50 ; ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 85C Model Setup Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT ; -3.933 ; -177.510 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -2.353 ; -2.353 ;
+; CLOCK_50 ; -2.198 ; -38.652 ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Slow 1100mV 85C Model Hold Summary ;
++-------------------------------------+-------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT ; 0.222 ; 0.000 ;
+; CLOCK_50 ; 0.381 ; 0.000 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1.023 ; 0.000 ;
++-------------------------------------+-------+---------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50 ; -0.658 ; -17.489 ;
+; tick_50000:TICK0|CLK_OUT ; -0.394 ; -41.338 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.439 ; 0.000 ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary ;
++------------+-----------------+--------------------------+------+
+; Fmax ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+--------------------------+------+
+; 205.47 MHz ; 205.47 MHz ; tick_50000:TICK0|CLK_OUT ; ;
+; 294.9 MHz ; 294.9 MHz ; CLOCK_50 ; ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 0C Model Setup Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT ; -3.867 ; -173.770 ;
+; CLOCK_50 ; -2.391 ; -39.269 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -2.208 ; -2.208 ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Slow 1100mV 0C Model Hold Summary ;
++-------------------------------------+-------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT ; 0.218 ; 0.000 ;
+; CLOCK_50 ; 0.401 ; 0.000 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.821 ; 0.000 ;
++-------------------------------------+-------+---------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50 ; -0.707 ; -16.083 ;
+; tick_50000:TICK0|CLK_OUT ; -0.394 ; -42.153 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.422 ; 0.000 ;
++-------------------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Setup Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT ; -2.263 ; -94.992 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.029 ; -1.029 ;
+; CLOCK_50 ; -1.002 ; -13.129 ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Fast 1100mV 85C Model Hold Summary ;
++-------------------------------------+-------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT ; 0.065 ; 0.000 ;
+; CLOCK_50 ; 0.184 ; 0.000 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.518 ; 0.000 ;
++-------------------------------------+-------+---------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50 ; -0.771 ; -12.597 ;
+; tick_50000:TICK0|CLK_OUT ; -0.035 ; -1.610 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.481 ; 0.000 ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Setup Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT ; -1.967 ; -82.047 ;
+; CLOCK_50 ; -0.958 ; -11.100 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.846 ; -0.846 ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Fast 1100mV 0C Model Hold Summary ;
++-------------------------------------+-------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT ; 0.049 ; 0.000 ;
+; CLOCK_50 ; 0.175 ; 0.000 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.366 ; 0.000 ;
++-------------------------------------+-------+---------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
++-------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50 ; -0.807 ; -14.887 ;
+; tick_50000:TICK0|CLK_OUT ; -0.016 ; -0.422 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.477 ; 0.000 ;
++-------------------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary ;
++--------------------------------------+----------+-------+----------+---------+---------------------+
+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++--------------------------------------+----------+-------+----------+---------+---------------------+
+; Worst-case Slack ; -3.933 ; 0.049 ; N/A ; N/A ; -0.807 ;
+; CLOCK_50 ; -2.391 ; 0.175 ; N/A ; N/A ; -0.807 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -2.353 ; 0.366 ; N/A ; N/A ; 0.422 ;
+; tick_50000:TICK0|CLK_OUT ; -3.933 ; 0.049 ; N/A ; N/A ; -0.394 ;
+; Design-wide TNS ; -218.515 ; 0.0 ; 0.0 ; 0.0 ; -58.827 ;
+; CLOCK_50 ; -39.269 ; 0.000 ; N/A ; N/A ; -17.489 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -2.353 ; 0.000 ; N/A ; N/A ; 0.000 ;
+; tick_50000:TICK0|CLK_OUT ; -177.510 ; 0.000 ; N/A ; N/A ; -42.153 ;
++--------------------------------------+----------+-------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX4[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX5[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX5[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX5[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX5[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX5[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX5[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; HEX5[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times ;
++----------+--------------+-----------------+-----------------+
+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; KEY[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
+; KEY[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
+; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
+; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
+; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
+; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
+; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
+; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
+; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
+; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
+; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
+; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
+; LEDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; LEDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; LEDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
+; LEDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
+; LEDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; CLOCK_50 ; CLOCK_50 ; 386 ; 0 ; 0 ; 0 ;
+; tick_50000:TICK0|CLK_OUT ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1 ; 0 ; 0 ; 0 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 38 ; 21 ; 0 ; 0 ;
+; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 955 ; 0 ; 0 ; 0 ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; CLOCK_50 ; CLOCK_50 ; 386 ; 0 ; 0 ; 0 ;
+; tick_50000:TICK0|CLK_OUT ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1 ; 0 ; 0 ; 0 ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 38 ; 21 ; 0 ; 0 ;
+; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; 955 ; 0 ; 0 ; 0 ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary ;
++---------------------------------+-------+------+
+; Property ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks ; 0 ; 0 ;
+; Unconstrained Clocks ; 0 ; 0 ;
+; Unconstrained Input Ports ; 2 ; 2 ;
+; Unconstrained Input Port Paths ; 20 ; 20 ;
+; Unconstrained Output Ports ; 45 ; 45 ;
+; Unconstrained Output Port Paths ; 500 ; 500 ;
++---------------------------------+-------+------+
+
+
++------------------------------------------------------------------------------------------------+
+; Clock Status Summary ;
++-------------------------------------+-------------------------------------+------+-------------+
+; Target ; Clock ; Type ; Status ;
++-------------------------------------+-------------------------------------+------+-------------+
+; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
+; tick_50000:TICK0|CLK_OUT ; tick_50000:TICK0|CLK_OUT ; Base ; Constrained ;
++-------------------------------------+-------------------------------------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; KEY[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; KEY[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+ Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+ Info: Processing started: Sun Dec 11 20:31:00 2016
+Info: Command: quartus_sta ex9 -c ex9
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+ Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
+ Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
+ Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Critical Warning (332148): Timing requirements not met
+ Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.933
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -3.933 -177.510 tick_50000:TICK0|CLK_OUT
+ Info (332119): -2.353 -2.353 formula_fsm:FSM|state.LIGHT_UP_LEDS
+ Info (332119): -2.198 -38.652 CLOCK_50
+Info (332146): Worst-case hold slack is 0.222
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 0.222 0.000 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.381 0.000 CLOCK_50
+ Info (332119): 1.023 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.658
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -0.658 -17.489 CLOCK_50
+ Info (332119): -0.394 -41.338 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.439 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+ Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.867
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -3.867 -173.770 tick_50000:TICK0|CLK_OUT
+ Info (332119): -2.391 -39.269 CLOCK_50
+ Info (332119): -2.208 -2.208 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332146): Worst-case hold slack is 0.218
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 0.218 0.000 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.401 0.000 CLOCK_50
+ Info (332119): 0.821 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.707
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -0.707 -16.083 CLOCK_50
+ Info (332119): -0.394 -42.153 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.422 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+ Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -2.263
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -2.263 -94.992 tick_50000:TICK0|CLK_OUT
+ Info (332119): -1.029 -1.029 formula_fsm:FSM|state.LIGHT_UP_LEDS
+ Info (332119): -1.002 -13.129 CLOCK_50
+Info (332146): Worst-case hold slack is 0.065
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 0.065 0.000 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.184 0.000 CLOCK_50
+ Info (332119): 0.518 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.771
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -0.771 -12.597 CLOCK_50
+ Info (332119): -0.035 -1.610 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.481 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info: Analyzing Fast 1100mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+ Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.967
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -1.967 -82.047 tick_50000:TICK0|CLK_OUT
+ Info (332119): -0.958 -11.100 CLOCK_50
+ Info (332119): -0.846 -0.846 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332146): Worst-case hold slack is 0.049
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): 0.049 0.000 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.175 0.000 CLOCK_50
+ Info (332119): 0.366 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.807
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -0.807 -14.887 CLOCK_50
+ Info (332119): -0.016 -0.422 tick_50000:TICK0|CLK_OUT
+ Info (332119): 0.477 0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
+ Info: Peak virtual memory: 1216 megabytes
+ Info: Processing ended: Sun Dec 11 20:31:05 2016
+ Info: Elapsed time: 00:00:05
+ Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_2/ex9/output_files/ex9.sta.summary b/part_2/ex9/output_files/ex9.sta.summary
index 87e925d..b1a6e61 100644
--- a/part_2/ex9/output_files/ex9.sta.summary
+++ b/part_2/ex9/output_files/ex9.sta.summary
@@ -1,149 +1,149 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.462
-TNS : -161.413
-
-Type : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -2.047
-TNS : -40.775
-
-Type : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.675
-TNS : -1.675
-
-Type : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.179
-TNS : 0.000
-
-Type : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.385
-TNS : 0.000
-
-Type : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.629
-TNS : 0.000
-
-Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.637
-TNS : -18.132
-
-Type : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS : -38.762
-
-Type : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.459
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.416
-TNS : -157.230
-
-Type : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -2.323
-TNS : -41.799
-
-Type : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.568
-TNS : -1.568
-
-Type : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.193
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.405
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.501
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.689
-TNS : -16.816
-
-Type : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS : -38.286
-
-Type : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.412
-TNS : 0.000
-
-Type : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.794
-TNS : -79.872
-
-Type : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -0.918
-TNS : -13.912
-
-Type : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.572
-TNS : -0.572
-
-Type : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.020
-TNS : -0.037
-
-Type : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.185
-TNS : 0.000
-
-Type : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.202
-TNS : 0.000
-
-Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.740
-TNS : -12.957
-
-Type : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.012
-TNS : -0.190
-
-Type : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.478
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.581
-TNS : -69.264
-
-Type : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -0.868
-TNS : -11.639
-
-Type : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.462
-TNS : -0.462
-
-Type : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.021
-TNS : -0.052
-
-Type : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.122
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.177
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.789
-TNS : -15.486
-
-Type : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.024
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.468
-TNS : 0.000
-
-------------------------------------------------------------
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -3.933
+TNS : -177.510
+
+Type : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -2.353
+TNS : -2.353
+
+Type : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -2.198
+TNS : -38.652
+
+Type : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.222
+TNS : 0.000
+
+Type : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.381
+TNS : 0.000
+
+Type : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 1.023
+TNS : 0.000
+
+Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.658
+TNS : -17.489
+
+Type : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.394
+TNS : -41.338
+
+Type : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.439
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -3.867
+TNS : -173.770
+
+Type : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -2.391
+TNS : -39.269
+
+Type : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -2.208
+TNS : -2.208
+
+Type : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.218
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.401
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.821
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.707
+TNS : -16.083
+
+Type : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.394
+TNS : -42.153
+
+Type : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.422
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -2.263
+TNS : -94.992
+
+Type : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -1.029
+TNS : -1.029
+
+Type : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -1.002
+TNS : -13.129
+
+Type : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.065
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.184
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.518
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.771
+TNS : -12.597
+
+Type : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.035
+TNS : -1.610
+
+Type : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.481
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -1.967
+TNS : -82.047
+
+Type : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -0.958
+TNS : -11.100
+
+Type : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -0.846
+TNS : -0.846
+
+Type : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.049
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.175
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.366
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.807
+TNS : -14.887
+
+Type : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.016
+TNS : -0.422
+
+Type : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.477
+TNS : 0.000
+
+------------------------------------------------------------
diff --git a/part_2/ex9/verilog_files/formula_fsm.v b/part_2/ex9/verilog_files/formula_fsm.v
index 2a79785..67ad1ee 100644
--- a/part_2/ex9/verilog_files/formula_fsm.v
+++ b/part_2/ex9/verilog_files/formula_fsm.v
@@ -1,39 +1,39 @@
module formula_fsm(clk, trigger, time_out, en_lfsr, start_delay, ledr);
-input clk, time_out, trigger;
-output en_lfsr, start_delay;
-output [9:0] ledr;
+ input clk, time_out, trigger;
+ output en_lfsr, start_delay;
+ output [9:0] ledr;
-reg [1:0] state;
-reg led_on, en_lfsr, start_delay;
-reg [9:0] ledr;
-reg [11:0] count;
+ reg [1:0] state;
+ reg led_on, en_lfsr, start_delay;
+ reg [9:0] ledr;
+ reg [8:0] count;
-parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;
+ parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;
-initial
- begin
- state = WAIT_TRIGGER;
- en_lfsr = 1'b0;
- start_delay = 1'b0;
- count = 12'd2499;
- end
+ initial
+ begin
+ state = WAIT_TRIGGER;
+ en_lfsr = 1'b0;
+ start_delay = 1'b0;
+ count = 9'd499;
+ end
-always @ (posedge clk)
- case(state)
- WAIT_TRIGGER:
- begin
- if(trigger == 1'b1)
- state <= LIGHT_UP_LEDS;
- end
- LIGHT_UP_LEDS:
- if(ledr == 10'h3ff)
- state <= WAIT_FOR_TIMEOUT;
- WAIT_FOR_TIMEOUT:
- if(time_out == 1'b1)
- state <= WAIT_TRIGGER;
- default: ;
- endcase
+ always @ (posedge clk)
+ case(state)
+ WAIT_TRIGGER:
+ begin
+ if(trigger == 1'b1)
+ state <= LIGHT_UP_LEDS;
+ end
+ LIGHT_UP_LEDS:
+ if(ledr == 10'h3ff)
+ state <= WAIT_FOR_TIMEOUT;
+ WAIT_FOR_TIMEOUT:
+ if(time_out == 1'b1)
+ state <= WAIT_TRIGGER;
+ default: ;
+ endcase
always @ (posedge clk)
case(state)
@@ -41,36 +41,36 @@ always @ (posedge clk)
ledr = 0;
LIGHT_UP_LEDS:
begin
- if(count == 1'b0)
+ if(count == 9'b0)
begin
ledr <= {ledr[8:0], 1'b1};
- count <= 12'd2499;
+ count <= 9'd499;
end
else
begin
count <= count - 1'b1;
end
end
- default: count <= 12'd2499;
- endcase
-
-always @ (*)
- case(state)
- WAIT_TRIGGER:
- begin
- en_lfsr = 1'b0;
- start_delay = 1'b0;
- end
- LIGHT_UP_LEDS:
- begin
- en_lfsr = 1'b1;
- end
- WAIT_FOR_TIMEOUT:
- begin
- start_delay = 1'b1;
- en_lfsr = 1'b0;
- end
- default: ;
+ default: count <= 9'd499;
endcase
+
+ always @ (*)
+ case(state)
+ WAIT_TRIGGER:
+ begin
+ en_lfsr = 1'b0;
+ start_delay = 1'b0;
+ end
+ LIGHT_UP_LEDS:
+ begin
+ en_lfsr = 1'b1;
+ end
+ WAIT_FOR_TIMEOUT:
+ begin
+ start_delay = 1'b1;
+ en_lfsr = 1'b0;
+ end
+ default: ;
+ endcase
endmodule \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-05-14 23:16:13 +0000