updated part 2

author: ymherklotz <ymherklotz@gmail.com> 2016-12-11 16:37:13 +0000
committer: ymherklotz <ymherklotz@gmail.com> 2016-12-11 16:37:13 +0000
commit: 47665d0ff2ee13848f4b5b2e3a36d7f4e8b08731 (patch)
tree: 3b6ca2e93e2ad9fd56d4286af311c3c880c09068
parent: 137e647c057d471bd0a26fa037b1ef575a2568e7 (diff)
download: VerilogCoursework-47665d0ff2ee13848f4b5b2e3a36d7f4e8b08731.tar.gz
VerilogCoursework-47665d0ff2ee13848f4b5b2e3a36d7f4e8b08731.zip
99 files changed, 12692 insertions, 12692 deletions
diff --git a/part_1/ex1/db/_cmp.kpt b/part_1/ex1/db/_cmp.kpt
new file mode 100644
index 0000000..454d272
--- /dev/null
+++ b/part_1/ex1/db/_cmp.kpt
diff --git a/part_1/ex2/db/_cmp.kpt b/part_1/ex2/db/_cmp.kpt
new file mode 100644
index 0000000..8d0efe5
--- /dev/null
+++ b/part_1/ex2/db/_cmp.kpt
diff --git a/part_1/ex2/extra_files/pin_assignment.txt b/part_1/ex2/extra_files/pin_assignment.txt
index 04a3a75..4a576a0 100755
--- a/part_1/ex2/extra_files/pin_assignment.txt
+++ b/part_1/ex2/extra_files/pin_assignment.txt
@@ -1,211 +1,211 @@
-#============================================================
-# CLOCK
-#============================================================
-set_location_assignment PIN_AF14 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# Add-on Card Interface Pins
-#============================================================
-set_location_assignment PIN_AJ20 -to PWM_OUT
-set_location_assignment PIN_AK21 -to DAC_LD
-set_location_assignment PIN_AD20 -to DAC_CS
-set_location_assignment PIN_AF20 -to DAC_SCK
-set_location_assignment PIN_AF21 -to ADC_SCK
-set_location_assignment PIN_AG21 -to ADC_SDI
-set_location_assignment PIN_AG20 -to ADC_CS
-set_location_assignment PIN_AG18 -to DAC_SDI
-set_location_assignment PIN_AJ21 -to ADC_SDO
-set_location_assignment PIN_Y17 -to OLED_CS
-set_location_assignment PIN_Y18 -to OLED_RST
-set_location_assignment PIN_AK18 -to OLED_DC
-set_location_assignment PIN_AJ19 -to OLED_CLK
-set_location_assignment PIN_AJ16 -to OLED_DATA
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
-
-
-#============================================================
-# HEX0
-#============================================================
-set_location_assignment PIN_AE26 -to HEX0[0]
-set_location_assignment PIN_AE27 -to HEX0[1]
-set_location_assignment PIN_AE28 -to HEX0[2]
-set_location_assignment PIN_AG27 -to HEX0[3]
-set_location_assignment PIN_AF28 -to HEX0[4]
-set_location_assignment PIN_AG28 -to HEX0[5]
-set_location_assignment PIN_AH28 -to HEX0[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
-
-#============================================================
-# HEX1
-#============================================================
-set_location_assignment PIN_AJ29 -to HEX1[0]
-set_location_assignment PIN_AH29 -to HEX1[1]
-set_location_assignment PIN_AH30 -to HEX1[2]
-set_location_assignment PIN_AG30 -to HEX1[3]
-set_location_assignment PIN_AF29 -to HEX1[4]
-set_location_assignment PIN_AF30 -to HEX1[5]
-set_location_assignment PIN_AD27 -to HEX1[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
-
-#============================================================
-# HEX2
-#============================================================
-set_location_assignment PIN_AB23 -to HEX2[0]
-set_location_assignment PIN_AE29 -to HEX2[1]
-set_location_assignment PIN_AD29 -to HEX2[2]
-set_location_assignment PIN_AC28 -to HEX2[3]
-set_location_assignment PIN_AD30 -to HEX2[4]
-set_location_assignment PIN_AC29 -to HEX2[5]
-set_location_assignment PIN_AC30 -to HEX2[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
-
-#============================================================
-# HEX3
-#============================================================
-set_location_assignment PIN_AD26 -to HEX3[0]
-set_location_assignment PIN_AC27 -to HEX3[1]
-set_location_assignment PIN_AD25 -to HEX3[2]
-set_location_assignment PIN_AC25 -to HEX3[3]
-set_location_assignment PIN_AB28 -to HEX3[4]
-set_location_assignment PIN_AB25 -to HEX3[5]
-set_location_assignment PIN_AB22 -to HEX3[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
-
-#============================================================
-# HEX4
-#============================================================
-set_location_assignment PIN_AA24 -to HEX4[0]
-set_location_assignment PIN_Y23 -to HEX4[1]
-set_location_assignment PIN_Y24 -to HEX4[2]
-set_location_assignment PIN_W22 -to HEX4[3]
-set_location_assignment PIN_W24 -to HEX4[4]
-set_location_assignment PIN_V23 -to HEX4[5]
-set_location_assignment PIN_W25 -to HEX4[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
-
-#============================================================
-# HEX5
-#============================================================
-set_location_assignment PIN_V25 -to HEX5[0]
-set_location_assignment PIN_AA28 -to HEX5[1]
-set_location_assignment PIN_Y27 -to HEX5[2]
-set_location_assignment PIN_AB27 -to HEX5[3]
-set_location_assignment PIN_AB26 -to HEX5[4]
-set_location_assignment PIN_AA26 -to HEX5[5]
-set_location_assignment PIN_AA25 -to HEX5[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
-
-#============================================================
-# KEY
-#============================================================
-set_location_assignment PIN_AA14 -to KEY[0]
-set_location_assignment PIN_AA15 -to KEY[1]
-set_location_assignment PIN_W15 -to KEY[2]
-set_location_assignment PIN_Y16 -to KEY[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
-
-#============================================================
-# LEDR
-#============================================================
-set_location_assignment PIN_V16 -to LEDR[0]
-set_location_assignment PIN_W16 -to LEDR[1]
-set_location_assignment PIN_V17 -to LEDR[2]
-set_location_assignment PIN_V18 -to LEDR[3]
-set_location_assignment PIN_W17 -to LEDR[4]
-set_location_assignment PIN_W19 -to LEDR[5]
-set_location_assignment PIN_Y19 -to LEDR[6]
-set_location_assignment PIN_W20 -to LEDR[7]
-set_location_assignment PIN_W21 -to LEDR[8]
-set_location_assignment PIN_Y21 -to LEDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
-
-#============================================================
-# SW
-#============================================================
-set_location_assignment PIN_AB12 -to SW[0]
-set_location_assignment PIN_AC12 -to SW[1]
-set_location_assignment PIN_AF9 -to SW[2]
-set_location_assignment PIN_AF10 -to SW[3]
-set_location_assignment PIN_AD11 -to SW[4]
-set_location_assignment PIN_AD12 -to SW[5]
-set_location_assignment PIN_AE11 -to SW[6]
-set_location_assignment PIN_AC9 -to SW[7]
-set_location_assignment PIN_AD10 -to SW[8]
-set_location_assignment PIN_AE12 -to SW[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
-
-#============================================================
-# End of pin and io_standard assignments
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
 #============================================================
 \ No newline at end of file
diff --git a/part_1/ex3/db/_cmp.kpt b/part_1/ex3/db/_cmp.kpt
new file mode 100644
index 0000000..bdb612b
--- /dev/null
+++ b/part_1/ex3/db/_cmp.kpt
diff --git a/part_1/ex4/db/_cmp.kpt b/part_1/ex4/db/_cmp.kpt
new file mode 100644
index 0000000..580e170
--- /dev/null
+++ b/part_1/ex4/db/_cmp.kpt
diff --git a/part_2/ex5/db/_cmp.kpt b/part_2/ex5/db/_cmp.kpt
new file mode 100644
index 0000000..1dafbef
--- /dev/null
+++ b/part_2/ex5/db/_cmp.kpt
diff --git a/part_2/ex5/pin_assignment.txt b/part_2/ex5/pin_assignment.txt
index 04a3a75..4a576a0 100755
--- a/part_2/ex5/pin_assignment.txt
+++ b/part_2/ex5/pin_assignment.txt
@@ -1,211 +1,211 @@
-#============================================================
-# CLOCK
-#============================================================
-set_location_assignment PIN_AF14 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# Add-on Card Interface Pins
-#============================================================
-set_location_assignment PIN_AJ20 -to PWM_OUT
-set_location_assignment PIN_AK21 -to DAC_LD
-set_location_assignment PIN_AD20 -to DAC_CS
-set_location_assignment PIN_AF20 -to DAC_SCK
-set_location_assignment PIN_AF21 -to ADC_SCK
-set_location_assignment PIN_AG21 -to ADC_SDI
-set_location_assignment PIN_AG20 -to ADC_CS
-set_location_assignment PIN_AG18 -to DAC_SDI
-set_location_assignment PIN_AJ21 -to ADC_SDO
-set_location_assignment PIN_Y17 -to OLED_CS
-set_location_assignment PIN_Y18 -to OLED_RST
-set_location_assignment PIN_AK18 -to OLED_DC
-set_location_assignment PIN_AJ19 -to OLED_CLK
-set_location_assignment PIN_AJ16 -to OLED_DATA
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
-
-
-#============================================================
-# HEX0
-#============================================================
-set_location_assignment PIN_AE26 -to HEX0[0]
-set_location_assignment PIN_AE27 -to HEX0[1]
-set_location_assignment PIN_AE28 -to HEX0[2]
-set_location_assignment PIN_AG27 -to HEX0[3]
-set_location_assignment PIN_AF28 -to HEX0[4]
-set_location_assignment PIN_AG28 -to HEX0[5]
-set_location_assignment PIN_AH28 -to HEX0[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
-
-#============================================================
-# HEX1
-#============================================================
-set_location_assignment PIN_AJ29 -to HEX1[0]
-set_location_assignment PIN_AH29 -to HEX1[1]
-set_location_assignment PIN_AH30 -to HEX1[2]
-set_location_assignment PIN_AG30 -to HEX1[3]
-set_location_assignment PIN_AF29 -to HEX1[4]
-set_location_assignment PIN_AF30 -to HEX1[5]
-set_location_assignment PIN_AD27 -to HEX1[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
-
-#============================================================
-# HEX2
-#============================================================
-set_location_assignment PIN_AB23 -to HEX2[0]
-set_location_assignment PIN_AE29 -to HEX2[1]
-set_location_assignment PIN_AD29 -to HEX2[2]
-set_location_assignment PIN_AC28 -to HEX2[3]
-set_location_assignment PIN_AD30 -to HEX2[4]
-set_location_assignment PIN_AC29 -to HEX2[5]
-set_location_assignment PIN_AC30 -to HEX2[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
-
-#============================================================
-# HEX3
-#============================================================
-set_location_assignment PIN_AD26 -to HEX3[0]
-set_location_assignment PIN_AC27 -to HEX3[1]
-set_location_assignment PIN_AD25 -to HEX3[2]
-set_location_assignment PIN_AC25 -to HEX3[3]
-set_location_assignment PIN_AB28 -to HEX3[4]
-set_location_assignment PIN_AB25 -to HEX3[5]
-set_location_assignment PIN_AB22 -to HEX3[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
-
-#============================================================
-# HEX4
-#============================================================
-set_location_assignment PIN_AA24 -to HEX4[0]
-set_location_assignment PIN_Y23 -to HEX4[1]
-set_location_assignment PIN_Y24 -to HEX4[2]
-set_location_assignment PIN_W22 -to HEX4[3]
-set_location_assignment PIN_W24 -to HEX4[4]
-set_location_assignment PIN_V23 -to HEX4[5]
-set_location_assignment PIN_W25 -to HEX4[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
-
-#============================================================
-# HEX5
-#============================================================
-set_location_assignment PIN_V25 -to HEX5[0]
-set_location_assignment PIN_AA28 -to HEX5[1]
-set_location_assignment PIN_Y27 -to HEX5[2]
-set_location_assignment PIN_AB27 -to HEX5[3]
-set_location_assignment PIN_AB26 -to HEX5[4]
-set_location_assignment PIN_AA26 -to HEX5[5]
-set_location_assignment PIN_AA25 -to HEX5[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
-
-#============================================================
-# KEY
-#============================================================
-set_location_assignment PIN_AA14 -to KEY[0]
-set_location_assignment PIN_AA15 -to KEY[1]
-set_location_assignment PIN_W15 -to KEY[2]
-set_location_assignment PIN_Y16 -to KEY[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
-
-#============================================================
-# LEDR
-#============================================================
-set_location_assignment PIN_V16 -to LEDR[0]
-set_location_assignment PIN_W16 -to LEDR[1]
-set_location_assignment PIN_V17 -to LEDR[2]
-set_location_assignment PIN_V18 -to LEDR[3]
-set_location_assignment PIN_W17 -to LEDR[4]
-set_location_assignment PIN_W19 -to LEDR[5]
-set_location_assignment PIN_Y19 -to LEDR[6]
-set_location_assignment PIN_W20 -to LEDR[7]
-set_location_assignment PIN_W21 -to LEDR[8]
-set_location_assignment PIN_Y21 -to LEDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
-
-#============================================================
-# SW
-#============================================================
-set_location_assignment PIN_AB12 -to SW[0]
-set_location_assignment PIN_AC12 -to SW[1]
-set_location_assignment PIN_AF9 -to SW[2]
-set_location_assignment PIN_AF10 -to SW[3]
-set_location_assignment PIN_AD11 -to SW[4]
-set_location_assignment PIN_AD12 -to SW[5]
-set_location_assignment PIN_AE11 -to SW[6]
-set_location_assignment PIN_AC9 -to SW[7]
-set_location_assignment PIN_AD10 -to SW[8]
-set_location_assignment PIN_AE12 -to SW[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
-
-#============================================================
-# End of pin and io_standard assignments
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
 #============================================================
 \ No newline at end of file
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_info b/part_2/ex5/simulation/modelsim/rtl_work/_info
index 9a599cc..9a0155e 100755
--- a/part_2/ex5/simulation/modelsim/rtl_work/_info
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_info
@@ -1,25 +1,25 @@
-m255
-K3
-13
-cModel Technology
-Z0 dC:\New folder\simulation\modelsim
-vcounter_8
-!i10b 1
-!s100 ;ldZ:oUkgLo?@Aa7ibdbm2
-Ia91@O_<g0BVIc?WTzTbB62
-Vdn7aTnOzPKdeZA;zmQ`Cl3
-Z1 dC:\New folder\simulation\modelsim
-w1479807538
-8C:/New folder/verilog_files/counter_8.v
-FC:/New folder/verilog_files/counter_8.v
-L0 3
-OV;L;10.1d;51
-r1
-!s85 0
-31
-!s108 1479807676.024000
-!s107 C:/New folder/verilog_files/counter_8.v|
-!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/verilog_files|C:/New folder/verilog_files/counter_8.v|
-!s101 -O0
-o-vlog01compat -work work -O0
-!s92 -vlog01compat -work work {+incdir+C:/New folder/verilog_files} -O0
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\simulation\modelsim
+vcounter_8
+!i10b 1
+!s100 ;ldZ:oUkgLo?@Aa7ibdbm2
+Ia91@O_<g0BVIc?WTzTbB62
+Vdn7aTnOzPKdeZA;zmQ`Cl3
+Z1 dC:\New folder\simulation\modelsim
+w1479807538
+8C:/New folder/verilog_files/counter_8.v
+FC:/New folder/verilog_files/counter_8.v
+L0 3
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1479807676.024000
+!s107 C:/New folder/verilog_files/counter_8.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/verilog_files|C:/New folder/verilog_files/counter_8.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/verilog_files} -O0
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_vmake b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
index 2f7e729..b51b305 100755
--- a/part_2/ex5/simulation/modelsim/rtl_work/_vmake
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
@@ -1,3 +1,3 @@
-m255
-K3
-cModel Technology
+m255
+K3
+cModel Technology
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
index 0dd84bc..8ada04e 100755
--- a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
@@ -1,14 +1,14 @@
-library verilog;
-use verilog.vl_types.all;
-entity counter_8 is
-    generic(
-        BIT_SZ          : integer := 8
-    );
-    port(
-        clock           : in     vl_logic;
-        enable          : in     vl_logic;
-        count           : out    vl_logic_vector
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of BIT_SZ : constant is 1;
-end counter_8;
+library verilog;
+use verilog.vl_types.all;
+entity counter_8 is
+    generic(
+        BIT_SZ          : integer := 8
+    );
+    port(
+        clock           : in     vl_logic;
+        enable          : in     vl_logic;
+        count           : out    vl_logic_vector
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BIT_SZ : constant is 1;
+end counter_8;
diff --git a/part_2/ex5/simulation/modelsim/tb_counter b/part_2/ex5/simulation/modelsim/tb_counter
index 6256691..4544d6a 100755
--- a/part_2/ex5/simulation/modelsim/tb_counter
+++ b/part_2/ex5/simulation/modelsim/tb_counter
@@ -1,9 +1,9 @@
-add wave clock enable
-add wave -hexadecimal count
-force clock 0 0, 1 10ns -repeat 20ns
-force enable 1
-run 100ns
-force enable 0
-run 100ns
-force enable 1
+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
 run 1000
 \ No newline at end of file
diff --git a/part_2/ex5/simulation/modelsim/tb_counter.do b/part_2/ex5/simulation/modelsim/tb_counter.do
index 6256691..4544d6a 100755
--- a/part_2/ex5/simulation/modelsim/tb_counter.do
+++ b/part_2/ex5/simulation/modelsim/tb_counter.do
@@ -1,9 +1,9 @@
-add wave clock enable
-add wave -hexadecimal count
-force clock 0 0, 1 10ns -repeat 20ns
-force enable 1
-run 100ns
-force enable 0
-run 100ns
-force enable 1
+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
 run 1000
 \ No newline at end of file
diff --git a/part_2/ex6/db/_cmp.kpt b/part_2/ex6/db/_cmp.kpt
new file mode 100644
index 0000000..38aa87b
--- /dev/null
+++ b/part_2/ex6/db/_cmp.kpt
diff --git a/part_2/ex7/db/_cmp.kpt b/part_2/ex7/db/_cmp.kpt
new file mode 100644
index 0000000..7fc2356
--- /dev/null
+++ b/part_2/ex7/db/_cmp.kpt
diff --git a/part_2/ex8/db/_cmp.kpt b/part_2/ex8/db/_cmp.kpt
new file mode 100644
index 0000000..810fa45
--- /dev/null
+++ b/part_2/ex8/db/_cmp.kpt
diff --git a/part_2/ex9/c5_pin_model_dump.txt b/part_2/ex9/c5_pin_model_dump.txt
index 31bb72c..a895a64 100644
--- a/part_2/ex9/c5_pin_model_dump.txt
+++ b/part_2/ex9/c5_pin_model_dump.txt
@@ -1,118 +1,118 @@
-io_4iomodule_c5_index: 55gpio_index: 2
-io_4iomodule_c5_index: 54gpio_index: 465
-io_4iomodule_c5_index: 33gpio_index: 6
-io_4iomodule_c5_index: 51gpio_index: 461
-io_4iomodule_c5_index: 27gpio_index: 10
-io_4iomodule_c5_index: 57gpio_index: 457
-io_4iomodule_c5_index: 34gpio_index: 14
-io_4iomodule_c5_index: 28gpio_index: 453
-io_4iomodule_c5_index: 26gpio_index: 19
-io_4iomodule_c5_index: 47gpio_index: 449
-io_4iomodule_c5_index: 29gpio_index: 22
-io_4iomodule_c5_index: 3gpio_index: 445
-io_4iomodule_c5_index: 16gpio_index: 27
-io_4iomodule_c5_index: 6gpio_index: 441
-io_4iomodule_c5_index: 50gpio_index: 30
-io_4iomodule_c5_index: 35gpio_index: 437
-io_4iomodule_c5_index: 7gpio_index: 35
-io_4iomodule_c5_index: 53gpio_index: 433
-io_4iomodule_c5_index: 12gpio_index: 38
-io_4iomodule_c5_index: 1gpio_index: 429
-io_4iomodule_c5_index: 22gpio_index: 43
-io_4iomodule_c5_index: 8gpio_index: 425
-io_4iomodule_c5_index: 20gpio_index: 46
-io_4iomodule_c5_index: 30gpio_index: 421
-io_4iomodule_c5_index: 2gpio_index: 51
-io_4iomodule_c5_index: 31gpio_index: 417
-io_4iomodule_c5_index: 39gpio_index: 54
-io_4iomodule_c5_index: 18gpio_index: 413
-io_4iomodule_c5_index: 10gpio_index: 59
-io_4iomodule_c5_index: 42gpio_index: 409
-io_4iomodule_c5_index: 5gpio_index: 62
-io_4iomodule_c5_index: 24gpio_index: 405
-io_4iomodule_c5_index: 37gpio_index: 67
-io_4iomodule_c5_index: 13gpio_index: 401
-io_4iomodule_c5_index: 0gpio_index: 70
-io_4iomodule_c5_index: 44gpio_index: 397
-io_4iomodule_c5_index: 38gpio_index: 75
-io_4iomodule_c5_index: 52gpio_index: 393
-io_4iomodule_c5_index: 32gpio_index: 78
-io_4iomodule_c5_index: 56gpio_index: 389
-io_4iomodule_a_index: 13gpio_index: 385
-io_4iomodule_c5_index: 4gpio_index: 83
-io_4iomodule_c5_index: 23gpio_index: 86
-io_4iomodule_a_index: 15gpio_index: 381
-io_4iomodule_a_index: 8gpio_index: 377
-io_4iomodule_c5_index: 46gpio_index: 91
-io_4iomodule_a_index: 5gpio_index: 373
-io_4iomodule_a_index: 11gpio_index: 369
-io_4iomodule_c5_index: 41gpio_index: 94
-io_4iomodule_a_index: 3gpio_index: 365
-io_4iomodule_c5_index: 25gpio_index: 99
-io_4iomodule_a_index: 7gpio_index: 361
-io_4iomodule_c5_index: 9gpio_index: 102
-io_4iomodule_a_index: 0gpio_index: 357
-io_4iomodule_c5_index: 14gpio_index: 107
-io_4iomodule_a_index: 12gpio_index: 353
-io_4iomodule_c5_index: 45gpio_index: 110
-io_4iomodule_c5_index: 17gpio_index: 115
-io_4iomodule_a_index: 4gpio_index: 349
-io_4iomodule_c5_index: 36gpio_index: 118
-io_4iomodule_a_index: 10gpio_index: 345
-io_4iomodule_a_index: 16gpio_index: 341
-io_4iomodule_c5_index: 15gpio_index: 123
-io_4iomodule_a_index: 14gpio_index: 337
-io_4iomodule_c5_index: 43gpio_index: 126
-io_4iomodule_c5_index: 19gpio_index: 131
-io_4iomodule_a_index: 1gpio_index: 333
-io_4iomodule_c5_index: 59gpio_index: 134
-io_4iomodule_a_index: 2gpio_index: 329
-io_4iomodule_a_index: 9gpio_index: 325
-io_4iomodule_c5_index: 48gpio_index: 139
-io_4iomodule_a_index: 6gpio_index: 321
-io_4iomodule_a_index: 17gpio_index: 317
-io_4iomodule_c5_index: 40gpio_index: 142
-io_4iomodule_c5_index: 11gpio_index: 147
-io_4iomodule_c5_index: 58gpio_index: 150
-io_4iomodule_c5_index: 21gpio_index: 155
-io_4iomodule_c5_index: 49gpio_index: 158
-io_4iomodule_h_c5_index: 0gpio_index: 161
-io_4iomodule_h_c5_index: 6gpio_index: 165
-io_4iomodule_h_c5_index: 10gpio_index: 169
-io_4iomodule_h_c5_index: 3gpio_index: 173
-io_4iomodule_h_c5_index: 8gpio_index: 176
-io_4iomodule_h_c5_index: 11gpio_index: 180
-io_4iomodule_h_c5_index: 7gpio_index: 184
-io_4iomodule_h_c5_index: 5gpio_index: 188
-io_4iomodule_h_c5_index: 1gpio_index: 192
-io_4iomodule_h_c5_index: 2gpio_index: 196
-io_4iomodule_h_c5_index: 9gpio_index: 200
-io_4iomodule_h_c5_index: 4gpio_index: 204
-io_4iomodule_h_index: 15gpio_index: 208
-io_4iomodule_h_index: 1gpio_index: 212
-io_4iomodule_h_index: 3gpio_index: 216
-io_4iomodule_h_index: 2gpio_index: 220
-io_4iomodule_h_index: 11gpio_index: 224
-io_4iomodule_vref_h_index: 1gpio_index: 228
-io_4iomodule_h_index: 20gpio_index: 231
-io_4iomodule_h_index: 8gpio_index: 235
-io_4iomodule_h_index: 6gpio_index: 239
-io_4iomodule_h_index: 10gpio_index: 243
-io_4iomodule_h_index: 23gpio_index: 247
-io_4iomodule_h_index: 7gpio_index: 251
-io_4iomodule_h_index: 22gpio_index: 255
-io_4iomodule_h_index: 5gpio_index: 259
-io_4iomodule_h_index: 24gpio_index: 263
-io_4iomodule_h_index: 0gpio_index: 267
-io_4iomodule_h_index: 13gpio_index: 271
-io_4iomodule_h_index: 21gpio_index: 275
-io_4iomodule_h_index: 16gpio_index: 279
-io_4iomodule_vref_h_index: 0gpio_index: 283
-io_4iomodule_h_index: 12gpio_index: 286
-io_4iomodule_h_index: 4gpio_index: 290
-io_4iomodule_h_index: 19gpio_index: 294
-io_4iomodule_h_index: 18gpio_index: 298
-io_4iomodule_h_index: 17gpio_index: 302
-io_4iomodule_h_index: 25gpio_index: 306
-io_4iomodule_h_index: 14gpio_index: 310
-io_4iomodule_h_index: 9gpio_index: 314
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_2/ex9/db/_cmp.kpt b/part_2/ex9/db/_cmp.kpt
new file mode 100644
index 0000000..1617b0b
--- /dev/null
+++ b/part_2/ex9/db/_cmp.kpt
diff --git a/part_2/ex9/db/ex9.asm.qmsg b/part_2/ex9/db/ex9.asm.qmsg
index 85a88b0..c869bf0 100644
--- a/part_2/ex9/db/ex9.asm.qmsg
+++ b/part_2/ex9/db/ex9.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112492741 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112492743 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:08:12 2016 " "Processing started: Wed Dec 07 12:08:12 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112492743 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481112492743 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481112492743 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481112493565 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481112498243 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:20 2016 " "Processing ended: Wed Dec 07 12:08:20 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481112500798 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112492741 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112492743 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:08:12 2016 " "Processing started: Wed Dec 07 12:08:12 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112492743 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481112492743 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481112492743 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481112493565 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481112498243 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:20 2016 " "Processing ended: Wed Dec 07 12:08:20 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481112500798 ""}
diff --git a/part_2/ex9/db/ex9.cbx.xml b/part_2/ex9/db/ex9.cbx.xml
index 3c357f6..9156ad4 100644
--- a/part_2/ex9/db/ex9.cbx.xml
+++ b/part_2/ex9/db/ex9.cbx.xml
@@ -1,5 +1,5 @@
-<?xml version="1.0" ?>
-<LOG_ROOT>
-	<PROJECT NAME="ex9">
-	</PROJECT>
-</LOG_ROOT>
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ex9">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/part_2/ex9/db/ex9.cmp.logdb b/part_2/ex9/db/ex9.cmp.logdb
index f553480..b4567d7 100644
--- a/part_2/ex9/db/ex9.cmp.logdb
+++ b/part_2/ex9/db/ex9.cmp.logdb
@@ -1,96 +1,96 @@
-v1
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
-IO_RULES_MATRIX,Total Pass,57;0;57;0;0;57;57;0;57;57;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,0;57;0;57;57;0;0;57;0;0;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,28,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,57;0;57;0;0;57;57;0;57;57;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;57;0;57;57;0;0;57;0;0;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_2/ex9/db/ex9.db_info b/part_2/ex9/db/ex9.db_info
index 877ee3d..0319e5b 100644
--- a/part_2/ex9/db/ex9.db_info
+++ b/part_2/ex9/db/ex9.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Version_Index = 402707200
-Creation_Time = Wed Dec 07 11:55:17 2016
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Wed Dec 07 11:55:17 2016
diff --git a/part_2/ex9/db/ex9.fit.qmsg b/part_2/ex9/db/ex9.fit.qmsg
index ae2d6ba..ad91f8e 100644
--- a/part_2/ex9/db/ex9.fit.qmsg
+++ b/part_2/ex9/db/ex9.fit.qmsg
@@ -1,45 +1,45 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481112453657 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481112453658 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481112453895 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112453945 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112453945 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481112454353 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481112454715 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481112465342 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481112465453 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481112465453 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112465454 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481112465457 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112465458 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112465459 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481112465459 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481112465460 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481112465460 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481112466204 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481112466204 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481112466205 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481112466208 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481112466209 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481112466209 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481112466213 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481112466214 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481112466214 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481112466267 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112466278 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481112471355 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481112471629 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112472386 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481112473242 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481112474189 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112474189 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481112475466 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481112480003 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481112480003 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481112481785 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481112481785 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112481789 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481112483588 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112483629 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112484239 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112484239 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112484754 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112487536 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481112487786 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481112487890 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2593 " "Peak virtual memory: 2593 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:09 2016 " "Processing ended: Wed Dec 07 12:08:09 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Elapsed time: 00:00:37" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:02 " "Total CPU time (on all processors): 00:01:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481112489326 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481112453657 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481112453658 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481112453895 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112453945 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112453945 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481112454353 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481112454715 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481112465342 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481112465453 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481112465453 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112465454 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481112465457 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112465458 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112465459 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481112465459 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481112465460 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481112465460 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481112466204 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481112466204 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481112466205 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481112466208 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481112466209 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481112466209 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481112466213 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481112466214 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481112466214 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481112466267 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112466278 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481112471355 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481112471629 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112472386 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481112473242 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481112474189 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112474189 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481112475466 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481112480003 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481112480003 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481112481785 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481112481785 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112481789 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481112483588 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112483629 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112484239 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112484239 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112484754 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112487536 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481112487786 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481112487890 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2593 " "Peak virtual memory: 2593 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:09 2016 " "Processing ended: Wed Dec 07 12:08:09 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Elapsed time: 00:00:37" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:02 " "Total CPU time (on all processors): 00:01:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481112489326 ""}
diff --git a/part_2/ex9/db/ex9.hier_info b/part_2/ex9/db/ex9.hier_info
index bfadead..2ac051e 100644
--- a/part_2/ex9/db/ex9.hier_info
+++ b/part_2/ex9/db/ex9.hier_info
@@ -1,784 +1,784 @@
-|ex9
-CLOCK_50 => CLOCK_50.IN1
-KEY[0] => _.IN1
-KEY[1] => ~NO_FANOUT~
-KEY[2] => ~NO_FANOUT~
-KEY[3] => _.IN1
-HEX0[0] << hex_to_7seg:SEG0.port0
-HEX0[1] << hex_to_7seg:SEG0.port0
-HEX0[2] << hex_to_7seg:SEG0.port0
-HEX0[3] << hex_to_7seg:SEG0.port0
-HEX0[4] << hex_to_7seg:SEG0.port0
-HEX0[5] << hex_to_7seg:SEG0.port0
-HEX0[6] << hex_to_7seg:SEG0.port0
-HEX1[0] << hex_to_7seg:SEG1.port0
-HEX1[1] << hex_to_7seg:SEG1.port0
-HEX1[2] << hex_to_7seg:SEG1.port0
-HEX1[3] << hex_to_7seg:SEG1.port0
-HEX1[4] << hex_to_7seg:SEG1.port0
-HEX1[5] << hex_to_7seg:SEG1.port0
-HEX1[6] << hex_to_7seg:SEG1.port0
-HEX2[0] << hex_to_7seg:SEG2.port0
-HEX2[1] << hex_to_7seg:SEG2.port0
-HEX2[2] << hex_to_7seg:SEG2.port0
-HEX2[3] << hex_to_7seg:SEG2.port0
-HEX2[4] << hex_to_7seg:SEG2.port0
-HEX2[5] << hex_to_7seg:SEG2.port0
-HEX2[6] << hex_to_7seg:SEG2.port0
-HEX3[0] << hex_to_7seg:SEG3.port0
-HEX3[1] << hex_to_7seg:SEG3.port0
-HEX3[2] << hex_to_7seg:SEG3.port0
-HEX3[3] << hex_to_7seg:SEG3.port0
-HEX3[4] << hex_to_7seg:SEG3.port0
-HEX3[5] << hex_to_7seg:SEG3.port0
-HEX3[6] << hex_to_7seg:SEG3.port0
-HEX4[0] << hex_to_7seg:SEG4.port0
-HEX4[1] << hex_to_7seg:SEG4.port0
-HEX4[2] << hex_to_7seg:SEG4.port0
-HEX4[3] << hex_to_7seg:SEG4.port0
-HEX4[4] << hex_to_7seg:SEG4.port0
-HEX4[5] << hex_to_7seg:SEG4.port0
-HEX4[6] << hex_to_7seg:SEG4.port0
-HEX5[0] << hex_to_7seg:SEG5.port0
-HEX5[1] << hex_to_7seg:SEG5.port0
-HEX5[2] << hex_to_7seg:SEG5.port0
-HEX5[3] << hex_to_7seg:SEG5.port0
-HEX5[4] << hex_to_7seg:SEG5.port0
-HEX5[5] << hex_to_7seg:SEG5.port0
-HEX5[6] << hex_to_7seg:SEG5.port0
-LEDR[0] << formula_fsm:FSM.port5
-LEDR[1] << formula_fsm:FSM.port5
-LEDR[2] << formula_fsm:FSM.port5
-LEDR[3] << formula_fsm:FSM.port5
-LEDR[4] << formula_fsm:FSM.port5
-LEDR[5] << formula_fsm:FSM.port5
-LEDR[6] << formula_fsm:FSM.port5
-LEDR[7] << formula_fsm:FSM.port5
-LEDR[8] << formula_fsm:FSM.port5
-LEDR[9] << formula_fsm:FSM.port5
-
-
-|ex9|tick_50000:TICK0
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => count[12].CLK
-CLOCK_IN => count[13].CLK
-CLOCK_IN => count[14].CLK
-CLOCK_IN => count[15].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|formula_fsm:FSM
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => count[9].CLK
-clk => count[10].CLK
-clk => count[11].CLK
-clk => ledr[0]~reg0.CLK
-clk => ledr[1]~reg0.CLK
-clk => ledr[2]~reg0.CLK
-clk => ledr[3]~reg0.CLK
-clk => ledr[4]~reg0.CLK
-clk => ledr[5]~reg0.CLK
-clk => ledr[6]~reg0.CLK
-clk => ledr[7]~reg0.CLK
-clk => ledr[8]~reg0.CLK
-clk => ledr[9]~reg0.CLK
-clk => state~3.DATAIN
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
-start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
-ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|LFSR:LFSR0
-CLK => COUNT[1]~reg0.CLK
-CLK => COUNT[2]~reg0.CLK
-CLK => COUNT[3]~reg0.CLK
-CLK => COUNT[4]~reg0.CLK
-CLK => COUNT[5]~reg0.CLK
-CLK => COUNT[6]~reg0.CLK
-CLK => COUNT[7]~reg0.CLK
-en => COUNT[1]~reg0.ENA
-en => COUNT[2]~reg0.ENA
-en => COUNT[3]~reg0.ENA
-en => COUNT[4]~reg0.ENA
-en => COUNT[5]~reg0.ENA
-en => COUNT[6]~reg0.ENA
-en => COUNT[7]~reg0.ENA
-COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|delay:DEL0
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => count[9].CLK
-clk => count[10].CLK
-clk => count[11].CLK
-clk => count[12].CLK
-clk => count[13].CLK
-clk => state~4.DATAIN
-N[0] => count.DATAB
-N[1] => count.DATAB
-N[2] => count.DATAB
-N[3] => count.DATAB
-N[4] => count.DATAB
-N[5] => count.DATAB
-N[6] => count.DATAB
-N[7] => ~NO_FANOUT~
-N[8] => ~NO_FANOUT~
-N[9] => ~NO_FANOUT~
-N[10] => ~NO_FANOUT~
-N[11] => ~NO_FANOUT~
-N[12] => ~NO_FANOUT~
-N[13] => ~NO_FANOUT~
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector17.IN3
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector14.IN2
-time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|counter_16:COUNT0
-clock => count[0]~reg0.CLK
-clock => count[1]~reg0.CLK
-clock => count[2]~reg0.CLK
-clock => count[3]~reg0.CLK
-clock => count[4]~reg0.CLK
-clock => count[5]~reg0.CLK
-clock => count[6]~reg0.CLK
-clock => count[7]~reg0.CLK
-clock => count[8]~reg0.CLK
-clock => count[9]~reg0.CLK
-clock => count[10]~reg0.CLK
-clock => count[11]~reg0.CLK
-clock => count[12]~reg0.CLK
-clock => count[13]~reg0.CLK
-clock => count[14]~reg0.CLK
-clock => count[15]~reg0.CLK
-clock => state.CLK
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => state.OUTPUTSELECT
-stop => state.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD
-B[0] => BCD_0[0].DATAIN
-B[1] => w35[0].IN1
-B[2] => w30[0].IN1
-B[3] => w26[0].IN1
-B[4] => w22[0].IN1
-B[5] => w18[0].IN1
-B[6] => w15[0].IN1
-B[7] => w12[0].IN1
-B[8] => w9[0].IN1
-B[9] => w7[0].IN1
-B[10] => w5[0].IN1
-B[11] => w3[0].IN1
-B[12] => w2[0].IN1
-B[13] => w1[0].IN1
-B[14] => w1[1].IN1
-B[15] => w1[2].IN1
-BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
-BCD_0[1] <= add3_ge5:A35.port1
-BCD_0[2] <= add3_ge5:A35.port1
-BCD_0[3] <= add3_ge5:A35.port1
-BCD_1[0] <= add3_ge5:A35.port1
-BCD_1[1] <= add3_ge5:A34.port1
-BCD_1[2] <= add3_ge5:A34.port1
-BCD_1[3] <= add3_ge5:A34.port1
-BCD_2[0] <= add3_ge5:A34.port1
-BCD_2[1] <= add3_ge5:A33.port1
-BCD_2[2] <= add3_ge5:A33.port1
-BCD_2[3] <= add3_ge5:A33.port1
-BCD_3[0] <= add3_ge5:A33.port1
-BCD_3[1] <= add3_ge5:A32.port1
-BCD_3[2] <= add3_ge5:A32.port1
-BCD_3[3] <= add3_ge5:A32.port1
-BCD_4[0] <= add3_ge5:A32.port1
-BCD_4[1] <= add3_ge5:A31.port1
-BCD_4[2] <= add3_ge5:A31.port1
-BCD_4[3] <= add3_ge5:A31.port1
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A1
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A2
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A3
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A4
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A5
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A6
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A7
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A8
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A9
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A10
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A11
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A12
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A13
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A14
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A15
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A16
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A17
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A18
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A19
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A20
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A21
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A22
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A23
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A24
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A25
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A26
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A27
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A28
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A29
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A30
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A31
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A32
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A33
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A34
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A35
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|hex_to_7seg:SEG0
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG1
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG2
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG3
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG4
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG5
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
+|ex9
+CLOCK_50 => CLOCK_50.IN1
+KEY[0] => _.IN1
+KEY[1] => ~NO_FANOUT~
+KEY[2] => ~NO_FANOUT~
+KEY[3] => _.IN1
+HEX0[0] << hex_to_7seg:SEG0.port0
+HEX0[1] << hex_to_7seg:SEG0.port0
+HEX0[2] << hex_to_7seg:SEG0.port0
+HEX0[3] << hex_to_7seg:SEG0.port0
+HEX0[4] << hex_to_7seg:SEG0.port0
+HEX0[5] << hex_to_7seg:SEG0.port0
+HEX0[6] << hex_to_7seg:SEG0.port0
+HEX1[0] << hex_to_7seg:SEG1.port0
+HEX1[1] << hex_to_7seg:SEG1.port0
+HEX1[2] << hex_to_7seg:SEG1.port0
+HEX1[3] << hex_to_7seg:SEG1.port0
+HEX1[4] << hex_to_7seg:SEG1.port0
+HEX1[5] << hex_to_7seg:SEG1.port0
+HEX1[6] << hex_to_7seg:SEG1.port0
+HEX2[0] << hex_to_7seg:SEG2.port0
+HEX2[1] << hex_to_7seg:SEG2.port0
+HEX2[2] << hex_to_7seg:SEG2.port0
+HEX2[3] << hex_to_7seg:SEG2.port0
+HEX2[4] << hex_to_7seg:SEG2.port0
+HEX2[5] << hex_to_7seg:SEG2.port0
+HEX2[6] << hex_to_7seg:SEG2.port0
+HEX3[0] << hex_to_7seg:SEG3.port0
+HEX3[1] << hex_to_7seg:SEG3.port0
+HEX3[2] << hex_to_7seg:SEG3.port0
+HEX3[3] << hex_to_7seg:SEG3.port0
+HEX3[4] << hex_to_7seg:SEG3.port0
+HEX3[5] << hex_to_7seg:SEG3.port0
+HEX3[6] << hex_to_7seg:SEG3.port0
+HEX4[0] << hex_to_7seg:SEG4.port0
+HEX4[1] << hex_to_7seg:SEG4.port0
+HEX4[2] << hex_to_7seg:SEG4.port0
+HEX4[3] << hex_to_7seg:SEG4.port0
+HEX4[4] << hex_to_7seg:SEG4.port0
+HEX4[5] << hex_to_7seg:SEG4.port0
+HEX4[6] << hex_to_7seg:SEG4.port0
+HEX5[0] << hex_to_7seg:SEG5.port0
+HEX5[1] << hex_to_7seg:SEG5.port0
+HEX5[2] << hex_to_7seg:SEG5.port0
+HEX5[3] << hex_to_7seg:SEG5.port0
+HEX5[4] << hex_to_7seg:SEG5.port0
+HEX5[5] << hex_to_7seg:SEG5.port0
+HEX5[6] << hex_to_7seg:SEG5.port0
+LEDR[0] << formula_fsm:FSM.port5
+LEDR[1] << formula_fsm:FSM.port5
+LEDR[2] << formula_fsm:FSM.port5
+LEDR[3] << formula_fsm:FSM.port5
+LEDR[4] << formula_fsm:FSM.port5
+LEDR[5] << formula_fsm:FSM.port5
+LEDR[6] << formula_fsm:FSM.port5
+LEDR[7] << formula_fsm:FSM.port5
+LEDR[8] << formula_fsm:FSM.port5
+LEDR[9] << formula_fsm:FSM.port5
+
+
+|ex9|tick_50000:TICK0
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => count[12].CLK
+CLOCK_IN => count[13].CLK
+CLOCK_IN => count[14].CLK
+CLOCK_IN => count[15].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|formula_fsm:FSM
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => count[10].CLK
+clk => count[11].CLK
+clk => ledr[0]~reg0.CLK
+clk => ledr[1]~reg0.CLK
+clk => ledr[2]~reg0.CLK
+clk => ledr[3]~reg0.CLK
+clk => ledr[4]~reg0.CLK
+clk => ledr[5]~reg0.CLK
+clk => ledr[6]~reg0.CLK
+clk => ledr[7]~reg0.CLK
+clk => ledr[8]~reg0.CLK
+clk => ledr[9]~reg0.CLK
+clk => state~3.DATAIN
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
+start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
+ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|LFSR:LFSR0
+CLK => COUNT[1]~reg0.CLK
+CLK => COUNT[2]~reg0.CLK
+CLK => COUNT[3]~reg0.CLK
+CLK => COUNT[4]~reg0.CLK
+CLK => COUNT[5]~reg0.CLK
+CLK => COUNT[6]~reg0.CLK
+CLK => COUNT[7]~reg0.CLK
+en => COUNT[1]~reg0.ENA
+en => COUNT[2]~reg0.ENA
+en => COUNT[3]~reg0.ENA
+en => COUNT[4]~reg0.ENA
+en => COUNT[5]~reg0.ENA
+en => COUNT[6]~reg0.ENA
+en => COUNT[7]~reg0.ENA
+COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|delay:DEL0
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => count[10].CLK
+clk => count[11].CLK
+clk => count[12].CLK
+clk => count[13].CLK
+clk => state~4.DATAIN
+N[0] => count.DATAB
+N[1] => count.DATAB
+N[2] => count.DATAB
+N[3] => count.DATAB
+N[4] => count.DATAB
+N[5] => count.DATAB
+N[6] => count.DATAB
+N[7] => ~NO_FANOUT~
+N[8] => ~NO_FANOUT~
+N[9] => ~NO_FANOUT~
+N[10] => ~NO_FANOUT~
+N[11] => ~NO_FANOUT~
+N[12] => ~NO_FANOUT~
+N[13] => ~NO_FANOUT~
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => Selector17.IN3
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => Selector14.IN2
+time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|counter_16:COUNT0
+clock => count[0]~reg0.CLK
+clock => count[1]~reg0.CLK
+clock => count[2]~reg0.CLK
+clock => count[3]~reg0.CLK
+clock => count[4]~reg0.CLK
+clock => count[5]~reg0.CLK
+clock => count[6]~reg0.CLK
+clock => count[7]~reg0.CLK
+clock => count[8]~reg0.CLK
+clock => count[9]~reg0.CLK
+clock => count[10]~reg0.CLK
+clock => count[11]~reg0.CLK
+clock => count[12]~reg0.CLK
+clock => count[13]~reg0.CLK
+clock => count[14]~reg0.CLK
+clock => count[15]~reg0.CLK
+clock => state.CLK
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => state.OUTPUTSELECT
+stop => state.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD
+B[0] => BCD_0[0].DATAIN
+B[1] => w35[0].IN1
+B[2] => w30[0].IN1
+B[3] => w26[0].IN1
+B[4] => w22[0].IN1
+B[5] => w18[0].IN1
+B[6] => w15[0].IN1
+B[7] => w12[0].IN1
+B[8] => w9[0].IN1
+B[9] => w7[0].IN1
+B[10] => w5[0].IN1
+B[11] => w3[0].IN1
+B[12] => w2[0].IN1
+B[13] => w1[0].IN1
+B[14] => w1[1].IN1
+B[15] => w1[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A35.port1
+BCD_0[2] <= add3_ge5:A35.port1
+BCD_0[3] <= add3_ge5:A35.port1
+BCD_1[0] <= add3_ge5:A35.port1
+BCD_1[1] <= add3_ge5:A34.port1
+BCD_1[2] <= add3_ge5:A34.port1
+BCD_1[3] <= add3_ge5:A34.port1
+BCD_2[0] <= add3_ge5:A34.port1
+BCD_2[1] <= add3_ge5:A33.port1
+BCD_2[2] <= add3_ge5:A33.port1
+BCD_2[3] <= add3_ge5:A33.port1
+BCD_3[0] <= add3_ge5:A33.port1
+BCD_3[1] <= add3_ge5:A32.port1
+BCD_3[2] <= add3_ge5:A32.port1
+BCD_3[3] <= add3_ge5:A32.port1
+BCD_4[0] <= add3_ge5:A32.port1
+BCD_4[1] <= add3_ge5:A31.port1
+BCD_4[2] <= add3_ge5:A31.port1
+BCD_4[3] <= add3_ge5:A31.port1
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A1
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A2
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A3
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A4
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A5
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A6
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A7
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A8
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A9
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A10
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A11
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A12
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A13
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A14
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A15
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A16
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A17
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A18
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A19
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A20
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A21
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A22
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A23
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A24
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A25
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A26
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A27
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A28
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A29
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A30
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A31
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A32
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A33
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A34
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A35
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG3
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG4
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG5
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_2/ex9/db/ex9.lpc.html b/part_2/ex9/db/ex9.lpc.html
index 66398b2..795349d 100644
--- a/part_2/ex9/db/ex9.lpc.html
+++ b/part_2/ex9/db/ex9.lpc.html
@@ -1,770 +1,770 @@
-<TABLE>
-<TR  bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-<TR >
-<TD >SEG5</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >7</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG3</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG1</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A35</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A34</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A33</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A32</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A31</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A30</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A29</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A28</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A27</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A26</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A25</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A24</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A23</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A22</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A21</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A20</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A19</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A18</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A17</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A16</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A15</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A14</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A13</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A12</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A11</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A10</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A9</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A8</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A7</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A6</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A5</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A4</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A3</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD</TD>
-<TD >16</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >20</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >COUNT0</TD>
-<TD >3</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >16</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >DEL0</TD>
-<TD >16</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >1</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >LFSR0</TD>
-<TD >2</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >FSM</TD>
-<TD >3</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >12</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >TICK0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-</TABLE>
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG5</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >7</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A35</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A34</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A33</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A32</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A31</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A30</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A29</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A28</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A27</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A26</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A25</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A24</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A23</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A22</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A21</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A20</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A19</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A18</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A17</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A16</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A15</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A14</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A13</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A12</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A11</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A10</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A9</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A4</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >COUNT0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >DEL0</TD>
+<TD >16</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >1</TD>
+<TD >7</TD>
+<TD >7</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >LFSR0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >FSM</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >TICK0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_2/ex9/db/ex9.lpc.txt b/part_2/ex9/db/ex9.lpc.txt
index d85a84b..538b3bf 100644
--- a/part_2/ex9/db/ex9.lpc.txt
+++ b/part_2/ex9/db/ex9.lpc.txt
@@ -1,53 +1,53 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; SEG5      ; 4     ; 4              ; 0            ; 4              ; 7      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG4      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG3      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD       ; 16    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; COUNT0    ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; FSM       ; 3     ; 0              ; 0            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG5      ; 4     ; 4              ; 0            ; 4              ; 7      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG4      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG3      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD       ; 16    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; COUNT0    ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; FSM       ; 3     ; 0              ; 0            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_2/ex9/db/ex9.map.logdb b/part_2/ex9/db/ex9.map.logdb
index 626799f..d45424f 100644
--- a/part_2/ex9/db/ex9.map.logdb
+++ b/part_2/ex9/db/ex9.map.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex9/db/ex9.map.qmsg b/part_2/ex9/db/ex9.map.qmsg
index 6476def..0c6e7c8 100644
--- a/part_2/ex9/db/ex9.map.qmsg
+++ b/part_2/ex9/db/ex9.map.qmsg
@@ -1,73 +1,73 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112434281 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112434284 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:07:13 2016 " "Processing started: Wed Dec 07 12:07:13 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112434284 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112434284 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112434284 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481112434902 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481112434902 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443515 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443515 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443519 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443519 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443523 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443523 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481112443527 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443528 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443528 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443536 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443536 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443536 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443540 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443540 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443543 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443548 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443548 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443548 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443552 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443552 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443555 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443555 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481112443627 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443633 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443637 ""}
-{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
-{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
-{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443643 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 20 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443647 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481112443648 "|ex9|delay:DEL0"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 22 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443692 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443714 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443719 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443728 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481112444476 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481112444661 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481112444740 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481112445211 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112445296 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481112445625 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112445625 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112446084 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112446084 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481112446084 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "354 " "Implemented 354 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481112446087 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481112446087 ""} { "Info" "ICUT_CUT_TM_LCELLS" "297 " "Implemented 297 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481112446087 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481112446087 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "918 " "Peak virtual memory: 918 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:07:26 2016 " "Processing ended: Wed Dec 07 12:07:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112446141 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112434281 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112434284 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:07:13 2016 " "Processing started: Wed Dec 07 12:07:13 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112434284 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112434284 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112434284 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481112434902 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481112434902 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443515 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443515 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443519 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443519 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443523 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443523 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481112443527 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443528 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443528 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443536 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443536 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443536 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443540 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443540 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443543 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443548 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443548 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443548 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443552 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443552 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443555 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443555 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481112443627 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443633 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443637 ""}
+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443643 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 20 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443647 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481112443648 "|ex9|delay:DEL0"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 22 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443692 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443714 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443719 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443728 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481112444476 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481112444661 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481112444740 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481112445211 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112445296 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481112445625 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112445625 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112446084 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112446084 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481112446084 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "354 " "Implemented 354 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481112446087 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481112446087 ""} { "Info" "ICUT_CUT_TM_LCELLS" "297 " "Implemented 297 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481112446087 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481112446087 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "918 " "Peak virtual memory: 918 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:07:26 2016 " "Processing ended: Wed Dec 07 12:07:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112446141 ""}
diff --git a/part_2/ex9/db/ex9.map_bb.logdb b/part_2/ex9/db/ex9.map_bb.logdb
index 626799f..d45424f 100644
--- a/part_2/ex9/db/ex9.map_bb.logdb
+++ b/part_2/ex9/db/ex9.map_bb.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex9/db/ex9.smart_action.txt b/part_2/ex9/db/ex9.smart_action.txt
index c8e8a13..437a63e 100644
--- a/part_2/ex9/db/ex9.smart_action.txt
+++ b/part_2/ex9/db/ex9.smart_action.txt
@@ -1 +1 @@
-DONE
+DONE
diff --git a/part_2/ex9/db/ex9.smp_dump.txt b/part_2/ex9/db/ex9.smp_dump.txt
index bd2b24e..26e74f6 100644
--- a/part_2/ex9/db/ex9.smp_dump.txt
+++ b/part_2/ex9/db/ex9.smp_dump.txt
@@ -1,13 +1,13 @@
-
-State Machine - |ex9|delay:DEL0|state
-Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 
-state.IDLE 0 0 0 0 
-state.COUNTING 0 0 1 1 
-state.TIME_OUT 0 1 0 1 
-state.WAIT_LOW 1 0 0 1 
-
-State Machine - |ex9|formula_fsm:FSM|state
-Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 
-state.WAIT_TRIGGER 0 0 0 
-state.LIGHT_UP_LEDS 1 0 1 
-state.WAIT_FOR_TIMEOUT 1 1 0 
+
+State Machine - |ex9|delay:DEL0|state
+Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 
+state.IDLE 0 0 0 0 
+state.COUNTING 0 0 1 1 
+state.TIME_OUT 0 1 0 1 
+state.WAIT_LOW 1 0 0 1 
+
+State Machine - |ex9|formula_fsm:FSM|state
+Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 
+state.WAIT_TRIGGER 0 0 0 
+state.LIGHT_UP_LEDS 1 0 1 
+state.WAIT_FOR_TIMEOUT 1 1 0 
diff --git a/part_2/ex9/db/ex9.sta.qmsg b/part_2/ex9/db/ex9.sta.qmsg
index 0b9471d..aab3a60 100644
--- a/part_2/ex9/db/ex9.sta.qmsg
+++ b/part_2/ex9/db/ex9.sta.qmsg
@@ -1,53 +1,53 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112502374 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112502377 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:08:21 2016 " "Processing started: Wed Dec 07 12:08:21 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112502377 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112502377 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112502378 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112502505 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503130 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503130 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503180 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503180 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503779 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503861 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503862 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503864 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503869 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503894 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112503895 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112503939 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112503972 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503972 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.462 " "Worst-case setup slack is -3.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT  " "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.047             -40.775 CLOCK_50  " "   -2.047             -40.775 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503984 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.179               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.179               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.385               0.000 CLOCK_50  " "    0.385               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504002 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504013 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504023 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.637 " "Worst-case minimum pulse width slack is -0.637" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.637             -18.132 CLOCK_50  " "   -0.637             -18.132 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504032 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112504054 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504090 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505120 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505353 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112505409 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505409 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.416 " "Worst-case setup slack is -3.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT  " "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.323             -41.799 CLOCK_50  " "   -2.323             -41.799 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505436 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.193               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.193               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.405               0.000 CLOCK_50  " "    0.405               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505454 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505465 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505488 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.689 " "Worst-case minimum pulse width slack is -0.689" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.689             -16.816 CLOCK_50  " "   -0.689             -16.816 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505519 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112505541 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505804 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506731 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506844 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112506847 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506847 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.794 " "Worst-case setup slack is -1.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT  " "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.918             -13.912 CLOCK_50  " "   -0.918             -13.912 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506855 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.020 " "Worst-case hold slack is -0.020" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT  " "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.185               0.000 CLOCK_50  " "    0.185               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506866 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506875 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506884 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.740 " "Worst-case minimum pulse width slack is -0.740" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.740             -12.957 CLOCK_50  " "   -0.740             -12.957 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT  " "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506893 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112506923 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507323 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112507325 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507325 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.581 " "Worst-case setup slack is -1.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT  " "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.868             -11.639 CLOCK_50  " "   -0.868             -11.639 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507338 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.021 " "Worst-case hold slack is -0.021" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT  " "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177               0.000 CLOCK_50  " "    0.177               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507349 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507359 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507368 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.789 " "Worst-case minimum pulse width slack is -0.789" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.789             -15.486 CLOCK_50  " "   -0.789             -15.486 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.024               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507377 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112509824 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112509826 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1213 " "Peak virtual memory: 1213 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:30 2016 " "Processing ended: Wed Dec 07 12:08:30 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112510016 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112502374 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112502377 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:08:21 2016 " "Processing started: Wed Dec 07 12:08:21 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112502377 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112502377 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112502378 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112502505 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503130 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503130 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503180 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503180 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503779 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503861 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503862 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503864 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503869 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503894 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112503895 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112503939 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112503972 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503972 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.462 " "Worst-case setup slack is -3.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT  " "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.047             -40.775 CLOCK_50  " "   -2.047             -40.775 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503984 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.179               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.179               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.385               0.000 CLOCK_50  " "    0.385               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504002 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504013 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504023 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.637 " "Worst-case minimum pulse width slack is -0.637" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.637             -18.132 CLOCK_50  " "   -0.637             -18.132 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504032 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112504054 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504090 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505120 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505353 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112505409 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505409 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.416 " "Worst-case setup slack is -3.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT  " "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.323             -41.799 CLOCK_50  " "   -2.323             -41.799 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505436 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.193               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.193               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.405               0.000 CLOCK_50  " "    0.405               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505454 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505465 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505488 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.689 " "Worst-case minimum pulse width slack is -0.689" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.689             -16.816 CLOCK_50  " "   -0.689             -16.816 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505519 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112505541 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505804 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506731 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506844 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112506847 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506847 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.794 " "Worst-case setup slack is -1.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT  " "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.918             -13.912 CLOCK_50  " "   -0.918             -13.912 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506855 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.020 " "Worst-case hold slack is -0.020" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT  " "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.185               0.000 CLOCK_50  " "    0.185               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506866 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506875 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506884 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.740 " "Worst-case minimum pulse width slack is -0.740" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.740             -12.957 CLOCK_50  " "   -0.740             -12.957 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT  " "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506893 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112506923 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507323 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112507325 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507325 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.581 " "Worst-case setup slack is -1.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT  " "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.868             -11.639 CLOCK_50  " "   -0.868             -11.639 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507338 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.021 " "Worst-case hold slack is -0.021" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT  " "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177               0.000 CLOCK_50  " "    0.177               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507349 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507359 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507368 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.789 " "Worst-case minimum pulse width slack is -0.789" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.789             -15.486 CLOCK_50  " "   -0.789             -15.486 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.024               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507377 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112509824 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112509826 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1213 " "Peak virtual memory: 1213 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:30 2016 " "Processing ended: Wed Dec 07 12:08:30 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112510016 ""}
diff --git a/part_2/ex9/db/ex9.tmw_info b/part_2/ex9/db/ex9.tmw_info
index a2d0efe..b5caf45 100644
--- a/part_2/ex9/db/ex9.tmw_info
+++ b/part_2/ex9/db/ex9.tmw_info
@@ -1,6 +1,6 @@
-start_full_compilation:s:00:01:18
-start_analysis_synthesis:s:00:00:19-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:40-start_full_compilation
-start_assembler:s:00:00:09-start_full_compilation
-start_timing_analyzer:s:00:00:10-start_full_compilation
+start_full_compilation:s:00:01:18
+start_analysis_synthesis:s:00:00:19-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:40-start_full_compilation
+start_assembler:s:00:00:09-start_full_compilation
+start_timing_analyzer:s:00:00:10-start_full_compilation
diff --git a/part_2/ex9/db/ex9_partition_pins.json b/part_2/ex9/db/ex9_partition_pins.json
index f8c0864..701d3b6 100644
--- a/part_2/ex9/db/ex9_partition_pins.json
+++ b/part_2/ex9/db/ex9_partition_pins.json
@@ -1,201 +1,201 @@
-{
-	"partitions" : [
-		{
-			"name" : "Top",
-			"pins" : [
-				{
-					"name" : "HEX0[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[6]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[0]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[1]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[2]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[3]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[4]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[5]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[6]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[7]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[8]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[9]",
-					"strict" : false
-				},
-				{
-					"name" : "KEY[0]",
-					"strict" : false
-				},
-				{
-					"name" : "CLOCK_50",
-					"strict" : false
-				},
-				{
-					"name" : "KEY[3]",
-					"strict" : false
-				}
-			]
-		}
-	]
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "HEX0[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[6]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[0]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[1]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[2]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[3]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[4]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[5]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[6]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[7]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[8]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[9]",
+					"strict" : false
+				},
+				{
+					"name" : "KEY[0]",
+					"strict" : false
+				},
+				{
+					"name" : "CLOCK_50",
+					"strict" : false
+				},
+				{
+					"name" : "KEY[3]",
+					"strict" : false
+				}
+			]
+		}
+	]
 }
 \ No newline at end of file
diff --git a/part_2/ex9/db/prev_cmp_ex9.qmsg b/part_2/ex9/db/prev_cmp_ex9.qmsg
index 6b47f34..5a19f5a 100644
--- a/part_2/ex9/db/prev_cmp_ex9.qmsg
+++ b/part_2/ex9/db/prev_cmp_ex9.qmsg
@@ -1,185 +1,185 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112317473 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112317476 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:05:17 2016 " "Processing started: Wed Dec 07 12:05:17 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112317476 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112317476 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112317476 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481112318034 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481112318034 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326529 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326529 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326533 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326533 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326538 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326538 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481112326542 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326544 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326544 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326548 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326549 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326549 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326557 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326557 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326564 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326564 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326564 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326568 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326568 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326568 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326568 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326568 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326569 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326569 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326569 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326569 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326570 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326570 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326574 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326574 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326579 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326579 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481112326688 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326695 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326701 ""}
-{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481112326706 "|ex9|formula_fsm:FSM"}
-{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481112326707 "|ex9|formula_fsm:FSM"}
-{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326707 "|ex9|formula_fsm:FSM"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326708 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 20 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326714 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481112326738 "|ex9|delay:DEL0"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 22 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326740 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326785 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326806 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326832 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481112327766 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481112327986 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481112328082 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481112328609 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112328762 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481112329208 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112329208 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112330179 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112330179 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481112330179 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "354 " "Implemented 354 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481112330200 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481112330200 ""} { "Info" "ICUT_CUT_TM_LCELLS" "297 " "Implemented 297 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481112330200 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481112330200 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112330427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:05:30 2016 " "Processing ended: Wed Dec 07 12:05:30 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112330427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112330427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112330427 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112330427 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1481112333521 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112333522 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:05:32 2016 " "Processing started: Wed Dec 07 12:05:32 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112333522 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1481112333522 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1481112333522 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1481112333753 ""}
-{ "Info" "0" "" "Project  = ex9" {  } {  } 0 0 "Project  = ex9" 0 0 "Fitter" 0 0 1481112333754 ""}
-{ "Info" "0" "" "Revision = ex9" {  } {  } 0 0 "Revision = ex9" 0 0 "Fitter" 0 0 1481112333754 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481112333946 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481112333947 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481112334254 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112334333 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112334333 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481112334757 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481112335135 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481112345503 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481112345612 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481112345612 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112345612 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481112345632 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112345633 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112345634 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481112345634 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481112345635 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481112345636 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481112346514 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481112346515 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481112346516 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481112346520 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481112346520 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481112346522 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481112346527 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481112346527 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481112346527 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481112346607 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112346622 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481112351634 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481112351926 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112352867 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481112353762 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481112354713 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112354713 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481112356114 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481112360790 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481112360790 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481112362627 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481112362627 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112362631 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.57 " "Total time spent on timing analysis during the Fitter is 0.57 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481112364677 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112364723 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112365265 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112365265 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112365772 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112368616 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481112368928 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481112369078 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2592 " "Peak virtual memory: 2592 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112371433 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:06:11 2016 " "Processing ended: Wed Dec 07 12:06:11 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112371433 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:39 " "Elapsed time: 00:00:39" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112371433 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:02 " "Total CPU time (on all processors): 00:01:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112371433 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481112371433 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1481112377103 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112377107 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:06:16 2016 " "Processing started: Wed Dec 07 12:06:16 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112377107 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481112377107 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481112377107 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481112377967 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481112383265 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "895 " "Peak virtual memory: 895 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112386576 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:06:26 2016 " "Processing ended: Wed Dec 07 12:06:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112386576 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112386576 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112386576 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481112386576 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1481112387598 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1481112388508 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112388509 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:06:27 2016 " "Processing started: Wed Dec 07 12:06:27 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112388509 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112388509 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112388510 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112388686 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112389445 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112389445 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112389495 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112389495 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390120 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390330 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390331 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112390336 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112390336 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112390336 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390336 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390342 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390373 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112390381 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112390450 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112390500 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390500 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.462 " "Worst-case setup slack is -3.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT  " "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.047             -40.775 CLOCK_50  " "   -2.047             -40.775 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390521 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390521 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.179               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.179               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.385               0.000 CLOCK_50  " "    0.385               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390562 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390562 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390586 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390613 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.637 " "Worst-case minimum pulse width slack is -0.637" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.637             -18.132 CLOCK_50  " "   -0.637             -18.132 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390635 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390635 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112390696 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390745 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112391851 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392004 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112392029 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392029 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.416 " "Worst-case setup slack is -3.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT  " "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.323             -41.799 CLOCK_50  " "   -2.323             -41.799 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392048 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392048 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.193               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.193               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.405               0.000 CLOCK_50  " "    0.405               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392078 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392078 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392096 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392115 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.689 " "Worst-case minimum pulse width slack is -0.689" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.689             -16.816 CLOCK_50  " "   -0.689             -16.816 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392134 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392134 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112392191 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392512 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393412 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393589 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112393593 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393593 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.794 " "Worst-case setup slack is -1.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT  " "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.918             -13.912 CLOCK_50  " "   -0.918             -13.912 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393616 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393616 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.020 " "Worst-case hold slack is -0.020" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT  " "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.185               0.000 CLOCK_50  " "    0.185               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393639 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393639 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393658 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393681 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.740 " "Worst-case minimum pulse width slack is -0.740" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.740             -12.957 CLOCK_50  " "   -0.740             -12.957 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT  " "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393703 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393703 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112393750 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394099 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112394101 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394101 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.581 " "Worst-case setup slack is -1.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT  " "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.868             -11.639 CLOCK_50  " "   -0.868             -11.639 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394126 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394126 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.021 " "Worst-case hold slack is -0.021" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394177 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394177 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT  " "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394177 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394177 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177               0.000 CLOCK_50  " "    0.177               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394177 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394177 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394218 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394241 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.789 " "Worst-case minimum pulse width slack is -0.789" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.789             -15.486 CLOCK_50  " "   -0.789             -15.486 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.024               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394267 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394267 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112396814 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112396816 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1212 " "Peak virtual memory: 1212 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112397064 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:06:37 2016 " "Processing ended: Wed Dec 07 12:06:37 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112397064 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112397064 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112397064 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112397064 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 53 s " "Quartus Prime Full Compilation was successful. 0 errors, 53 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112399351 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112317473 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112317476 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:05:17 2016 " "Processing started: Wed Dec 07 12:05:17 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112317476 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112317476 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112317476 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481112318034 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481112318034 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326529 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326529 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326533 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326533 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326538 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326538 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481112326542 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326544 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326548 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326549 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326549 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326557 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326557 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326564 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326564 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326564 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326565 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326566 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326567 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326568 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326568 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326568 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326568 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326568 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326569 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326569 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326569 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112326569 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326570 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326570 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326574 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326574 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112326579 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326579 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481112326688 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326695 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326701 ""}
+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481112326706 "|ex9|formula_fsm:FSM"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481112326707 "|ex9|formula_fsm:FSM"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112326707 "|ex9|formula_fsm:FSM"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326708 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 20 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326714 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481112326738 "|ex9|delay:DEL0"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 22 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326740 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326785 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326806 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112326832 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481112327766 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112327986 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481112327986 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481112328082 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481112328609 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112328762 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481112329208 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112329208 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112330179 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112330179 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481112330179 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "354 " "Implemented 354 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481112330200 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481112330200 ""} { "Info" "ICUT_CUT_TM_LCELLS" "297 " "Implemented 297 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481112330200 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481112330200 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112330427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:05:30 2016 " "Processing ended: Wed Dec 07 12:05:30 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112330427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112330427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112330427 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112330427 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1481112333521 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112333522 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:05:32 2016 " "Processing started: Wed Dec 07 12:05:32 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112333522 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1481112333522 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1481112333522 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1481112333753 ""}
+{ "Info" "0" "" "Project  = ex9" {  } {  } 0 0 "Project  = ex9" 0 0 "Fitter" 0 0 1481112333754 ""}
+{ "Info" "0" "" "Revision = ex9" {  } {  } 0 0 "Revision = ex9" 0 0 "Fitter" 0 0 1481112333754 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481112333946 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481112333947 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481112334254 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112334333 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112334333 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481112334757 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481112335135 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481112345503 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481112345612 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481112345612 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112345612 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481112345632 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112345633 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112345634 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481112345634 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481112345635 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481112345636 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481112346514 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481112346515 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481112346516 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481112346520 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481112346520 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481112346522 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481112346527 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481112346527 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481112346527 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112346607 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481112346607 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112346622 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481112351634 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481112351926 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112352867 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481112353762 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481112354713 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112354713 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481112356114 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481112360790 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481112360790 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481112362627 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481112362627 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112362631 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.57 " "Total time spent on timing analysis during the Fitter is 0.57 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481112364677 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112364723 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112365265 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112365265 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112365772 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112368616 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481112368928 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481112369078 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2592 " "Peak virtual memory: 2592 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112371433 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:06:11 2016 " "Processing ended: Wed Dec 07 12:06:11 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112371433 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:39 " "Elapsed time: 00:00:39" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112371433 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:02 " "Total CPU time (on all processors): 00:01:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112371433 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481112371433 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1481112377103 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112377107 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:06:16 2016 " "Processing started: Wed Dec 07 12:06:16 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112377107 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481112377107 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481112377107 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481112377967 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481112383265 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "895 " "Peak virtual memory: 895 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112386576 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:06:26 2016 " "Processing ended: Wed Dec 07 12:06:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112386576 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112386576 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112386576 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481112386576 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1481112387598 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1481112388508 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112388509 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:06:27 2016 " "Processing started: Wed Dec 07 12:06:27 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112388509 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112388509 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112388510 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112388686 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112389445 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112389445 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112389495 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112389495 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390120 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390330 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390331 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112390336 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112390336 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112390336 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390336 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390342 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390373 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112390381 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112390450 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112390500 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390500 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.462 " "Worst-case setup slack is -3.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT  " "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.047             -40.775 CLOCK_50  " "   -2.047             -40.775 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390521 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390521 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.179               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.179               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.385               0.000 CLOCK_50  " "    0.385               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390562 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390562 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390586 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390613 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.637 " "Worst-case minimum pulse width slack is -0.637" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.637             -18.132 CLOCK_50  " "   -0.637             -18.132 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112390635 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390635 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112390696 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112390745 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112391851 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392004 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112392029 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392029 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.416 " "Worst-case setup slack is -3.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT  " "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.323             -41.799 CLOCK_50  " "   -2.323             -41.799 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392048 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392048 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.193               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.193               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.405               0.000 CLOCK_50  " "    0.405               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392078 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392078 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392096 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392115 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.689 " "Worst-case minimum pulse width slack is -0.689" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.689             -16.816 CLOCK_50  " "   -0.689             -16.816 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392134 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112392134 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392134 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112392191 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112392512 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393412 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393589 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112393593 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393593 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.794 " "Worst-case setup slack is -1.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT  " "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.918             -13.912 CLOCK_50  " "   -0.918             -13.912 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393616 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393616 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.020 " "Worst-case hold slack is -0.020" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT  " "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.185               0.000 CLOCK_50  " "    0.185               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393639 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393639 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393658 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393681 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.740 " "Worst-case minimum pulse width slack is -0.740" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.740             -12.957 CLOCK_50  " "   -0.740             -12.957 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT  " "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393703 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112393703 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112393703 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112393750 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394099 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112394101 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394101 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.581 " "Worst-case setup slack is -1.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT  " "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.868             -11.639 CLOCK_50  " "   -0.868             -11.639 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394126 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394126 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.021 " "Worst-case hold slack is -0.021" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394177 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394177 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT  " "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394177 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394177 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177               0.000 CLOCK_50  " "    0.177               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394177 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394177 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394218 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394241 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.789 " "Worst-case minimum pulse width slack is -0.789" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.789             -15.486 CLOCK_50  " "   -0.789             -15.486 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.024               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112394267 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112394267 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112396814 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112396816 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1212 " "Peak virtual memory: 1212 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112397064 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:06:37 2016 " "Processing ended: Wed Dec 07 12:06:37 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112397064 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112397064 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112397064 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112397064 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 53 s " "Quartus Prime Full Compilation was successful. 0 errors, 53 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112399351 ""}
diff --git a/part_2/ex9/ex9.qpf b/part_2/ex9/ex9.qpf
index 8e80747..28b4ce8 100644
--- a/part_2/ex9/ex9.qpf
+++ b/part_2/ex9/ex9.qpf
@@ -1,31 +1,31 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, the Altera Quartus Prime License Agreement,
-# the Altera MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Altera and sold by Altera or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-# Date created = 10:28:00  November 25, 2016
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "16.0"
-DATE = "10:28:00  November 25, 2016"
-
-# Revisions
-
-PROJECT_REVISION = "ex9"
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 10:28:00  November 25, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.0"
+DATE = "10:28:00  November 25, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ex9"
diff --git a/part_2/ex9/ex9.qsf b/part_2/ex9/ex9.qsf
index 9b3ee1f..af789d5 100644
--- a/part_2/ex9/ex9.qsf
+++ b/part_2/ex9/ex9.qsf
@@ -1,274 +1,274 @@
-#============================================================
-# CLOCK
-#============================================================
-set_location_assignment PIN_AF14 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# Add-on Card Interface Pins
-#============================================================
-set_location_assignment PIN_AJ20 -to PWM_OUT
-set_location_assignment PIN_AK21 -to DAC_LD
-set_location_assignment PIN_AD20 -to DAC_CS
-set_location_assignment PIN_AF20 -to DAC_SCK
-set_location_assignment PIN_AF21 -to ADC_SCK
-set_location_assignment PIN_AG21 -to ADC_SDI
-set_location_assignment PIN_AG20 -to ADC_CS
-set_location_assignment PIN_AG18 -to DAC_SDI
-set_location_assignment PIN_AJ21 -to ADC_SDO
-set_location_assignment PIN_Y17 -to OLED_CS
-set_location_assignment PIN_Y18 -to OLED_RST
-set_location_assignment PIN_AK18 -to OLED_DC
-set_location_assignment PIN_AJ19 -to OLED_CLK
-set_location_assignment PIN_AJ16 -to OLED_DATA
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
-
-
-#============================================================
-# HEX0
-#============================================================
-set_location_assignment PIN_AE26 -to HEX0[0]
-set_location_assignment PIN_AE27 -to HEX0[1]
-set_location_assignment PIN_AE28 -to HEX0[2]
-set_location_assignment PIN_AG27 -to HEX0[3]
-set_location_assignment PIN_AF28 -to HEX0[4]
-set_location_assignment PIN_AG28 -to HEX0[5]
-set_location_assignment PIN_AH28 -to HEX0[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
-
-#============================================================
-# HEX1
-#============================================================
-set_location_assignment PIN_AJ29 -to HEX1[0]
-set_location_assignment PIN_AH29 -to HEX1[1]
-set_location_assignment PIN_AH30 -to HEX1[2]
-set_location_assignment PIN_AG30 -to HEX1[3]
-set_location_assignment PIN_AF29 -to HEX1[4]
-set_location_assignment PIN_AF30 -to HEX1[5]
-set_location_assignment PIN_AD27 -to HEX1[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
-
-#============================================================
-# HEX2
-#============================================================
-set_location_assignment PIN_AB23 -to HEX2[0]
-set_location_assignment PIN_AE29 -to HEX2[1]
-set_location_assignment PIN_AD29 -to HEX2[2]
-set_location_assignment PIN_AC28 -to HEX2[3]
-set_location_assignment PIN_AD30 -to HEX2[4]
-set_location_assignment PIN_AC29 -to HEX2[5]
-set_location_assignment PIN_AC30 -to HEX2[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
-
-#============================================================
-# HEX3
-#============================================================
-set_location_assignment PIN_AD26 -to HEX3[0]
-set_location_assignment PIN_AC27 -to HEX3[1]
-set_location_assignment PIN_AD25 -to HEX3[2]
-set_location_assignment PIN_AC25 -to HEX3[3]
-set_location_assignment PIN_AB28 -to HEX3[4]
-set_location_assignment PIN_AB25 -to HEX3[5]
-set_location_assignment PIN_AB22 -to HEX3[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
-
-#============================================================
-# HEX4
-#============================================================
-set_location_assignment PIN_AA24 -to HEX4[0]
-set_location_assignment PIN_Y23 -to HEX4[1]
-set_location_assignment PIN_Y24 -to HEX4[2]
-set_location_assignment PIN_W22 -to HEX4[3]
-set_location_assignment PIN_W24 -to HEX4[4]
-set_location_assignment PIN_V23 -to HEX4[5]
-set_location_assignment PIN_W25 -to HEX4[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
-
-#============================================================
-# HEX5
-#============================================================
-set_location_assignment PIN_V25 -to HEX5[0]
-set_location_assignment PIN_AA28 -to HEX5[1]
-set_location_assignment PIN_Y27 -to HEX5[2]
-set_location_assignment PIN_AB27 -to HEX5[3]
-set_location_assignment PIN_AB26 -to HEX5[4]
-set_location_assignment PIN_AA26 -to HEX5[5]
-set_location_assignment PIN_AA25 -to HEX5[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
-
-#============================================================
-# KEY
-#============================================================
-set_location_assignment PIN_AA14 -to KEY[0]
-set_location_assignment PIN_AA15 -to KEY[1]
-set_location_assignment PIN_W15 -to KEY[2]
-set_location_assignment PIN_Y16 -to KEY[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
-
-#============================================================
-# LEDR
-#============================================================
-set_location_assignment PIN_V16 -to LEDR[0]
-set_location_assignment PIN_W16 -to LEDR[1]
-set_location_assignment PIN_V17 -to LEDR[2]
-set_location_assignment PIN_V18 -to LEDR[3]
-set_location_assignment PIN_W17 -to LEDR[4]
-set_location_assignment PIN_W19 -to LEDR[5]
-set_location_assignment PIN_Y19 -to LEDR[6]
-set_location_assignment PIN_W20 -to LEDR[7]
-set_location_assignment PIN_W21 -to LEDR[8]
-set_location_assignment PIN_Y21 -to LEDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
-
-#============================================================
-# SW
-#============================================================
-set_location_assignment PIN_AB12 -to SW[0]
-set_location_assignment PIN_AC12 -to SW[1]
-set_location_assignment PIN_AF9 -to SW[2]
-set_location_assignment PIN_AF10 -to SW[3]
-set_location_assignment PIN_AD11 -to SW[4]
-set_location_assignment PIN_AD12 -to SW[5]
-set_location_assignment PIN_AE11 -to SW[6]
-set_location_assignment PIN_AC9 -to SW[7]
-set_location_assignment PIN_AD10 -to SW[8]
-set_location_assignment PIN_AE12 -to SW[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
-
-#============================================================
-# End of pin and io_standard assignments
-#============================================================# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, the Altera Quartus Prime License Agreement,
-# the Altera MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Altera and sold by Altera or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-# Date created = 10:28:00  November 25, 2016
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		ex9_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus Prime software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name DEVICE 5CSEMA5F31C6
-set_global_assignment -name TOP_LEVEL_ENTITY ex9
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v
-set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v
-set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
-set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v
-set_global_assignment -name VERILOG_FILE verilog_files/delay.v
-set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v
-set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
-set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
-set_global_assignment -name VERILOG_FILE verilog_files/ex9.v
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 10:28:00  November 25, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ex9_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex9
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v
+set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v
+set_global_assignment -name VERILOG_FILE verilog_files/delay.v
+set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
+set_global_assignment -name VERILOG_FILE verilog_files/ex9.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 \ No newline at end of file
diff --git a/part_2/ex9/ex9.qsf.bak b/part_2/ex9/ex9.qsf.bak
index 5860fa4..d4eef07 100644
--- a/part_2/ex9/ex9.qsf.bak
+++ b/part_2/ex9/ex9.qsf.bak
@@ -1,65 +1,65 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, the Altera Quartus Prime License Agreement,
-# the Altera MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Altera and sold by Altera or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-# Date created = 10:28:00  November 25, 2016
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		ex9_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus Prime software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name DEVICE 5CSEMA5F31C6
-set_global_assignment -name TOP_LEVEL_ENTITY ex9
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v
-set_global_assignment -name VERILOG_FILE verilog_files/tick_2500.v
-set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v
-set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
-set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v
-set_global_assignment -name VERILOG_FILE verilog_files/delay.v
-set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v
-set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
-set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
-set_global_assignment -name VERILOG_FILE verilog_files/ex9.v
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 10:28:00  November 25, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ex9_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex9
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v
+set_global_assignment -name VERILOG_FILE verilog_files/tick_2500.v
+set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v
+set_global_assignment -name VERILOG_FILE verilog_files/delay.v
+set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
+set_global_assignment -name VERILOG_FILE verilog_files/ex9.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 \ No newline at end of file
diff --git a/part_2/ex9/incremental_db/README b/part_2/ex9/incremental_db/README
index 9f62dcd..6191fbe 100644
--- a/part_2/ex9/incremental_db/README
+++ b/part_2/ex9/incremental_db/README
@@ -1,11 +1,11 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used.  To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info b/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info
index cfd36a1..f84b742 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Version_Index = 402707200
-Creation_Time = Fri Nov 25 10:41:49 2016
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Fri Nov 25 10:41:49 2016
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
index 626799f..d45424f 100644
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex9/output_files/ex9.asm.rpt b/part_2/ex9/output_files/ex9.asm.rpt
index 0da0660..abf1d89 100644
--- a/part_2/ex9/output_files/ex9.asm.rpt
+++ b/part_2/ex9/output_files/ex9.asm.rpt
@@ -1,92 +1,92 @@
-Assembler report for ex9
-Wed Dec 07 12:08:20 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Altera and sold by Altera or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Wed Dec 07 12:08:20 2016 ;
-; Revision Name         ; ex9                                   ;
-; Top-level Entity Name ; ex9                                   ;
-; Family                ; Cyclone V                             ;
-; Device                ; 5CSEMA5F31C6                          ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings               ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+----------------------------------------------------------------------------+
-; Assembler Generated Files                                                  ;
-+----------------------------------------------------------------------------+
-; File Name                                                                  ;
-+----------------------------------------------------------------------------+
-; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
-+----------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------+
-; Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
-+----------------+-------------------------------------------------------------------------------------+
-; Option         ; Setting                                                                             ;
-+----------------+-------------------------------------------------------------------------------------+
-; Device         ; 5CSEMA5F31C6                                                                        ;
-; JTAG usercode  ; 0x00B4D80C                                                                          ;
-; Checksum       ; 0x00B4D80C                                                                          ;
-+----------------+-------------------------------------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
-    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-    Info: Processing started: Wed Dec 07 12:08:12 2016
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 896 megabytes
-    Info: Processing ended: Wed Dec 07 12:08:20 2016
-    Info: Elapsed time: 00:00:08
-    Info: Total CPU time (on all processors): 00:00:06
-
-
+Assembler report for ex9
+Wed Dec 07 12:08:20 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Wed Dec 07 12:08:20 2016 ;
+; Revision Name         ; ex9                                   ;
+; Top-level Entity Name ; ex9                                   ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CSEMA5F31C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++----------------------------------------------------------------------------+
+; Assembler Generated Files                                                  ;
++----------------------------------------------------------------------------+
+; File Name                                                                  ;
++----------------------------------------------------------------------------+
+; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
++----------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
++----------------+-------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                             ;
++----------------+-------------------------------------------------------------------------------------+
+; Device         ; 5CSEMA5F31C6                                                                        ;
+; JTAG usercode  ; 0x00B4D80C                                                                          ;
+; Checksum       ; 0x00B4D80C                                                                          ;
++----------------+-------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Wed Dec 07 12:08:12 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 896 megabytes
+    Info: Processing ended: Wed Dec 07 12:08:20 2016
+    Info: Elapsed time: 00:00:08
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_2/ex9/output_files/ex9.done b/part_2/ex9/output_files/ex9.done
index 1bc853a..2aa652f 100644
--- a/part_2/ex9/output_files/ex9.done
+++ b/part_2/ex9/output_files/ex9.done
@@ -1 +1 @@
-Wed Dec 07 12:08:31 2016
+Wed Dec 07 12:08:31 2016
diff --git a/part_2/ex9/output_files/ex9.fit.rpt b/part_2/ex9/output_files/ex9.fit.rpt
index 133a9e5..90d3227 100644
--- a/part_2/ex9/output_files/ex9.fit.rpt
+++ b/part_2/ex9/output_files/ex9.fit.rpt
@@ -1,2129 +1,2129 @@
-Fitter report for ex9
-Wed Dec 07 12:08:07 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. I/O Assignment Warnings
-  6. Fitter Netlist Optimizations
-  7. Ignored Assignments
-  8. Incremental Compilation Preservation Summary
-  9. Incremental Compilation Partition Settings
- 10. Incremental Compilation Placement Preservation
- 11. Pin-Out File
- 12. Fitter Resource Usage Summary
- 13. Fitter Partition Statistics
- 14. Input Pins
- 15. Output Pins
- 16. I/O Bank Usage
- 17. All Package Pins
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Global & Other Fast Signals
- 23. Routing Usage Summary
- 24. I/O Rules Summary
- 25. I/O Rules Details
- 26. I/O Rules Matrix
- 27. Fitter Device Options
- 28. Operating Settings and Conditions
- 29. Estimated Delay Added for Hold Timing Summary
- 30. Estimated Delay Added for Hold Timing Details
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Altera and sold by Altera or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Fitter Summary                                                                    ;
-+---------------------------------+-------------------------------------------------+
-; Fitter Status                   ; Successful - Wed Dec 07 12:08:07 2016           ;
-; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name                   ; ex9                                             ;
-; Top-level Entity Name           ; ex9                                             ;
-; Family                          ; Cyclone V                                       ;
-; Device                          ; 5CSEMA5F31C6                                    ;
-; Timing Models                   ; Final                                           ;
-; Logic utilization (in ALMs)     ; 159 / 32,070 ( < 1 % )                          ;
-; Total registers                 ; 95                                              ;
-; Total pins                      ; 57 / 457 ( 12 % )                               ;
-; Total virtual pins              ; 0                                               ;
-; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
-; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;
-; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
-; Total HSSI RX PCSs              ; 0                                               ;
-; Total HSSI PMA RX Deserializers ; 0                                               ;
-; Total HSSI TX PCSs              ; 0                                               ;
-; Total HSSI PMA TX Serializers   ; 0                                               ;
-; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
-; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
-+---------------------------------+-------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                                            ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option                                                                     ; Setting                               ; Default Value                         ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
-; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
-; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
-; Use smart compilation                                                      ; Off                                   ; Off                                   ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
-; Enable compact report table                                                ; Off                                   ; Off                                   ;
-; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
-; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
-; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
-; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
-; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
-; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
-; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
-; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
-; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
-; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
-; SSN Optimization                                                           ; Off                                   ; Off                                   ;
-; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
-; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
-; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
-; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
-; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
-; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
-; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
-; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
-; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
-; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
-; Auto Delay Chains                                                          ; On                                    ; On                                    ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
-; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
-; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
-; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
-; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
-; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
-; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
-; Auto Global Clock                                                          ; On                                    ; On                                    ;
-; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
-; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
-; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
-; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
-; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
-; Clamping Diode                                                             ; Off                                   ; Off                                   ;
-; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
-; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.02        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.8%      ;
-;     Processor 3            ;   0.8%      ;
-;     Processor 4            ;   0.8%      ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings                         ;
-+----------+--------------------------------------+
-; Pin Name ; Reason                               ;
-+----------+--------------------------------------+
-; HEX0[0]  ; Missing drive strength and slew rate ;
-; HEX0[1]  ; Missing drive strength and slew rate ;
-; HEX0[2]  ; Missing drive strength and slew rate ;
-; HEX0[3]  ; Missing drive strength and slew rate ;
-; HEX0[4]  ; Missing drive strength and slew rate ;
-; HEX0[5]  ; Missing drive strength and slew rate ;
-; HEX0[6]  ; Missing drive strength and slew rate ;
-; HEX1[0]  ; Missing drive strength and slew rate ;
-; HEX1[1]  ; Missing drive strength and slew rate ;
-; HEX1[2]  ; Missing drive strength and slew rate ;
-; HEX1[3]  ; Missing drive strength and slew rate ;
-; HEX1[4]  ; Missing drive strength and slew rate ;
-; HEX1[5]  ; Missing drive strength and slew rate ;
-; HEX1[6]  ; Missing drive strength and slew rate ;
-; HEX2[0]  ; Missing drive strength and slew rate ;
-; HEX2[1]  ; Missing drive strength and slew rate ;
-; HEX2[2]  ; Missing drive strength and slew rate ;
-; HEX2[3]  ; Missing drive strength and slew rate ;
-; HEX2[4]  ; Missing drive strength and slew rate ;
-; HEX2[5]  ; Missing drive strength and slew rate ;
-; HEX2[6]  ; Missing drive strength and slew rate ;
-; HEX3[0]  ; Missing drive strength and slew rate ;
-; HEX3[1]  ; Missing drive strength and slew rate ;
-; HEX3[2]  ; Missing drive strength and slew rate ;
-; HEX3[3]  ; Missing drive strength and slew rate ;
-; HEX3[4]  ; Missing drive strength and slew rate ;
-; HEX3[5]  ; Missing drive strength and slew rate ;
-; HEX3[6]  ; Missing drive strength and slew rate ;
-; HEX4[0]  ; Missing drive strength and slew rate ;
-; HEX4[1]  ; Missing drive strength and slew rate ;
-; HEX4[2]  ; Missing drive strength and slew rate ;
-; HEX4[3]  ; Missing drive strength and slew rate ;
-; HEX4[4]  ; Missing drive strength and slew rate ;
-; HEX4[5]  ; Missing drive strength and slew rate ;
-; HEX4[6]  ; Missing drive strength and slew rate ;
-; HEX5[0]  ; Missing drive strength and slew rate ;
-; HEX5[1]  ; Missing drive strength and slew rate ;
-; HEX5[2]  ; Missing drive strength and slew rate ;
-; HEX5[3]  ; Missing drive strength and slew rate ;
-; HEX5[4]  ; Missing drive strength and slew rate ;
-; HEX5[5]  ; Missing drive strength and slew rate ;
-; HEX5[6]  ; Missing drive strength and slew rate ;
-; LEDR[0]  ; Missing drive strength and slew rate ;
-; LEDR[1]  ; Missing drive strength and slew rate ;
-; LEDR[2]  ; Missing drive strength and slew rate ;
-; LEDR[3]  ; Missing drive strength and slew rate ;
-; LEDR[4]  ; Missing drive strength and slew rate ;
-; LEDR[5]  ; Missing drive strength and slew rate ;
-; LEDR[6]  ; Missing drive strength and slew rate ;
-; LEDR[7]  ; Missing drive strength and slew rate ;
-; LEDR[8]  ; Missing drive strength and slew rate ;
-; LEDR[9]  ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Netlist Optimizations                                                                                                                                                                                                            ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; Node                       ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                     ; Destination Port ; Destination Port Name ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; CLOCK_50~inputCLKENA0      ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                      ;                  ;                       ;
-; formula_fsm:FSM|count[6]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[6]~DUPLICATE   ;                  ;                       ;
-; tick_50000:TICK0|count[0]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[0]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[1]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[2]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[2]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[5]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[8]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[8]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[10]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[11]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[12]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[14]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[15]~DUPLICATE ;                  ;                       ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------------------------+
-; Ignored Assignments                                                                        ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
-; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
-; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;
-; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;
-; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;
-; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;
-; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;
-; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;
-; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;
-; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary                                                     ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ;                    ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 )         ; 0.00 % ( 0 / 489 )       ;
-;     -- Achieved     ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 )         ; 0.00 % ( 0 / 489 )       ;
-;                     ;                    ;                            ;                          ;
-; Routing (by net)    ;                    ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings                                                                                                                                             ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation                                                                                     ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 489 )    ; N/A                     ; Source File       ; N/A                 ;       ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.pin.
-
-
-+------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                                            ;
-+-------------------------------------------------------------+--------------------+-------+
-; Resource                                                    ; Usage              ; %     ;
-+-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 159 / 32,070       ; < 1 % ;
-; ALMs needed [=A-B+C]                                        ; 159                ;       ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 162 / 32,070       ; < 1 % ;
-;         [a] ALMs used for LUT logic and registers           ; 36                 ;       ;
-;         [b] ALMs used for LUT logic                         ; 120                ;       ;
-;         [c] ALMs used for registers                         ; 6                  ;       ;
-;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32,070         ; < 1 % ;
-;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
-;         [a] Due to location constrained logic               ; 0                  ;       ;
-;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
-;         [c] Due to LAB input limits                         ; 0                  ;       ;
-;         [d] Due to virtual I/Os                             ; 0                  ;       ;
-;                                                             ;                    ;       ;
-; Difficulty packing design                                   ; Low                ;       ;
-;                                                             ;                    ;       ;
-; Total LABs:  partially or completely used                   ; 19 / 3,207         ; < 1 % ;
-;     -- Logic LABs                                           ; 19                 ;       ;
-;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
-;                                                             ;                    ;       ;
-; Combinational ALUT usage for logic                          ; 290                ;       ;
-;     -- 7 input functions                                    ; 0                  ;       ;
-;     -- 6 input functions                                    ; 41                 ;       ;
-;     -- 5 input functions                                    ; 5                  ;       ;
-;     -- 4 input functions                                    ; 157                ;       ;
-;     -- <=3 input functions                                  ; 87                 ;       ;
-; Combinational ALUT usage for route-throughs                 ; 1                  ;       ;
-; Dedicated logic registers                                   ; 95                 ;       ;
-;     -- By type:                                             ;                    ;       ;
-;         -- Primary logic registers                          ; 84 / 64,140        ; < 1 % ;
-;         -- Secondary logic registers                        ; 11 / 64,140        ; < 1 % ;
-;     -- By function:                                         ;                    ;       ;
-;         -- Design implementation registers                  ; 84                 ;       ;
-;         -- Routing optimization registers                   ; 11                 ;       ;
-;                                                             ;                    ;       ;
-; Virtual pins                                                ; 0                  ;       ;
-; I/O pins                                                    ; 57 / 457           ; 12 %  ;
-;     -- Clock pins                                           ; 4 / 8              ; 50 %  ;
-;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
-;                                                             ;                    ;       ;
-; Hard processor system peripheral utilization                ;                    ;       ;
-;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
-;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
-;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
-;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
-;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
-;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
-;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
-;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
-;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
-;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
-;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
-;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
-;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
-;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
-;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
-;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
-;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
-;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
-;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
-;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
-;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
-;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
-;                                                             ;                    ;       ;
-; Global signals                                              ; 1                  ;       ;
-; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
-; Total MLAB memory bits                                      ; 0                  ;       ;
-; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
-; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
-;                                                             ;                    ;       ;
-; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
-;                                                             ;                    ;       ;
-; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
-; Global clocks                                               ; 1 / 16             ; 6 %   ;
-; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;
-; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;
-; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
-; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
-; JTAGs                                                       ; 0 / 1              ; 0 %   ;
-; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
-; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
-; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
-; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
-; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
-; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
-; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;
-; Peak interconnect usage (total/H/V)                         ; 2.7% / 3.0% / 1.9% ;       ;
-; Maximum fan-out                                             ; 68                 ;       ;
-; Highest non-global fan-out                                  ; 68                 ;       ;
-; Total fan-out                                               ; 1448               ;       ;
-; Average fan-out                                             ; 2.89               ;       ;
-+-------------------------------------------------------------+--------------------+-------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics                                                                                          ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 159 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
-; ALMs needed [=A-B+C]                                        ; 159                   ; 0                              ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 162 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
-;         [a] ALMs used for LUT logic and registers           ; 36                    ; 0                              ;
-;         [b] ALMs used for LUT logic                         ; 120                   ; 0                              ;
-;         [c] ALMs used for registers                         ; 6                     ; 0                              ;
-;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;
-;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
-;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
-;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
-;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;
-;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Difficulty packing design                                   ; Low                   ; Low                            ;
-;                                                             ;                       ;                                ;
-; Total LABs:  partially or completely used                   ; 19 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
-;     -- Logic LABs                                           ; 19                    ; 0                              ;
-;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Combinational ALUT usage for logic                          ; 290                   ; 0                              ;
-;     -- 7 input functions                                    ; 0                     ; 0                              ;
-;     -- 6 input functions                                    ; 41                    ; 0                              ;
-;     -- 5 input functions                                    ; 5                     ; 0                              ;
-;     -- 4 input functions                                    ; 157                   ; 0                              ;
-;     -- <=3 input functions                                  ; 87                    ; 0                              ;
-; Combinational ALUT usage for route-throughs                 ; 1                     ; 0                              ;
-; Memory ALUT usage                                           ; 0                     ; 0                              ;
-;     -- 64-address deep                                      ; 0                     ; 0                              ;
-;     -- 32-address deep                                      ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Dedicated logic registers                                   ; 0                     ; 0                              ;
-;     -- By type:                                             ;                       ;                                ;
-;         -- Primary logic registers                          ; 84 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
-;         -- Secondary logic registers                        ; 11 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
-;     -- By function:                                         ;                       ;                                ;
-;         -- Design implementation registers                  ; 84                    ; 0                              ;
-;         -- Routing optimization registers                   ; 11                    ; 0                              ;
-;                                                             ;                       ;                                ;
-;                                                             ;                       ;                                ;
-; Virtual pins                                                ; 0                     ; 0                              ;
-; I/O pins                                                    ; 57                    ; 0                              ;
-; I/O registers                                               ; 0                     ; 0                              ;
-; Total block memory bits                                     ; 0                     ; 0                              ;
-; Total block memory implementation bits                      ; 0                     ; 0                              ;
-; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;
-;                                                             ;                       ;                                ;
-; Connections                                                 ;                       ;                                ;
-;     -- Input Connections                                    ; 0                     ; 0                              ;
-;     -- Registered Input Connections                         ; 0                     ; 0                              ;
-;     -- Output Connections                                   ; 0                     ; 0                              ;
-;     -- Registered Output Connections                        ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Internal Connections                                        ;                       ;                                ;
-;     -- Total Connections                                    ; 1448                  ; 0                              ;
-;     -- Registered Connections                               ; 438                   ; 0                              ;
-;                                                             ;                       ;                                ;
-; External Connections                                        ;                       ;                                ;
-;     -- Top                                                  ; 0                     ; 0                              ;
-;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Partition Interface                                         ;                       ;                                ;
-;     -- Input Ports                                          ; 5                     ; 0                              ;
-;     -- Output Ports                                         ; 52                    ; 0                              ;
-;     -- Bidir Ports                                          ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Registered Ports                                            ;                       ;                                ;
-;     -- Registered Input Ports                               ; 0                     ; 0                              ;
-;     -- Registered Output Ports                              ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Port Connectivity                                           ;                       ;                                ;
-;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;
-;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;
-;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;
-;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;
-;     -- Input Ports with no Source                           ; 0                     ; 0                              ;
-;     -- Output Ports with no Source                          ; 0                     ; 0                              ;
-;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;
-;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                                                                              ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 27                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[2]   ; W15   ; 3B       ; 40           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[3]   ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 3                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[0] ; V25   ; 5B       ; 89           ; 20           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[1] ; AA28  ; 5B       ; 89           ; 21           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[2] ; Y27   ; 5B       ; 89           ; 25           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[3] ; AB27  ; 5B       ; 89           ; 23           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[4] ; AB26  ; 5A       ; 89           ; 9            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[5] ; AA26  ; 5B       ; 89           ; 23           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[6] ; AA25  ; 5A       ; 89           ; 9            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[0] ; V16   ; 4A       ; 52           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[1] ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[2] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[3] ; V18   ; 4A       ; 80           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[4] ; W17   ; 4A       ; 60           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[5] ; W19   ; 4A       ; 80           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[6] ; Y19   ; 4A       ; 84           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[7] ; W20   ; 5A       ; 89           ; 6            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[8] ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[9] ; Y21   ; 5A       ; 89           ; 6            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-----------------------------------------------------------------------------+
-; I/O Bank Usage                                                              ;
-+----------+-------------------+---------------+--------------+---------------+
-; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
-+----------+-------------------+---------------+--------------+---------------+
-; B2L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
-; B1L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
-; 3A       ; 0 / 32 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 3B       ; 5 / 48 ( 10 % )   ; 3.3V          ; --           ; 3.3V          ;
-; 4A       ; 7 / 80 ( 9 % )    ; 3.3V          ; --           ; 3.3V          ;
-; 5A       ; 32 / 32 ( 100 % ) ; 3.3V          ; --           ; 3.3V          ;
-; 5B       ; 13 / 16 ( 81 % )  ; 3.3V          ; --           ; 3.3V          ;
-; 6B       ; 0 / 44 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 6A       ; 0 / 56 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7A       ; 0 / 19 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7B       ; 0 / 22 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7C       ; 0 / 12 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7D       ; 0 / 14 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 8A       ; 0 / 80 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-+----------+-------------------+---------------+--------------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                                                                  ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA25     ; 224        ; 5A             ; HEX5[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA26     ; 252        ; 5B             ; HEX5[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AA28     ; 251        ; 5B             ; HEX5[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB26     ; 226        ; 5A             ; HEX5[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB27     ; 254        ; 5B             ; HEX5[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
-; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
-; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
-; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
-; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V16      ; 138        ; 4A             ; LEDR[0]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V17      ; 154        ; 4A             ; LEDR[2]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V18      ; 194        ; 4A             ; LEDR[3]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; V25      ; 246        ; 5B             ; HEX5[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W15      ; 130        ; 3B             ; KEY[2]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W16      ; 136        ; 4A             ; LEDR[1]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W17      ; 152        ; 4A             ; LEDR[4]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W19      ; 192        ; 4A             ; LEDR[5]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W20      ; 217        ; 5A             ; LEDR[7]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W21      ; 221        ; 5A             ; LEDR[8]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y16      ; 128        ; 3B             ; KEY[3]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y19      ; 202        ; 4A             ; LEDR[6]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y21      ; 219        ; 5A             ; LEDR[9]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y27      ; 258        ; 5B             ; HEX5[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                               ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex9                       ; 158.5 (0.5)          ; 161.5 (0.5)                      ; 3.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 290 (1)             ; 95 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
-;    |LFSR:LFSR0|            ; 3.0 (3.0)            ; 3.3 (3.3)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 7 (7)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
-;    |bin2bcd_16:BCD|        ; 67.7 (0.0)           ; 68.0 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 124 (0)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A1|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
-;       |add3_ge5:A10|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
-;       |add3_ge5:A11|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
-;       |add3_ge5:A12|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
-;       |add3_ge5:A13|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
-;       |add3_ge5:A14|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
-;       |add3_ge5:A15|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
-;       |add3_ge5:A16|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
-;       |add3_ge5:A17|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
-;       |add3_ge5:A18|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
-;       |add3_ge5:A19|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
-;       |add3_ge5:A2|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
-;       |add3_ge5:A20|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
-;       |add3_ge5:A21|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
-;       |add3_ge5:A22|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A23|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
-;       |add3_ge5:A24|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
-;       |add3_ge5:A25|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A27|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
-;       |add3_ge5:A28|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
-;       |add3_ge5:A29|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
-;       |add3_ge5:A3|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
-;       |add3_ge5:A30|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
-;       |add3_ge5:A32|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
-;       |add3_ge5:A33|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
-;       |add3_ge5:A34|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
-;       |add3_ge5:A35|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
-;       |add3_ge5:A4|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
-;       |add3_ge5:A5|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
-;       |add3_ge5:A6|        ; 3.7 (3.7)            ; 4.0 (4.0)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
-;       |add3_ge5:A7|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
-;       |add3_ge5:A8|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
-;       |add3_ge5:A9|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
-;    |counter_16:COUNT0|     ; 8.5 (8.5)            ; 8.6 (8.6)                        ; 0.1 (0.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (17)             ; 17 (17)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
-;    |delay:DEL0|            ; 14.3 (14.3)          ; 15.4 (15.4)                      ; 1.1 (1.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 25 (25)             ; 18 (18)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
-;    |formula_fsm:FSM|       ; 24.5 (24.5)          ; 25.3 (25.3)                      ; 0.8 (0.8)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 43 (43)             ; 26 (26)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
-;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG2|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG3|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG4|      ; 7.5 (7.5)            ; 7.5 (7.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
-;    |tick_50000:TICK0|      ; 18.5 (18.5)          ; 18.9 (18.9)                      ; 0.4 (0.4)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (36)             ; 27 (27)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Delay Chain Summary                                                                                                     ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; KEY[1]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; KEY[2]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; KEY[0]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; CLOCK_50 ; Input    ; -- ; (0)  ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; KEY[3]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout                                                ;
-+-------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout                             ; Pad To Core Index ; Setting ;
-+-------------------------------------------------+-------------------+---------+
-; KEY[1]                                          ;                   ;         ;
-; KEY[2]                                          ;                   ;         ;
-; KEY[0]                                          ;                   ;         ;
-;      - counter_16:COUNT0|count~0                ; 1                 ; 0       ;
-; CLOCK_50                                        ;                   ;         ;
-;      - tick_50000:TICK0|CLK_OUT                 ; 1                 ; 0       ;
-; KEY[3]                                          ;                   ;         ;
-;      - formula_fsm:FSM|Selector3~0              ; 1                 ; 0       ;
-;      - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~0 ; 1                 ; 0       ;
-;      - formula_fsm:FSM|Selector2~0              ; 1                 ; 0       ;
-+-------------------------------------------------+-------------------+---------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                                                                                ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; Name                                ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50                            ; PIN_AF14           ; 2       ; Clock                      ; no     ; --                   ; --               ; --                        ;
-; CLOCK_50                            ; PIN_AF14           ; 26      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
-; counter_16:COUNT0|count~0           ; LABCELL_X60_Y4_N30 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; counter_16:COUNT0|state             ; FF_X59_Y4_N14      ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
-; delay:DEL0|count[5]~0               ; LABCELL_X62_Y4_N51 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; delay:DEL0|state.COUNTING           ; FF_X63_Y4_N56      ; 19      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X62_Y4_N56      ; 26      ; Clock enable, Latch enable ; no     ; --                   ; --               ; --                        ;
-; formula_fsm:FSM|state.WAIT_TRIGGER  ; FF_X61_Y4_N2       ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; tick_50000:TICK0|CLK_OUT            ; FF_X60_Y4_N2       ; 68      ; Clock                      ; no     ; --                   ; --               ; --                        ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals                                                                         ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 26      ; Global Clock         ; GCLK6            ; --                        ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------+
-; Routing Usage Summary                                                 ;
-+---------------------------------------------+-------------------------+
-; Routing Resource Type                       ; Usage                   ;
-+---------------------------------------------+-------------------------+
-; Block interconnects                         ; 375 / 289,320 ( < 1 % ) ;
-; C12 interconnects                           ; 2 / 13,420 ( < 1 % )    ;
-; C2 interconnects                            ; 132 / 119,108 ( < 1 % ) ;
-; C4 interconnects                            ; 84 / 56,300 ( < 1 % )   ;
-; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
-; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
-; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
-; Direct links                                ; 62 / 289,320 ( < 1 % )  ;
-; Global clocks                               ; 1 / 16 ( 6 % )          ;
-; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
-; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
-; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
-; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
-; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
-; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
-; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
-; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
-; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
-; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
-; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
-; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
-; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
-; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
-; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
-; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
-; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
-; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
-; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
-; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
-; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
-; Local interconnects                         ; 147 / 84,580 ( < 1 % )  ;
-; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
-; R14 interconnects                           ; 25 / 12,676 ( < 1 % )   ;
-; R14/C12 interconnect drivers                ; 26 / 20,720 ( < 1 % )   ;
-; R3 interconnects                            ; 160 / 130,992 ( < 1 % ) ;
-; R6 interconnects                            ; 252 / 266,960 ( < 1 % ) ;
-; Spine clocks                                ; 1 / 360 ( < 1 % )       ;
-; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
-+---------------------------------------------+-------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary                        ;
-+----------------------------------+-------+
-; I/O Rules Statistic              ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules                  ; 28    ;
-; Number of I/O Rules Passed       ; 6     ;
-; Number of I/O Rules Failed       ; 0     ;
-; Number of I/O Rules Unchecked    ; 0     ;
-; Number of I/O Rules Inapplicable ; 22    ;
-+----------------------------------+-------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details                                                                                                                                                                                                                                                  ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
-; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
-; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
-; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
-; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
-; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-; Total Pass         ; 57        ; 0            ; 57        ; 0            ; 0            ; 57        ; 57        ; 0            ; 57        ; 57        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
-; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
-; Total Inapplicable ; 0         ; 57           ; 0         ; 57           ; 57           ; 0         ; 0         ; 57           ; 0         ; 0         ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ;
-; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
-; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[8]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[9]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Fitter Device Options                                                                          ;
-+------------------------------------------------------------------+-----------------------------+
-; Option                                                           ; Setting                     ;
-+------------------------------------------------------------------+-----------------------------+
-; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
-; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
-; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
-; Enable INIT_DONE output                                          ; Off                         ;
-; Configuration scheme                                             ; Passive Serial              ;
-; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
-; Enable CvP_CONFDONE pin                                          ; Off                         ;
-; Enable open drain on CRC_ERROR pin                               ; On                          ;
-; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
-; Enable open drain on INIT_DONE pin                               ; On                          ;
-; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
-; Enable open drain on nCEO pin                                    ; On                          ;
-; Enable Partial Reconfiguration pins                              ; Off                         ;
-; Enable input tri-state on active configuration pins in user mode ; Off                         ;
-; Enable internal scrubbing                                        ; Off                         ;
-; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
-; Device initialization clock source                               ; Internal Oscillator         ;
-; Configuration via Protocol                                       ; Off                         ;
-; Configuration Voltage Level                                      ; Auto                        ;
-; Force Configuration Voltage Level                                ; Off                         ;
-; Enable nCEO output                                               ; Off                         ;
-; Data[15..8]                                                      ; Unreserved                  ;
-; Data[7..5]                                                       ; Unreserved                  ;
-; Base pin-out file on sameframe device                            ; Off                         ;
-+------------------------------------------------------------------+-----------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions  ;
-+---------------------------+--------+
-; Setting                   ; Value  ;
-+---------------------------+--------+
-; Nominal Core Voltage      ; 1.10 V ;
-; Low Junction Temperature  ; 0 �C   ;
-; High Junction Temperature ; 85 �C  ;
-+---------------------------+--------+
-
-
-+-------------------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary                                                               ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; Source Clock(s)                                              ; Destination Clock(s)     ; Delay Added in ns ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; tick_50000:TICK0|CLK_OUT                                     ; tick_50000:TICK0|CLK_OUT ; 62.3              ;
-; CLOCK_50                                                     ; CLOCK_50                 ; 9.8               ;
-; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.7               ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS                          ; tick_50000:TICK0|CLK_OUT ; 3.2               ;
-; tick_50000:TICK0|CLK_OUT,I/O                                 ; tick_50000:TICK0|CLK_OUT ; 1.6               ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
-
-
-+--------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details                                                    ;
-+----------------------------------------+-------------------------------------+-------------------+
-; Source Register                        ; Destination Register                ; Delay Added in ns ;
-+----------------------------------------+-------------------------------------+-------------------+
-; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; formula_fsm:FSM|ledr[3]             ; 2.057             ;
-; formula_fsm:FSM|start_delay            ; delay:DEL0|state.IDLE               ; 1.568             ;
-; tick_50000:TICK0|count[5]              ; tick_50000:TICK0|CLK_OUT            ; 1.369             ;
-; tick_50000:TICK0|count[11]             ; tick_50000:TICK0|CLK_OUT            ; 1.341             ;
-; tick_50000:TICK0|count[14]             ; tick_50000:TICK0|CLK_OUT            ; 1.313             ;
-; tick_50000:TICK0|count[15]             ; tick_50000:TICK0|CLK_OUT            ; 1.313             ;
-; tick_50000:TICK0|count[6]              ; tick_50000:TICK0|CLK_OUT            ; 1.267             ;
-; tick_50000:TICK0|count[12]             ; tick_50000:TICK0|CLK_OUT            ; 1.232             ;
-; tick_50000:TICK0|count[3]              ; tick_50000:TICK0|CLK_OUT            ; 1.227             ;
-; tick_50000:TICK0|count[8]              ; tick_50000:TICK0|CLK_OUT            ; 1.224             ;
-; tick_50000:TICK0|count[13]             ; tick_50000:TICK0|CLK_OUT            ; 1.214             ;
-; tick_50000:TICK0|count[9]              ; tick_50000:TICK0|CLK_OUT            ; 1.207             ;
-; tick_50000:TICK0|count[4]              ; tick_50000:TICK0|CLK_OUT            ; 1.206             ;
-; tick_50000:TICK0|count[7]              ; tick_50000:TICK0|CLK_OUT            ; 1.192             ;
-; tick_50000:TICK0|count[0]              ; tick_50000:TICK0|CLK_OUT            ; 1.189             ;
-; tick_50000:TICK0|count[1]              ; tick_50000:TICK0|CLK_OUT            ; 1.170             ;
-; tick_50000:TICK0|count[2]              ; tick_50000:TICK0|CLK_OUT            ; 1.169             ;
-; tick_50000:TICK0|count[10]             ; tick_50000:TICK0|CLK_OUT            ; 1.155             ;
-; delay:DEL0|count[13]                   ; delay:DEL0|count[11]                ; 0.995             ;
-; formula_fsm:FSM|count[1]               ; formula_fsm:FSM|count[1]            ; 0.879             ;
-; formula_fsm:FSM|count[6]               ; formula_fsm:FSM|count[5]            ; 0.876             ;
-; formula_fsm:FSM|count[9]               ; formula_fsm:FSM|count[5]            ; 0.866             ;
-; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[3]             ; 0.865             ;
-; delay:DEL0|state.IDLE                  ; delay:DEL0|state.COUNTING           ; 0.863             ;
-; formula_fsm:FSM|count[0]               ; formula_fsm:FSM|count[1]            ; 0.855             ;
-; formula_fsm:FSM|count[7]               ; formula_fsm:FSM|count[5]            ; 0.852             ;
-; delay:DEL0|count[0]                    ; delay:DEL0|count[11]                ; 0.851             ;
-; delay:DEL0|count[3]                    ; delay:DEL0|count[11]                ; 0.848             ;
-; delay:DEL0|count[9]                    ; delay:DEL0|count[11]                ; 0.836             ;
-; delay:DEL0|count[8]                    ; delay:DEL0|count[11]                ; 0.833             ;
-; delay:DEL0|count[1]                    ; delay:DEL0|count[11]                ; 0.830             ;
-; formula_fsm:FSM|ledr[0]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[1]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[2]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[3]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[4]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[5]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[6]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[7]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[8]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[9]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; KEY[3]                                 ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|state.WAIT_TRIGGER     ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; delay:DEL0|state.TIME_OUT              ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; delay:DEL0|count[6]                    ; delay:DEL0|count[11]                ; 0.820             ;
-; delay:DEL0|state.COUNTING              ; delay:DEL0|state.IDLE               ; 0.805             ;
-; formula_fsm:FSM|count[4]               ; formula_fsm:FSM|count[1]            ; 0.801             ;
-; delay:DEL0|count[7]                    ; delay:DEL0|count[11]                ; 0.800             ;
-; delay:DEL0|state.WAIT_LOW              ; delay:DEL0|state.IDLE               ; 0.784             ;
-; delay:DEL0|count[4]                    ; delay:DEL0|count[11]                ; 0.779             ;
-; formula_fsm:FSM|count[8]               ; formula_fsm:FSM|count[10]           ; 0.751             ;
-; delay:DEL0|count[10]                   ; delay:DEL0|count[11]                ; 0.743             ;
-; formula_fsm:FSM|count[2]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
-; formula_fsm:FSM|count[3]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
-; formula_fsm:FSM|count[5]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
-; formula_fsm:FSM|count[10]              ; formula_fsm:FSM|count[5]            ; 0.741             ;
-; formula_fsm:FSM|count[11]              ; formula_fsm:FSM|count[5]            ; 0.741             ;
-; delay:DEL0|count[11]                   ; delay:DEL0|count[11]                ; 0.720             ;
-; delay:DEL0|count[12]                   ; delay:DEL0|count[11]                ; 0.714             ;
-; delay:DEL0|count[5]                    ; delay:DEL0|count[11]                ; 0.714             ;
-; LFSR:LFSR0|COUNT[1]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.700             ;
-; LFSR:LFSR0|COUNT[7]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.700             ;
-; delay:DEL0|count[2]                    ; delay:DEL0|count[11]                ; 0.673             ;
-; LFSR:LFSR0|COUNT[5]                    ; LFSR:LFSR0|COUNT[6]                 ; 0.631             ;
-; LFSR:LFSR0|COUNT[3]                    ; LFSR:LFSR0|COUNT[4]                 ; 0.626             ;
-; LFSR:LFSR0|COUNT[4]                    ; LFSR:LFSR0|COUNT[5]                 ; 0.613             ;
-; LFSR:LFSR0|COUNT[6]                    ; LFSR:LFSR0|COUNT[7]                 ; 0.613             ;
-; LFSR:LFSR0|COUNT[2]                    ; delay:DEL0|count[8]                 ; 0.610             ;
-; counter_16:COUNT0|count[7]             ; counter_16:COUNT0|count[15]         ; 0.249             ;
-; counter_16:COUNT0|count[1]             ; counter_16:COUNT0|count[15]         ; 0.239             ;
-; counter_16:COUNT0|count[12]            ; counter_16:COUNT0|count[15]         ; 0.238             ;
-; counter_16:COUNT0|count[0]             ; counter_16:COUNT0|count[15]         ; 0.237             ;
-; counter_16:COUNT0|count[8]             ; counter_16:COUNT0|count[15]         ; 0.236             ;
-; counter_16:COUNT0|count[5]             ; counter_16:COUNT0|count[15]         ; 0.236             ;
-; counter_16:COUNT0|count[3]             ; counter_16:COUNT0|count[15]         ; 0.232             ;
-; counter_16:COUNT0|count[13]            ; counter_16:COUNT0|count[15]         ; 0.231             ;
-; counter_16:COUNT0|count[6]             ; counter_16:COUNT0|count[15]         ; 0.228             ;
-; counter_16:COUNT0|count[9]             ; counter_16:COUNT0|count[15]         ; 0.227             ;
-; counter_16:COUNT0|state                ; counter_16:COUNT0|state             ; 0.140             ;
-; KEY[0]                                 ; counter_16:COUNT0|state             ; 0.089             ;
-; counter_16:COUNT0|count[11]            ; counter_16:COUNT0|count[15]         ; 0.053             ;
-; counter_16:COUNT0|count[14]            ; counter_16:COUNT0|count[15]         ; 0.047             ;
-; counter_16:COUNT0|count[2]             ; counter_16:COUNT0|count[15]         ; 0.046             ;
-; counter_16:COUNT0|count[10]            ; counter_16:COUNT0|count[15]         ; 0.043             ;
-; counter_16:COUNT0|count[4]             ; counter_16:COUNT0|count[15]         ; 0.043             ;
-; tick_50000:TICK0|CLK_OUT               ; counter_16:COUNT0|state             ; 0.036             ;
-+----------------------------------------+-------------------------------------+-------------------+
-Note: This table only shows the top 86 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device 5CSEMA5F31C6 for design "ex9"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Info (184020): Starting Fitter periphery placement operations
-Info (11191): Automatically promoted 1 clock (1 global)
-    Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
-Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
-Info (176233): Starting register packing
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176235): Finished register packing
-    Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
-    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
-Info (11798): Fitter preparation operations ending: elapsed time is 00:00:12
-Info (170189): Fitter placement preparation operations beginning
-Info (14951): The Fitter is using Advanced Physical Optimization.
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:02
-Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 30 warnings
-    Info: Peak virtual memory: 2593 megabytes
-    Info: Processing ended: Wed Dec 07 12:08:09 2016
-    Info: Elapsed time: 00:00:37
-    Info: Total CPU time (on all processors): 00:01:02
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg.
-
-
+Fitter report for ex9
+Wed Dec 07 12:08:07 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Fitter Netlist Optimizations
+  7. Ignored Assignments
+  8. Incremental Compilation Preservation Summary
+  9. Incremental Compilation Partition Settings
+ 10. Incremental Compilation Placement Preservation
+ 11. Pin-Out File
+ 12. Fitter Resource Usage Summary
+ 13. Fitter Partition Statistics
+ 14. Input Pins
+ 15. Output Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Routing Usage Summary
+ 24. I/O Rules Summary
+ 25. I/O Rules Details
+ 26. I/O Rules Matrix
+ 27. Fitter Device Options
+ 28. Operating Settings and Conditions
+ 29. Estimated Delay Added for Hold Timing Summary
+ 30. Estimated Delay Added for Hold Timing Details
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary                                                                    ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status                   ; Successful - Wed Dec 07 12:08:07 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex9                                             ;
+; Top-level Entity Name           ; ex9                                             ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 159 / 32,070 ( < 1 % )                          ;
+; Total registers                 ; 95                                              ;
+; Total pins                      ; 57 / 457 ( 12 % )                               ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Clamping Diode                                                             ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.02        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.8%      ;
+;     Processor 3            ;   0.8%      ;
+;     Processor 4            ;   0.8%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings                         ;
++----------+--------------------------------------+
+; Pin Name ; Reason                               ;
++----------+--------------------------------------+
+; HEX0[0]  ; Missing drive strength and slew rate ;
+; HEX0[1]  ; Missing drive strength and slew rate ;
+; HEX0[2]  ; Missing drive strength and slew rate ;
+; HEX0[3]  ; Missing drive strength and slew rate ;
+; HEX0[4]  ; Missing drive strength and slew rate ;
+; HEX0[5]  ; Missing drive strength and slew rate ;
+; HEX0[6]  ; Missing drive strength and slew rate ;
+; HEX1[0]  ; Missing drive strength and slew rate ;
+; HEX1[1]  ; Missing drive strength and slew rate ;
+; HEX1[2]  ; Missing drive strength and slew rate ;
+; HEX1[3]  ; Missing drive strength and slew rate ;
+; HEX1[4]  ; Missing drive strength and slew rate ;
+; HEX1[5]  ; Missing drive strength and slew rate ;
+; HEX1[6]  ; Missing drive strength and slew rate ;
+; HEX2[0]  ; Missing drive strength and slew rate ;
+; HEX2[1]  ; Missing drive strength and slew rate ;
+; HEX2[2]  ; Missing drive strength and slew rate ;
+; HEX2[3]  ; Missing drive strength and slew rate ;
+; HEX2[4]  ; Missing drive strength and slew rate ;
+; HEX2[5]  ; Missing drive strength and slew rate ;
+; HEX2[6]  ; Missing drive strength and slew rate ;
+; HEX3[0]  ; Missing drive strength and slew rate ;
+; HEX3[1]  ; Missing drive strength and slew rate ;
+; HEX3[2]  ; Missing drive strength and slew rate ;
+; HEX3[3]  ; Missing drive strength and slew rate ;
+; HEX3[4]  ; Missing drive strength and slew rate ;
+; HEX3[5]  ; Missing drive strength and slew rate ;
+; HEX3[6]  ; Missing drive strength and slew rate ;
+; HEX4[0]  ; Missing drive strength and slew rate ;
+; HEX4[1]  ; Missing drive strength and slew rate ;
+; HEX4[2]  ; Missing drive strength and slew rate ;
+; HEX4[3]  ; Missing drive strength and slew rate ;
+; HEX4[4]  ; Missing drive strength and slew rate ;
+; HEX4[5]  ; Missing drive strength and slew rate ;
+; HEX4[6]  ; Missing drive strength and slew rate ;
+; HEX5[0]  ; Missing drive strength and slew rate ;
+; HEX5[1]  ; Missing drive strength and slew rate ;
+; HEX5[2]  ; Missing drive strength and slew rate ;
+; HEX5[3]  ; Missing drive strength and slew rate ;
+; HEX5[4]  ; Missing drive strength and slew rate ;
+; HEX5[5]  ; Missing drive strength and slew rate ;
+; HEX5[6]  ; Missing drive strength and slew rate ;
+; LEDR[0]  ; Missing drive strength and slew rate ;
+; LEDR[1]  ; Missing drive strength and slew rate ;
+; LEDR[2]  ; Missing drive strength and slew rate ;
+; LEDR[3]  ; Missing drive strength and slew rate ;
+; LEDR[4]  ; Missing drive strength and slew rate ;
+; LEDR[5]  ; Missing drive strength and slew rate ;
+; LEDR[6]  ; Missing drive strength and slew rate ;
+; LEDR[7]  ; Missing drive strength and slew rate ;
+; LEDR[8]  ; Missing drive strength and slew rate ;
+; LEDR[9]  ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                            ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+; Node                       ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                     ; Destination Port ; Destination Port Name ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0      ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                      ;                  ;                       ;
+; formula_fsm:FSM|count[6]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[6]~DUPLICATE   ;                  ;                       ;
+; tick_50000:TICK0|count[0]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[0]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[1]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[2]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[2]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[5]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[8]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[8]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[10]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[11]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[12]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[14]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[15]~DUPLICATE ;                  ;                       ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                        ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
+; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;
+; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;
+; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;
+; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;
+; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;
+; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;
+; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;
+; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 )         ; 0.00 % ( 0 / 489 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 )         ; 0.00 % ( 0 / 489 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 489 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 159 / 32,070       ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 159                ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 162 / 32,070       ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 36                 ;       ;
+;         [b] ALMs used for LUT logic                         ; 120                ;       ;
+;         [c] ALMs used for registers                         ; 6                  ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32,070         ; < 1 % ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 0                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 19 / 3,207         ; < 1 % ;
+;     -- Logic LABs                                           ; 19                 ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 290                ;       ;
+;     -- 7 input functions                                    ; 0                  ;       ;
+;     -- 6 input functions                                    ; 41                 ;       ;
+;     -- 5 input functions                                    ; 5                  ;       ;
+;     -- 4 input functions                                    ; 157                ;       ;
+;     -- <=3 input functions                                  ; 87                 ;       ;
+; Combinational ALUT usage for route-throughs                 ; 1                  ;       ;
+; Dedicated logic registers                                   ; 95                 ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 84 / 64,140        ; < 1 % ;
+;         -- Secondary logic registers                        ; 11 / 64,140        ; < 1 % ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 84                 ;       ;
+;         -- Routing optimization registers                   ; 11                 ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 57 / 457           ; 12 %  ;
+;     -- Clock pins                                           ; 4 / 8              ; 50 %  ;
+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Hard processor system peripheral utilization                ;                    ;       ;
+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
+;                                                             ;                    ;       ;
+; Global signals                                              ; 1                  ;       ;
+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
+; Global clocks                                               ; 1 / 16             ; 6 %   ;
+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;
+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 2.7% / 3.0% / 1.9% ;       ;
+; Maximum fan-out                                             ; 68                 ;       ;
+; Highest non-global fan-out                                  ; 68                 ;       ;
+; Total fan-out                                               ; 1448               ;       ;
+; Average fan-out                                             ; 2.89               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                          ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 159 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 159                   ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 162 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 36                    ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 120                   ; 0                              ;
+;         [c] ALMs used for registers                         ; 6                     ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
+;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Difficulty packing design                                   ; Low                   ; Low                            ;
+;                                                             ;                       ;                                ;
+; Total LABs:  partially or completely used                   ; 19 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 19                    ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Combinational ALUT usage for logic                          ; 290                   ; 0                              ;
+;     -- 7 input functions                                    ; 0                     ; 0                              ;
+;     -- 6 input functions                                    ; 41                    ; 0                              ;
+;     -- 5 input functions                                    ; 5                     ; 0                              ;
+;     -- 4 input functions                                    ; 157                   ; 0                              ;
+;     -- <=3 input functions                                  ; 87                    ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 1                     ; 0                              ;
+; Memory ALUT usage                                           ; 0                     ; 0                              ;
+;     -- 64-address deep                                      ; 0                     ; 0                              ;
+;     -- 32-address deep                                      ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Dedicated logic registers                                   ; 0                     ; 0                              ;
+;     -- By type:                                             ;                       ;                                ;
+;         -- Primary logic registers                          ; 84 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 11 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
+;     -- By function:                                         ;                       ;                                ;
+;         -- Design implementation registers                  ; 84                    ; 0                              ;
+;         -- Routing optimization registers                   ; 11                    ; 0                              ;
+;                                                             ;                       ;                                ;
+;                                                             ;                       ;                                ;
+; Virtual pins                                                ; 0                     ; 0                              ;
+; I/O pins                                                    ; 57                    ; 0                              ;
+; I/O registers                                               ; 0                     ; 0                              ;
+; Total block memory bits                                     ; 0                     ; 0                              ;
+; Total block memory implementation bits                      ; 0                     ; 0                              ;
+; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;
+;                                                             ;                       ;                                ;
+; Connections                                                 ;                       ;                                ;
+;     -- Input Connections                                    ; 0                     ; 0                              ;
+;     -- Registered Input Connections                         ; 0                     ; 0                              ;
+;     -- Output Connections                                   ; 0                     ; 0                              ;
+;     -- Registered Output Connections                        ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Internal Connections                                        ;                       ;                                ;
+;     -- Total Connections                                    ; 1448                  ; 0                              ;
+;     -- Registered Connections                               ; 438                   ; 0                              ;
+;                                                             ;                       ;                                ;
+; External Connections                                        ;                       ;                                ;
+;     -- Top                                                  ; 0                     ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Partition Interface                                         ;                       ;                                ;
+;     -- Input Ports                                          ; 5                     ; 0                              ;
+;     -- Output Ports                                         ; 52                    ; 0                              ;
+;     -- Bidir Ports                                          ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Registered Ports                                            ;                       ;                                ;
+;     -- Registered Input Ports                               ; 0                     ; 0                              ;
+;     -- Registered Output Ports                              ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Port Connectivity                                           ;                       ;                                ;
+;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 27                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[2]   ; W15   ; 3B       ; 40           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[3]   ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 3                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[0] ; V25   ; 5B       ; 89           ; 20           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[1] ; AA28  ; 5B       ; 89           ; 21           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[2] ; Y27   ; 5B       ; 89           ; 25           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[3] ; AB27  ; 5B       ; 89           ; 23           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[4] ; AB26  ; 5A       ; 89           ; 9            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[5] ; AA26  ; 5B       ; 89           ; 23           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[6] ; AA25  ; 5A       ; 89           ; 9            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[0] ; V16   ; 4A       ; 52           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[1] ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[2] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[3] ; V18   ; 4A       ; 80           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[4] ; W17   ; 4A       ; 60           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[5] ; W19   ; 4A       ; 80           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[6] ; Y19   ; 4A       ; 84           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[7] ; W20   ; 5A       ; 89           ; 6            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[8] ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[9] ; Y21   ; 5A       ; 89           ; 6            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-----------------------------------------------------------------------------+
+; I/O Bank Usage                                                              ;
++----------+-------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+-------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
+; 3A       ; 0 / 32 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 3B       ; 5 / 48 ( 10 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 4A       ; 7 / 80 ( 9 % )    ; 3.3V          ; --           ; 3.3V          ;
+; 5A       ; 32 / 32 ( 100 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 5B       ; 13 / 16 ( 81 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 6B       ; 0 / 44 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
++----------+-------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                  ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA25     ; 224        ; 5A             ; HEX5[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA26     ; 252        ; 5B             ; HEX5[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA28     ; 251        ; 5B             ; HEX5[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB26     ; 226        ; 5A             ; HEX5[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB27     ; 254        ; 5B             ; HEX5[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V16      ; 138        ; 4A             ; LEDR[0]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V17      ; 154        ; 4A             ; LEDR[2]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V18      ; 194        ; 4A             ; LEDR[3]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V25      ; 246        ; 5B             ; HEX5[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W15      ; 130        ; 3B             ; KEY[2]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W16      ; 136        ; 4A             ; LEDR[1]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W17      ; 152        ; 4A             ; LEDR[4]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W19      ; 192        ; 4A             ; LEDR[5]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W20      ; 217        ; 5A             ; LEDR[7]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W21      ; 221        ; 5A             ; LEDR[8]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y16      ; 128        ; 3B             ; KEY[3]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y19      ; 202        ; 4A             ; LEDR[6]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y21      ; 219        ; 5A             ; LEDR[9]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y27      ; 258        ; 5B             ; HEX5[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                               ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+; |ex9                       ; 158.5 (0.5)          ; 161.5 (0.5)                      ; 3.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 290 (1)             ; 95 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
+;    |LFSR:LFSR0|            ; 3.0 (3.0)            ; 3.3 (3.3)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 7 (7)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
+;    |bin2bcd_16:BCD|        ; 67.7 (0.0)           ; 68.0 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 124 (0)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
+;       |add3_ge5:A1|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
+;       |add3_ge5:A10|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
+;       |add3_ge5:A11|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
+;       |add3_ge5:A12|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
+;       |add3_ge5:A13|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
+;       |add3_ge5:A14|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
+;       |add3_ge5:A15|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
+;       |add3_ge5:A16|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
+;       |add3_ge5:A17|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
+;       |add3_ge5:A18|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
+;       |add3_ge5:A19|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
+;       |add3_ge5:A2|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
+;       |add3_ge5:A20|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
+;       |add3_ge5:A21|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
+;       |add3_ge5:A22|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
+;       |add3_ge5:A23|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
+;       |add3_ge5:A24|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
+;       |add3_ge5:A25|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
+;       |add3_ge5:A26|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
+;       |add3_ge5:A27|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
+;       |add3_ge5:A28|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
+;       |add3_ge5:A29|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
+;       |add3_ge5:A3|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
+;       |add3_ge5:A30|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
+;       |add3_ge5:A32|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
+;       |add3_ge5:A33|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
+;       |add3_ge5:A34|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
+;       |add3_ge5:A35|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
+;       |add3_ge5:A4|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
+;       |add3_ge5:A5|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
+;       |add3_ge5:A6|        ; 3.7 (3.7)            ; 4.0 (4.0)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
+;       |add3_ge5:A7|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
+;       |add3_ge5:A8|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
+;       |add3_ge5:A9|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
+;    |counter_16:COUNT0|     ; 8.5 (8.5)            ; 8.6 (8.6)                        ; 0.1 (0.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (17)             ; 17 (17)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
+;    |delay:DEL0|            ; 14.3 (14.3)          ; 15.4 (15.4)                      ; 1.1 (1.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 25 (25)             ; 18 (18)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
+;    |formula_fsm:FSM|       ; 24.5 (24.5)          ; 25.3 (25.3)                      ; 0.8 (0.8)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 43 (43)             ; 26 (26)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
+;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG1|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG2|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG3|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG4|      ; 7.5 (7.5)            ; 7.5 (7.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
+;    |tick_50000:TICK0|      ; 18.5 (18.5)          ; 18.9 (18.9)                      ; 0.4 (0.4)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (36)             ; 27 (27)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                     ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; KEY[1]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; KEY[2]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; KEY[0]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; CLOCK_50 ; Input    ; -- ; (0)  ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; KEY[3]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                ;
++-------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                             ; Pad To Core Index ; Setting ;
++-------------------------------------------------+-------------------+---------+
+; KEY[1]                                          ;                   ;         ;
+; KEY[2]                                          ;                   ;         ;
+; KEY[0]                                          ;                   ;         ;
+;      - counter_16:COUNT0|count~0                ; 1                 ; 0       ;
+; CLOCK_50                                        ;                   ;         ;
+;      - tick_50000:TICK0|CLK_OUT                 ; 1                 ; 0       ;
+; KEY[3]                                          ;                   ;         ;
+;      - formula_fsm:FSM|Selector3~0              ; 1                 ; 0       ;
+;      - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~0 ; 1                 ; 0       ;
+;      - formula_fsm:FSM|Selector2~0              ; 1                 ; 0       ;
++-------------------------------------------------+-------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                            ; PIN_AF14           ; 2       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                            ; PIN_AF14           ; 26      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; counter_16:COUNT0|count~0           ; LABCELL_X60_Y4_N30 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; counter_16:COUNT0|state             ; FF_X59_Y4_N14      ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; delay:DEL0|count[5]~0               ; LABCELL_X62_Y4_N51 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; delay:DEL0|state.COUNTING           ; FF_X63_Y4_N56      ; 19      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X62_Y4_N56      ; 26      ; Clock enable, Latch enable ; no     ; --                   ; --               ; --                        ;
+; formula_fsm:FSM|state.WAIT_TRIGGER  ; FF_X61_Y4_N2       ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; tick_50000:TICK0|CLK_OUT            ; FF_X60_Y4_N2       ; 68      ; Clock                      ; no     ; --                   ; --               ; --                        ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                         ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 26      ; Global Clock         ; GCLK6            ; --                        ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary                                                 ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type                       ; Usage                   ;
++---------------------------------------------+-------------------------+
+; Block interconnects                         ; 375 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 2 / 13,420 ( < 1 % )    ;
+; C2 interconnects                            ; 132 / 119,108 ( < 1 % ) ;
+; C4 interconnects                            ; 84 / 56,300 ( < 1 % )   ;
+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
+; Direct links                                ; 62 / 289,320 ( < 1 % )  ;
+; Global clocks                               ; 1 / 16 ( 6 % )          ;
+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
+; Local interconnects                         ; 147 / 84,580 ( < 1 % )  ;
+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
+; R14 interconnects                           ; 25 / 12,676 ( < 1 % )   ;
+; R14/C12 interconnect drivers                ; 26 / 20,720 ( < 1 % )   ;
+; R3 interconnects                            ; 160 / 130,992 ( < 1 % ) ;
+; R6 interconnects                            ; 252 / 266,960 ( < 1 % ) ;
+; Spine clocks                                ; 1 / 360 ( < 1 % )       ;
+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                  ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 57        ; 0            ; 57        ; 0            ; 0            ; 57        ; 57        ; 0            ; 57        ; 57        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 57           ; 0         ; 57           ; 57           ; 0         ; 0         ; 57           ; 0         ; 0         ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; KEY[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[8]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[9]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; KEY[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                                               ;
++--------------------------------------------------------------+--------------------------+-------------------+
+; Source Clock(s)                                              ; Destination Clock(s)     ; Delay Added in ns ;
++--------------------------------------------------------------+--------------------------+-------------------+
+; tick_50000:TICK0|CLK_OUT                                     ; tick_50000:TICK0|CLK_OUT ; 62.3              ;
+; CLOCK_50                                                     ; CLOCK_50                 ; 9.8               ;
+; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.7               ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS                          ; tick_50000:TICK0|CLK_OUT ; 3.2               ;
+; tick_50000:TICK0|CLK_OUT,I/O                                 ; tick_50000:TICK0|CLK_OUT ; 1.6               ;
++--------------------------------------------------------------+--------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++--------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                    ;
++----------------------------------------+-------------------------------------+-------------------+
+; Source Register                        ; Destination Register                ; Delay Added in ns ;
++----------------------------------------+-------------------------------------+-------------------+
+; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; formula_fsm:FSM|ledr[3]             ; 2.057             ;
+; formula_fsm:FSM|start_delay            ; delay:DEL0|state.IDLE               ; 1.568             ;
+; tick_50000:TICK0|count[5]              ; tick_50000:TICK0|CLK_OUT            ; 1.369             ;
+; tick_50000:TICK0|count[11]             ; tick_50000:TICK0|CLK_OUT            ; 1.341             ;
+; tick_50000:TICK0|count[14]             ; tick_50000:TICK0|CLK_OUT            ; 1.313             ;
+; tick_50000:TICK0|count[15]             ; tick_50000:TICK0|CLK_OUT            ; 1.313             ;
+; tick_50000:TICK0|count[6]              ; tick_50000:TICK0|CLK_OUT            ; 1.267             ;
+; tick_50000:TICK0|count[12]             ; tick_50000:TICK0|CLK_OUT            ; 1.232             ;
+; tick_50000:TICK0|count[3]              ; tick_50000:TICK0|CLK_OUT            ; 1.227             ;
+; tick_50000:TICK0|count[8]              ; tick_50000:TICK0|CLK_OUT            ; 1.224             ;
+; tick_50000:TICK0|count[13]             ; tick_50000:TICK0|CLK_OUT            ; 1.214             ;
+; tick_50000:TICK0|count[9]              ; tick_50000:TICK0|CLK_OUT            ; 1.207             ;
+; tick_50000:TICK0|count[4]              ; tick_50000:TICK0|CLK_OUT            ; 1.206             ;
+; tick_50000:TICK0|count[7]              ; tick_50000:TICK0|CLK_OUT            ; 1.192             ;
+; tick_50000:TICK0|count[0]              ; tick_50000:TICK0|CLK_OUT            ; 1.189             ;
+; tick_50000:TICK0|count[1]              ; tick_50000:TICK0|CLK_OUT            ; 1.170             ;
+; tick_50000:TICK0|count[2]              ; tick_50000:TICK0|CLK_OUT            ; 1.169             ;
+; tick_50000:TICK0|count[10]             ; tick_50000:TICK0|CLK_OUT            ; 1.155             ;
+; delay:DEL0|count[13]                   ; delay:DEL0|count[11]                ; 0.995             ;
+; formula_fsm:FSM|count[1]               ; formula_fsm:FSM|count[1]            ; 0.879             ;
+; formula_fsm:FSM|count[6]               ; formula_fsm:FSM|count[5]            ; 0.876             ;
+; formula_fsm:FSM|count[9]               ; formula_fsm:FSM|count[5]            ; 0.866             ;
+; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[3]             ; 0.865             ;
+; delay:DEL0|state.IDLE                  ; delay:DEL0|state.COUNTING           ; 0.863             ;
+; formula_fsm:FSM|count[0]               ; formula_fsm:FSM|count[1]            ; 0.855             ;
+; formula_fsm:FSM|count[7]               ; formula_fsm:FSM|count[5]            ; 0.852             ;
+; delay:DEL0|count[0]                    ; delay:DEL0|count[11]                ; 0.851             ;
+; delay:DEL0|count[3]                    ; delay:DEL0|count[11]                ; 0.848             ;
+; delay:DEL0|count[9]                    ; delay:DEL0|count[11]                ; 0.836             ;
+; delay:DEL0|count[8]                    ; delay:DEL0|count[11]                ; 0.833             ;
+; delay:DEL0|count[1]                    ; delay:DEL0|count[11]                ; 0.830             ;
+; formula_fsm:FSM|ledr[0]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[1]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[2]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[3]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[4]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[5]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[6]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[7]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[8]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[9]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; KEY[3]                                 ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|state.WAIT_TRIGGER     ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; delay:DEL0|state.TIME_OUT              ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; delay:DEL0|count[6]                    ; delay:DEL0|count[11]                ; 0.820             ;
+; delay:DEL0|state.COUNTING              ; delay:DEL0|state.IDLE               ; 0.805             ;
+; formula_fsm:FSM|count[4]               ; formula_fsm:FSM|count[1]            ; 0.801             ;
+; delay:DEL0|count[7]                    ; delay:DEL0|count[11]                ; 0.800             ;
+; delay:DEL0|state.WAIT_LOW              ; delay:DEL0|state.IDLE               ; 0.784             ;
+; delay:DEL0|count[4]                    ; delay:DEL0|count[11]                ; 0.779             ;
+; formula_fsm:FSM|count[8]               ; formula_fsm:FSM|count[10]           ; 0.751             ;
+; delay:DEL0|count[10]                   ; delay:DEL0|count[11]                ; 0.743             ;
+; formula_fsm:FSM|count[2]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
+; formula_fsm:FSM|count[3]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
+; formula_fsm:FSM|count[5]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
+; formula_fsm:FSM|count[10]              ; formula_fsm:FSM|count[5]            ; 0.741             ;
+; formula_fsm:FSM|count[11]              ; formula_fsm:FSM|count[5]            ; 0.741             ;
+; delay:DEL0|count[11]                   ; delay:DEL0|count[11]                ; 0.720             ;
+; delay:DEL0|count[12]                   ; delay:DEL0|count[11]                ; 0.714             ;
+; delay:DEL0|count[5]                    ; delay:DEL0|count[11]                ; 0.714             ;
+; LFSR:LFSR0|COUNT[1]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.700             ;
+; LFSR:LFSR0|COUNT[7]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.700             ;
+; delay:DEL0|count[2]                    ; delay:DEL0|count[11]                ; 0.673             ;
+; LFSR:LFSR0|COUNT[5]                    ; LFSR:LFSR0|COUNT[6]                 ; 0.631             ;
+; LFSR:LFSR0|COUNT[3]                    ; LFSR:LFSR0|COUNT[4]                 ; 0.626             ;
+; LFSR:LFSR0|COUNT[4]                    ; LFSR:LFSR0|COUNT[5]                 ; 0.613             ;
+; LFSR:LFSR0|COUNT[6]                    ; LFSR:LFSR0|COUNT[7]                 ; 0.613             ;
+; LFSR:LFSR0|COUNT[2]                    ; delay:DEL0|count[8]                 ; 0.610             ;
+; counter_16:COUNT0|count[7]             ; counter_16:COUNT0|count[15]         ; 0.249             ;
+; counter_16:COUNT0|count[1]             ; counter_16:COUNT0|count[15]         ; 0.239             ;
+; counter_16:COUNT0|count[12]            ; counter_16:COUNT0|count[15]         ; 0.238             ;
+; counter_16:COUNT0|count[0]             ; counter_16:COUNT0|count[15]         ; 0.237             ;
+; counter_16:COUNT0|count[8]             ; counter_16:COUNT0|count[15]         ; 0.236             ;
+; counter_16:COUNT0|count[5]             ; counter_16:COUNT0|count[15]         ; 0.236             ;
+; counter_16:COUNT0|count[3]             ; counter_16:COUNT0|count[15]         ; 0.232             ;
+; counter_16:COUNT0|count[13]            ; counter_16:COUNT0|count[15]         ; 0.231             ;
+; counter_16:COUNT0|count[6]             ; counter_16:COUNT0|count[15]         ; 0.228             ;
+; counter_16:COUNT0|count[9]             ; counter_16:COUNT0|count[15]         ; 0.227             ;
+; counter_16:COUNT0|state                ; counter_16:COUNT0|state             ; 0.140             ;
+; KEY[0]                                 ; counter_16:COUNT0|state             ; 0.089             ;
+; counter_16:COUNT0|count[11]            ; counter_16:COUNT0|count[15]         ; 0.053             ;
+; counter_16:COUNT0|count[14]            ; counter_16:COUNT0|count[15]         ; 0.047             ;
+; counter_16:COUNT0|count[2]             ; counter_16:COUNT0|count[15]         ; 0.046             ;
+; counter_16:COUNT0|count[10]            ; counter_16:COUNT0|count[15]         ; 0.043             ;
+; counter_16:COUNT0|count[4]             ; counter_16:COUNT0|count[15]         ; 0.043             ;
+; tick_50000:TICK0|CLK_OUT               ; counter_16:COUNT0|state             ; 0.036             ;
++----------------------------------------+-------------------------------------+-------------------+
+Note: This table only shows the top 86 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex9"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+    Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:12
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:02
+Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 30 warnings
+    Info: Peak virtual memory: 2593 megabytes
+    Info: Processing ended: Wed Dec 07 12:08:09 2016
+    Info: Elapsed time: 00:00:37
+    Info: Total CPU time (on all processors): 00:01:02
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg.
+
+
diff --git a/part_2/ex9/output_files/ex9.fit.smsg b/part_2/ex9/output_files/ex9.fit.smsg
index 9302919..43eead5 100644
--- a/part_2/ex9/output_files/ex9.fit.smsg
+++ b/part_2/ex9/output_files/ex9.fit.smsg
@@ -1,6 +1,6 @@
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
-Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_2/ex9/output_files/ex9.fit.summary b/part_2/ex9/output_files/ex9.fit.summary
index 1195ded..496001c 100644
--- a/part_2/ex9/output_files/ex9.fit.summary
+++ b/part_2/ex9/output_files/ex9.fit.summary
@@ -1,20 +1,20 @@
-Fitter Status : Successful - Wed Dec 07 12:08:07 2016
-Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex9
-Top-level Entity Name : ex9
-Family : Cyclone V
-Device : 5CSEMA5F31C6
-Timing Models : Final
-Logic utilization (in ALMs) : 159 / 32,070 ( < 1 % )
-Total registers : 95
-Total pins : 57 / 457 ( 12 % )
-Total virtual pins : 0
-Total block memory bits : 0 / 4,065,280 ( 0 % )
-Total RAM Blocks : 0 / 397 ( 0 % )
-Total DSP Blocks : 0 / 87 ( 0 % )
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0 / 6 ( 0 % )
-Total DLLs : 0 / 4 ( 0 % )
+Fitter Status : Successful - Wed Dec 07 12:08:07 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex9
+Top-level Entity Name : ex9
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 159 / 32,070 ( < 1 % )
+Total registers : 95
+Total pins : 57 / 457 ( 12 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_2/ex9/output_files/ex9.flow.rpt b/part_2/ex9/output_files/ex9.flow.rpt
index 771324d..1f2bee6 100644
--- a/part_2/ex9/output_files/ex9.flow.rpt
+++ b/part_2/ex9/output_files/ex9.flow.rpt
@@ -1,128 +1,128 @@
-Flow report for ex9
-Wed Dec 07 12:08:29 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Altera and sold by Altera or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Flow Summary                                                                      ;
-+---------------------------------+-------------------------------------------------+
-; Flow Status                     ; Successful - Wed Dec 07 12:08:20 2016           ;
-; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name                   ; ex9                                             ;
-; Top-level Entity Name           ; ex9                                             ;
-; Family                          ; Cyclone V                                       ;
-; Device                          ; 5CSEMA5F31C6                                    ;
-; Timing Models                   ; Final                                           ;
-; Logic utilization (in ALMs)     ; 159 / 32,070 ( < 1 % )                          ;
-; Total registers                 ; 95                                              ;
-; Total pins                      ; 57 / 457 ( 12 % )                               ;
-; Total virtual pins              ; 0                                               ;
-; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
-; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
-; Total HSSI RX PCSs              ; 0                                               ;
-; Total HSSI PMA RX Deserializers ; 0                                               ;
-; Total HSSI TX PCSs              ; 0                                               ;
-; Total HSSI PMA TX Serializers   ; 0                                               ;
-; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
-; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
-+---------------------------------+-------------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings                           ;
-+-------------------+---------------------+
-; Option            ; Setting             ;
-+-------------------+---------------------+
-; Start date & time ; 12/07/2016 12:07:14 ;
-; Main task         ; Compilation         ;
-; Revision Name     ; ex9                 ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                       ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID               ; 260248564297098.148111243406576       ; --            ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
-; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
-; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
-; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
-; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
-+-------------------------------------+---------------------------------------+---------------+-------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:12     ; 1.0                     ; 918 MB              ; 00:00:23                           ;
-; Fitter                    ; 00:00:35     ; 1.0                     ; 2593 MB             ; 00:01:01                           ;
-; Assembler                 ; 00:00:08     ; 1.0                     ; 895 MB              ; 00:00:06                           ;
-; TimeQuest Timing Analyzer ; 00:00:08     ; 1.1                     ; 1213 MB             ; 00:00:06                           ;
-; Total                     ; 00:01:03     ; --                      ; --                  ; 00:01:36                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                        ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Analysis & Synthesis      ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
-; Fitter                    ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
-; Assembler                 ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
-; TimeQuest Timing Analyzer ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
-+---------------------------+------------------+-----------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
-quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9
-quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
-quartus_sta ex9 -c ex9
-
-
-
+Flow report for ex9
+Wed Dec 07 12:08:29 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary                                                                      ;
++---------------------------------+-------------------------------------------------+
+; Flow Status                     ; Successful - Wed Dec 07 12:08:20 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex9                                             ;
+; Top-level Entity Name           ; ex9                                             ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 159 / 32,070 ( < 1 % )                          ;
+; Total registers                 ; 95                                              ;
+; Total pins                      ; 57 / 457 ( 12 % )                               ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 12/07/2016 12:07:14 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ex9                 ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564297098.148111243406576       ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:12     ; 1.0                     ; 918 MB              ; 00:00:23                           ;
+; Fitter                    ; 00:00:35     ; 1.0                     ; 2593 MB             ; 00:01:01                           ;
+; Assembler                 ; 00:00:08     ; 1.0                     ; 895 MB              ; 00:00:06                           ;
+; TimeQuest Timing Analyzer ; 00:00:08     ; 1.1                     ; 1213 MB             ; 00:00:06                           ;
+; Total                     ; 00:01:03     ; --                      ; --                  ; 00:01:36                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
+quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9
+quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
+quartus_sta ex9 -c ex9
+
+
+
diff --git a/part_2/ex9/output_files/ex9.jdi b/part_2/ex9/output_files/ex9.jdi
index 69f89ad..63b9c30 100644
--- a/part_2/ex9/output_files/ex9.jdi
+++ b/part_2/ex9/output_files/ex9.jdi
@@ -1,8 +1,8 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="814875341ee80fb3b165"/>
-  </project>
-  <file_info>
-    <file device="5CSEMA5F31C6" path="ex9.sof" usercode="0xFFFFFFFF"/>
-  </file_info>
-</sld_project_info>
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="814875341ee80fb3b165"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="ex9.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/part_2/ex9/output_files/ex9.map.rpt b/part_2/ex9/output_files/ex9.map.rpt
index e26b2e5..c0ed2ee 100644
--- a/part_2/ex9/output_files/ex9.map.rpt
+++ b/part_2/ex9/output_files/ex9.map.rpt
@@ -1,615 +1,615 @@
-Analysis & Synthesis report for ex9
-Wed Dec 07 12:07:26 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. State Machine - |ex9|delay:DEL0|state
-  9. State Machine - |ex9|formula_fsm:FSM|state
- 10. User-Specified and Inferred Latches
- 11. Registers Removed During Synthesis
- 12. General Register Statistics
- 13. Inverted Register Statistics
- 14. Multiplexer Restructuring Statistics (Restructuring Performed)
- 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
- 16. Parameter Settings for User Entity Instance: formula_fsm:FSM
- 17. Parameter Settings for User Entity Instance: delay:DEL0
- 18. Parameter Settings for User Entity Instance: counter_16:COUNT0
- 19. Port Connectivity Checks: "hex_to_7seg:SEG5"
- 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
- 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
- 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
- 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
- 24. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
- 25. Port Connectivity Checks: "delay:DEL0"
- 26. Post-Synthesis Netlist Statistics for Top Partition
- 27. Elapsed Time Per Partition
- 28. Analysis & Synthesis Messages
- 29. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Altera and sold by Altera or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                      ;
-+---------------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status     ; Successful - Wed Dec 07 12:07:26 2016           ;
-; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name                   ; ex9                                             ;
-; Top-level Entity Name           ; ex9                                             ;
-; Family                          ; Cyclone V                                       ;
-; Logic utilization (in ALMs)     ; N/A                                             ;
-; Total registers                 ; 84                                              ;
-; Total pins                      ; 57                                              ;
-; Total virtual pins              ; 0                                               ;
-; Total block memory bits         ; 0                                               ;
-; Total DSP Blocks                ; 0                                               ;
-; Total HSSI RX PCSs              ; 0                                               ;
-; Total HSSI PMA RX Deserializers ; 0                                               ;
-; Total HSSI TX PCSs              ; 0                                               ;
-; Total HSSI PMA TX Serializers   ; 0                                               ;
-; Total PLLs                      ; 0                                               ;
-; Total DLLs                      ; 0                                               ;
-+---------------------------------+-------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                             ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                                          ; Setting            ; Default Value      ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
-; Top-level entity name                                                           ; ex9                ; ex9                ;
-; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
-; Use smart compilation                                                           ; Off                ; Off                ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
-; Enable compact report table                                                     ; Off                ; Off                ;
-; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
-; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
-; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
-; Preserve fewer node names                                                       ; On                 ; On                 ;
-; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
-; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
-; State Machine Processing                                                        ; Auto               ; Auto               ;
-; Safe State Machine                                                              ; Off                ; Off                ;
-; Extract Verilog State Machines                                                  ; On                 ; On                 ;
-; Extract VHDL State Machines                                                     ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
-; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
-; Parallel Synthesis                                                              ; On                 ; On                 ;
-; DSP Block Balancing                                                             ; Auto               ; Auto               ;
-; NOT Gate Push-Back                                                              ; On                 ; On                 ;
-; Power-Up Don't Care                                                             ; On                 ; On                 ;
-; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
-; Remove Duplicate Registers                                                      ; On                 ; On                 ;
-; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
-; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
-; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
-; Optimization Technique                                                          ; Balanced           ; Balanced           ;
-; Carry Chain Length                                                              ; 70                 ; 70                 ;
-; Auto Carry Chains                                                               ; On                 ; On                 ;
-; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
-; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
-; Auto ROM Replacement                                                            ; On                 ; On                 ;
-; Auto RAM Replacement                                                            ; On                 ; On                 ;
-; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
-; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
-; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
-; Strict RAM Replacement                                                          ; Off                ; Off                ;
-; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
-; Auto Resource Sharing                                                           ; Off                ; Off                ;
-; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
-; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
-; Report Parameter Settings                                                       ; On                 ; On                 ;
-; Report Source Assignments                                                       ; On                 ; On                 ;
-; Report Connectivity Checks                                                      ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
-; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
-; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
-; HDL message level                                                               ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
-; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
-; Clock MUX Protection                                                            ; On                 ; On                 ;
-; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
-; Block Design Naming                                                             ; Auto               ; Auto               ;
-; SDC constraint protection                                                       ; Off                ; Off                ;
-; Synthesis Effort                                                                ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
-; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
-; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
-; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
-; Synthesis Seed                                                                  ; 1                  ; 1                  ;
-; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
-; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.0%      ;
-;     Processors 3-4         ;   0.0%      ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                                    ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                      ; Library ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
-; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v  ;         ;
-; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v        ;         ;
-; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v ;         ;
-; verilog_files/formula_fsm.v      ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v ;         ;
-; verilog_files/delay.v            ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v       ;         ;
-; verilog_files/counter_16.v       ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v  ;         ;
-; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v  ;         ;
-; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v    ;         ;
-; verilog_files/ex9.v              ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v         ;         ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
-
-
-+------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary                            ;
-+---------------------------------------------+--------------------------+
-; Resource                                    ; Usage                    ;
-+---------------------------------------------+--------------------------+
-; Estimate of Logic utilization (ALMs needed) ; 166                      ;
-;                                             ;                          ;
-; Combinational ALUT usage for logic          ; 290                      ;
-;     -- 7 input functions                    ; 0                        ;
-;     -- 6 input functions                    ; 41                       ;
-;     -- 5 input functions                    ; 5                        ;
-;     -- 4 input functions                    ; 157                      ;
-;     -- <=3 input functions                  ; 87                       ;
-;                                             ;                          ;
-; Dedicated logic registers                   ; 84                       ;
-;                                             ;                          ;
-; I/O pins                                    ; 57                       ;
-;                                             ;                          ;
-; Total DSP Blocks                            ; 0                        ;
-;                                             ;                          ;
-; Maximum fan-out node                        ; tick_50000:TICK0|CLK_OUT ;
-; Maximum fan-out                             ; 67                       ;
-; Total fan-out                               ; 1423                     ;
-; Average fan-out                             ; 2.92                     ;
-+---------------------------------------------+--------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex9                       ; 290 (1)           ; 84 (0)       ; 0                 ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
-;    |LFSR:LFSR0|            ; 3 (3)             ; 7 (7)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
-;    |bin2bcd_16:BCD|        ; 124 (0)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A10|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
-;       |add3_ge5:A11|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
-;       |add3_ge5:A12|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
-;       |add3_ge5:A13|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
-;       |add3_ge5:A14|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
-;       |add3_ge5:A15|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
-;       |add3_ge5:A16|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
-;       |add3_ge5:A17|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
-;       |add3_ge5:A18|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
-;       |add3_ge5:A19|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
-;       |add3_ge5:A1|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
-;       |add3_ge5:A20|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
-;       |add3_ge5:A21|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
-;       |add3_ge5:A22|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A23|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
-;       |add3_ge5:A24|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
-;       |add3_ge5:A25|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A27|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
-;       |add3_ge5:A28|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
-;       |add3_ge5:A29|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
-;       |add3_ge5:A2|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
-;       |add3_ge5:A30|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
-;       |add3_ge5:A32|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
-;       |add3_ge5:A33|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
-;       |add3_ge5:A34|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
-;       |add3_ge5:A35|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
-;       |add3_ge5:A3|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
-;       |add3_ge5:A4|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
-;       |add3_ge5:A5|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
-;       |add3_ge5:A6|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
-;       |add3_ge5:A7|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
-;       |add3_ge5:A8|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
-;       |add3_ge5:A9|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
-;    |counter_16:COUNT0|     ; 17 (17)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
-;    |delay:DEL0|            ; 25 (25)           ; 18 (18)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
-;    |formula_fsm:FSM|       ; 43 (43)           ; 25 (25)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
-;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG2|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG3|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG4|      ; 13 (13)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
-;    |tick_50000:TICK0|      ; 36 (36)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------+
-; State Machine - |ex9|delay:DEL0|state                                          ;
-+----------------+----------------+----------------+----------------+------------+
-; Name           ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
-+----------------+----------------+----------------+----------------+------------+
-; state.IDLE     ; 0              ; 0              ; 0              ; 0          ;
-; state.COUNTING ; 0              ; 0              ; 1              ; 1          ;
-; state.TIME_OUT ; 0              ; 1              ; 0              ; 1          ;
-; state.WAIT_LOW ; 1              ; 0              ; 0              ; 1          ;
-+----------------+----------------+----------------+----------------+------------+
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------------------+
-; State Machine - |ex9|formula_fsm:FSM|state                                                 ;
-+------------------------+--------------------+------------------------+---------------------+
-; Name                   ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
-+------------------------+--------------------+------------------------+---------------------+
-; state.WAIT_TRIGGER     ; 0                  ; 0                      ; 0                   ;
-; state.LIGHT_UP_LEDS    ; 1                  ; 0                      ; 1                   ;
-; state.WAIT_FOR_TIMEOUT ; 1                  ; 1                      ; 0                   ;
-+------------------------+--------------------+------------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; User-Specified and Inferred Latches                                                                               ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; Latch Name                                         ; Latch Enable Signal                 ; Free of Timing Hazards ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; formula_fsm:FSM|start_delay                        ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes                    ;
-; Number of user-specified and inferred latches = 1  ;                                     ;                        ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
-
-
-+------------------------------------------------------------+
-; Registers Removed During Synthesis                         ;
-+---------------------------------------+--------------------+
-; Register name                         ; Reason for Removal ;
-+---------------------------------------+--------------------+
-; delay:DEL0|state~5                    ; Lost fanout        ;
-; delay:DEL0|state~6                    ; Lost fanout        ;
-; Total Number of Removed Registers = 2 ;                    ;
-+---------------------------------------+--------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 84    ;
-; Number of registers using Synchronous Clear  ; 16    ;
-; Number of registers using Synchronous Load   ; 15    ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 42    ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+---------------------------------------------------+
-; Inverted Register Statistics                      ;
-+-----------------------------------------+---------+
-; Inverted Register                       ; Fan out ;
-+-----------------------------------------+---------+
-; formula_fsm:FSM|count[1]                ; 2       ;
-; formula_fsm:FSM|count[0]                ; 2       ;
-; formula_fsm:FSM|count[6]                ; 2       ;
-; formula_fsm:FSM|count[7]                ; 2       ;
-; formula_fsm:FSM|count[8]                ; 2       ;
-; formula_fsm:FSM|count[11]               ; 2       ;
-; tick_50000:TICK0|count[14]              ; 2       ;
-; tick_50000:TICK0|count[15]              ; 2       ;
-; tick_50000:TICK0|count[0]               ; 2       ;
-; tick_50000:TICK0|count[1]               ; 2       ;
-; tick_50000:TICK0|count[2]               ; 2       ;
-; tick_50000:TICK0|count[3]               ; 2       ;
-; tick_50000:TICK0|count[6]               ; 2       ;
-; tick_50000:TICK0|count[8]               ; 2       ;
-; tick_50000:TICK0|count[9]               ; 2       ;
-; LFSR:LFSR0|COUNT[1]                     ; 3       ;
-; Total number of inverted registers = 16 ;         ;
-+-----------------------------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |ex9|counter_16:COUNT0|count[0] ;
-; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[5]        ;
-; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[13]       ;
-; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |ex9|formula_fsm:FSM|count[0]   ;
-; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex9|formula_fsm:FSM|Selector3  ;
-; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |ex9|delay:DEL0|Selector16      ;
-; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |ex9|delay:DEL0|Selector17      ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-
-
-+---------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
-+----------------+-------+--------------------------------------+
-; Parameter Name ; Value ; Type                                 ;
-+----------------+-------+--------------------------------------+
-; NBIT           ; 16    ; Signed Integer                       ;
-+----------------+-------+--------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
-+------------------+-------+-----------------------------------+
-; Parameter Name   ; Value ; Type                              ;
-+------------------+-------+-----------------------------------+
-; WAIT_TRIGGER     ; 00    ; Unsigned Binary                   ;
-; LIGHT_UP_LEDS    ; 01    ; Unsigned Binary                   ;
-; WAIT_FOR_TIMEOUT ; 10    ; Unsigned Binary                   ;
-+------------------+-------+-----------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------+
-; Parameter Settings for User Entity Instance: delay:DEL0 ;
-+----------------+-------+--------------------------------+
-; Parameter Name ; Value ; Type                           ;
-+----------------+-------+--------------------------------+
-; BIT_SZ         ; 14    ; Signed Integer                 ;
-; IDLE           ; 00    ; Unsigned Binary                ;
-; COUNTING       ; 01    ; Unsigned Binary                ;
-; TIME_OUT       ; 10    ; Unsigned Binary                ;
-; WAIT_LOW       ; 11    ; Unsigned Binary                ;
-+----------------+-------+--------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: counter_16:COUNT0 ;
-+----------------+-------+---------------------------------------+
-; Parameter Name ; Value ; Type                                  ;
-+----------------+-------+---------------------------------------+
-; BIT_SZ         ; 16    ; Signed Integer                        ;
-; COUNTING       ; 1     ; Unsigned Binary                       ;
-; IDLE           ; 0     ; Unsigned Binary                       ;
-+----------------+-------+---------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------+
-; Port Connectivity Checks: "hex_to_7seg:SEG5" ;
-+------+-------+----------+--------------------+
-; Port ; Type  ; Severity ; Details            ;
-+------+-------+----------+--------------------+
-; in   ; Input ; Info     ; Stuck at GND       ;
-+------+-------+----------+--------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"                                                         ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; Port  ; Type   ; Severity ; Details                                                                             ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; iW[3] ; Input  ; Info     ; Stuck at GND                                                                        ;
-; oA[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
-+-------+-------+----------+------------------------------+
-; Port  ; Type  ; Severity ; Details                      ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                 ;
-+-------+-------+----------+------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
-+-------+-------+----------+------------------------------+
-; Port  ; Type  ; Severity ; Details                      ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                 ;
-+-------+-------+----------+------------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
-+-------+-------+----------+-----------------------------+
-; Port  ; Type  ; Severity ; Details                     ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                ;
-+-------+-------+----------+-----------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
-+-------+-------+----------+-----------------------------+
-; Port  ; Type  ; Severity ; Details                     ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                ;
-+-------+-------+----------+-----------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "delay:DEL0"                                                                                                                                ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type  ; Severity ; Details                                                                                                                                     ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; N    ; Input ; Warning  ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives.  Extra input bit(s) "N[13..7]" will be connected to GND. ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type                  ; Count                       ;
-+-----------------------+-----------------------------+
-; arriav_ff             ; 84                          ;
-;     ENA               ; 12                          ;
-;     ENA SCLR          ; 16                          ;
-;     ENA SLD           ; 14                          ;
-;     SLD               ; 1                           ;
-;     plain             ; 41                          ;
-; arriav_lcell_comb     ; 308                         ;
-;     arith             ; 58                          ;
-;         1 data inputs ; 58                          ;
-;     normal            ; 250                         ;
-;         0 data inputs ; 2                           ;
-;         1 data inputs ; 28                          ;
-;         2 data inputs ; 8                           ;
-;         3 data inputs ; 9                           ;
-;         4 data inputs ; 157                         ;
-;         5 data inputs ; 5                           ;
-;         6 data inputs ; 41                          ;
-; boundary_port         ; 57                          ;
-;                       ;                             ;
-; Max LUT depth         ; 15.00                       ;
-; Average LUT depth     ; 7.32                        ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition    ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top            ; 00:00:01     ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-    Info: Processing started: Wed Dec 07 12:07:13 2016
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
-    Info (12023): Found entity 1: tick_50000 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v
-    Info (12023): Found entity 1: LFSR File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
-    Info (12023): Found entity 1: hex_to_7seg File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
-    Info (12023): Found entity 1: formula_fsm File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
-    Info (12023): Found entity 1: delay File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
-    Info (12023): Found entity 1: counter_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
-    Info (12023): Found entity 1: bin2bcd_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 12
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
-    Info (12023): Found entity 1: add3_ge5 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v Line: 9
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex9.v
-    Info (12023): Found entity 1: ex9 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 1
-Info (12127): Elaborating entity "ex9" for the top level hierarchy
-Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 14
-Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 16
-Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 39
-Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 58
-Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 58
-Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 18
-Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 20
-Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 24
-Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:COUNT0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 22
-Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 24
-Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 26
-Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 26
-Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
-Warning (13024): Output pins are stuck at VCC or GND
-    Warning (13410): Pin "HEX5[0]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[1]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[2]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[3]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[4]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[5]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[6]" is stuck at VCC File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
-Info (286030): Timing-Driven Synthesis is running
-Info (17049): 2 registers lost all their fanouts during netlist optimizations.
-Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
-    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 2 input pin(s) that do not drive logic
-    Warning (15610): No output dependent on input pin "KEY[1]" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 4
-    Warning (15610): No output dependent on input pin "KEY[2]" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 4
-Info (21057): Implemented 354 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 5 input pins
-    Info (21059): Implemented 52 output pins
-    Info (21061): Implemented 297 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
-    Info: Peak virtual memory: 918 megabytes
-    Info: Processing ended: Wed Dec 07 12:07:26 2016
-    Info: Elapsed time: 00:00:13
-    Info: Total CPU time (on all processors): 00:00:23
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg.
-
-
+Analysis & Synthesis report for ex9
+Wed Dec 07 12:07:26 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. State Machine - |ex9|delay:DEL0|state
+  9. State Machine - |ex9|formula_fsm:FSM|state
+ 10. User-Specified and Inferred Latches
+ 11. Registers Removed During Synthesis
+ 12. General Register Statistics
+ 13. Inverted Register Statistics
+ 14. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
+ 16. Parameter Settings for User Entity Instance: formula_fsm:FSM
+ 17. Parameter Settings for User Entity Instance: delay:DEL0
+ 18. Parameter Settings for User Entity Instance: counter_16:COUNT0
+ 19. Port Connectivity Checks: "hex_to_7seg:SEG5"
+ 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
+ 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
+ 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
+ 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
+ 24. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
+ 25. Port Connectivity Checks: "delay:DEL0"
+ 26. Post-Synthesis Netlist Statistics for Top Partition
+ 27. Elapsed Time Per Partition
+ 28. Analysis & Synthesis Messages
+ 29. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Wed Dec 07 12:07:26 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex9                                             ;
+; Top-level Entity Name           ; ex9                                             ;
+; Family                          ; Cyclone V                                       ;
+; Logic utilization (in ALMs)     ; N/A                                             ;
+; Total registers                 ; 84                                              ;
+; Total pins                      ; 57                                              ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0                                               ;
+; Total DSP Blocks                ; 0                                               ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0                                               ;
+; Total DLLs                      ; 0                                               ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; ex9                ; ex9                ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Synthesis Seed                                                                  ; 1                  ; 1                  ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.0%      ;
+;     Processors 3-4         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                    ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                      ; Library ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
+; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v  ;         ;
+; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v        ;         ;
+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v ;         ;
+; verilog_files/formula_fsm.v      ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v ;         ;
+; verilog_files/delay.v            ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v       ;         ;
+; verilog_files/counter_16.v       ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v  ;         ;
+; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v  ;         ;
+; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v    ;         ;
+; verilog_files/ex9.v              ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v         ;         ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
+
+
++------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                            ;
++---------------------------------------------+--------------------------+
+; Resource                                    ; Usage                    ;
++---------------------------------------------+--------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 166                      ;
+;                                             ;                          ;
+; Combinational ALUT usage for logic          ; 290                      ;
+;     -- 7 input functions                    ; 0                        ;
+;     -- 6 input functions                    ; 41                       ;
+;     -- 5 input functions                    ; 5                        ;
+;     -- 4 input functions                    ; 157                      ;
+;     -- <=3 input functions                  ; 87                       ;
+;                                             ;                          ;
+; Dedicated logic registers                   ; 84                       ;
+;                                             ;                          ;
+; I/O pins                                    ; 57                       ;
+;                                             ;                          ;
+; Total DSP Blocks                            ; 0                        ;
+;                                             ;                          ;
+; Maximum fan-out node                        ; tick_50000:TICK0|CLK_OUT ;
+; Maximum fan-out                             ; 67                       ;
+; Total fan-out                               ; 1423                     ;
+; Average fan-out                             ; 2.92                     ;
++---------------------------------------------+--------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; |ex9                       ; 290 (1)           ; 84 (0)       ; 0                 ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
+;    |LFSR:LFSR0|            ; 3 (3)             ; 7 (7)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
+;    |bin2bcd_16:BCD|        ; 124 (0)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
+;       |add3_ge5:A10|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
+;       |add3_ge5:A11|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
+;       |add3_ge5:A12|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
+;       |add3_ge5:A13|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
+;       |add3_ge5:A14|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
+;       |add3_ge5:A15|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
+;       |add3_ge5:A16|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
+;       |add3_ge5:A17|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
+;       |add3_ge5:A18|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
+;       |add3_ge5:A19|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
+;       |add3_ge5:A1|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
+;       |add3_ge5:A20|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
+;       |add3_ge5:A21|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
+;       |add3_ge5:A22|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
+;       |add3_ge5:A23|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
+;       |add3_ge5:A24|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
+;       |add3_ge5:A25|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
+;       |add3_ge5:A26|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
+;       |add3_ge5:A27|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
+;       |add3_ge5:A28|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
+;       |add3_ge5:A29|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
+;       |add3_ge5:A2|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
+;       |add3_ge5:A30|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
+;       |add3_ge5:A32|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
+;       |add3_ge5:A33|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
+;       |add3_ge5:A34|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
+;       |add3_ge5:A35|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
+;       |add3_ge5:A3|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
+;       |add3_ge5:A4|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
+;       |add3_ge5:A5|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
+;       |add3_ge5:A6|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
+;       |add3_ge5:A7|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
+;       |add3_ge5:A8|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
+;       |add3_ge5:A9|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
+;    |counter_16:COUNT0|     ; 17 (17)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
+;    |delay:DEL0|            ; 25 (25)           ; 18 (18)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
+;    |formula_fsm:FSM|       ; 43 (43)           ; 25 (25)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
+;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG1|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG2|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG3|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG4|      ; 13 (13)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
+;    |tick_50000:TICK0|      ; 36 (36)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------------------------+
+; State Machine - |ex9|delay:DEL0|state                                          ;
++----------------+----------------+----------------+----------------+------------+
+; Name           ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
++----------------+----------------+----------------+----------------+------------+
+; state.IDLE     ; 0              ; 0              ; 0              ; 0          ;
+; state.COUNTING ; 0              ; 0              ; 1              ; 1          ;
+; state.TIME_OUT ; 0              ; 1              ; 0              ; 1          ;
+; state.WAIT_LOW ; 1              ; 0              ; 0              ; 1          ;
++----------------+----------------+----------------+----------------+------------+
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------------------------------------+
+; State Machine - |ex9|formula_fsm:FSM|state                                                 ;
++------------------------+--------------------+------------------------+---------------------+
+; Name                   ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
++------------------------+--------------------+------------------------+---------------------+
+; state.WAIT_TRIGGER     ; 0                  ; 0                      ; 0                   ;
+; state.LIGHT_UP_LEDS    ; 1                  ; 0                      ; 1                   ;
+; state.WAIT_FOR_TIMEOUT ; 1                  ; 1                      ; 0                   ;
++------------------------+--------------------+------------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; User-Specified and Inferred Latches                                                                               ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; Latch Name                                         ; Latch Enable Signal                 ; Free of Timing Hazards ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; formula_fsm:FSM|start_delay                        ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes                    ;
+; Number of user-specified and inferred latches = 1  ;                                     ;                        ;
++----------------------------------------------------+-------------------------------------+------------------------+
+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+
+
++------------------------------------------------------------+
+; Registers Removed During Synthesis                         ;
++---------------------------------------+--------------------+
+; Register name                         ; Reason for Removal ;
++---------------------------------------+--------------------+
+; delay:DEL0|state~5                    ; Lost fanout        ;
+; delay:DEL0|state~6                    ; Lost fanout        ;
+; Total Number of Removed Registers = 2 ;                    ;
++---------------------------------------+--------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 84    ;
+; Number of registers using Synchronous Clear  ; 16    ;
+; Number of registers using Synchronous Load   ; 15    ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 42    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++---------------------------------------------------+
+; Inverted Register Statistics                      ;
++-----------------------------------------+---------+
+; Inverted Register                       ; Fan out ;
++-----------------------------------------+---------+
+; formula_fsm:FSM|count[1]                ; 2       ;
+; formula_fsm:FSM|count[0]                ; 2       ;
+; formula_fsm:FSM|count[6]                ; 2       ;
+; formula_fsm:FSM|count[7]                ; 2       ;
+; formula_fsm:FSM|count[8]                ; 2       ;
+; formula_fsm:FSM|count[11]               ; 2       ;
+; tick_50000:TICK0|count[14]              ; 2       ;
+; tick_50000:TICK0|count[15]              ; 2       ;
+; tick_50000:TICK0|count[0]               ; 2       ;
+; tick_50000:TICK0|count[1]               ; 2       ;
+; tick_50000:TICK0|count[2]               ; 2       ;
+; tick_50000:TICK0|count[3]               ; 2       ;
+; tick_50000:TICK0|count[6]               ; 2       ;
+; tick_50000:TICK0|count[8]               ; 2       ;
+; tick_50000:TICK0|count[9]               ; 2       ;
+; LFSR:LFSR0|COUNT[1]                     ; 3       ;
+; Total number of inverted registers = 16 ;         ;
++-----------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |ex9|counter_16:COUNT0|count[0] ;
+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[5]        ;
+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[13]       ;
+; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |ex9|formula_fsm:FSM|count[0]   ;
+; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex9|formula_fsm:FSM|Selector3  ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |ex9|delay:DEL0|Selector16      ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |ex9|delay:DEL0|Selector17      ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+
+
++---------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
++----------------+-------+--------------------------------------+
+; Parameter Name ; Value ; Type                                 ;
++----------------+-------+--------------------------------------+
+; NBIT           ; 16    ; Signed Integer                       ;
++----------------+-------+--------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
++------------------+-------+-----------------------------------+
+; Parameter Name   ; Value ; Type                              ;
++------------------+-------+-----------------------------------+
+; WAIT_TRIGGER     ; 00    ; Unsigned Binary                   ;
+; LIGHT_UP_LEDS    ; 01    ; Unsigned Binary                   ;
+; WAIT_FOR_TIMEOUT ; 10    ; Unsigned Binary                   ;
++------------------+-------+-----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------+
+; Parameter Settings for User Entity Instance: delay:DEL0 ;
++----------------+-------+--------------------------------+
+; Parameter Name ; Value ; Type                           ;
++----------------+-------+--------------------------------+
+; BIT_SZ         ; 14    ; Signed Integer                 ;
+; IDLE           ; 00    ; Unsigned Binary                ;
+; COUNTING       ; 01    ; Unsigned Binary                ;
+; TIME_OUT       ; 10    ; Unsigned Binary                ;
+; WAIT_LOW       ; 11    ; Unsigned Binary                ;
++----------------+-------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: counter_16:COUNT0 ;
++----------------+-------+---------------------------------------+
+; Parameter Name ; Value ; Type                                  ;
++----------------+-------+---------------------------------------+
+; BIT_SZ         ; 16    ; Signed Integer                        ;
+; COUNTING       ; 1     ; Unsigned Binary                       ;
+; IDLE           ; 0     ; Unsigned Binary                       ;
++----------------+-------+---------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------+
+; Port Connectivity Checks: "hex_to_7seg:SEG5" ;
++------+-------+----------+--------------------+
+; Port ; Type  ; Severity ; Details            ;
++------+-------+----------+--------------------+
+; in   ; Input ; Info     ; Stuck at GND       ;
++------+-------+----------+--------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"                                                         ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; Port  ; Type   ; Severity ; Details                                                                             ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; iW[3] ; Input  ; Info     ; Stuck at GND                                                                        ;
+; oA[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
++-------+-------+----------+------------------------------+
+; Port  ; Type  ; Severity ; Details                      ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                 ;
++-------+-------+----------+------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
++-------+-------+----------+------------------------------+
+; Port  ; Type  ; Severity ; Details                      ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                 ;
++-------+-------+----------+------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
++-------+-------+----------+-----------------------------+
+; Port  ; Type  ; Severity ; Details                     ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                ;
++-------+-------+----------+-----------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
++-------+-------+----------+-----------------------------+
+; Port  ; Type  ; Severity ; Details                     ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                ;
++-------+-------+----------+-----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "delay:DEL0"                                                                                                                                ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                                                                                                                     ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; N    ; Input ; Warning  ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives.  Extra input bit(s) "N[13..7]" will be connected to GND. ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_ff             ; 84                          ;
+;     ENA               ; 12                          ;
+;     ENA SCLR          ; 16                          ;
+;     ENA SLD           ; 14                          ;
+;     SLD               ; 1                           ;
+;     plain             ; 41                          ;
+; arriav_lcell_comb     ; 308                         ;
+;     arith             ; 58                          ;
+;         1 data inputs ; 58                          ;
+;     normal            ; 250                         ;
+;         0 data inputs ; 2                           ;
+;         1 data inputs ; 28                          ;
+;         2 data inputs ; 8                           ;
+;         3 data inputs ; 9                           ;
+;         4 data inputs ; 157                         ;
+;         5 data inputs ; 5                           ;
+;         6 data inputs ; 41                          ;
+; boundary_port         ; 57                          ;
+;                       ;                             ;
+; Max LUT depth         ; 15.00                       ;
+; Average LUT depth     ; 7.32                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:01     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Wed Dec 07 12:07:13 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
+    Info (12023): Found entity 1: tick_50000 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v
+    Info (12023): Found entity 1: LFSR File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+    Info (12023): Found entity 1: hex_to_7seg File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
+    Info (12023): Found entity 1: formula_fsm File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
+    Info (12023): Found entity 1: delay File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
+    Info (12023): Found entity 1: counter_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+    Info (12023): Found entity 1: bin2bcd_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+    Info (12023): Found entity 1: add3_ge5 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex9.v
+    Info (12023): Found entity 1: ex9 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 1
+Info (12127): Elaborating entity "ex9" for the top level hierarchy
+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 14
+Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 16
+Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 39
+Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 58
+Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 58
+Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 18
+Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 20
+Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 24
+Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:COUNT0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 22
+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 24
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 26
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 26
+Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "HEX5[0]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[1]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[2]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[3]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[4]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[5]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[6]" is stuck at VCC File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 2 registers lost all their fanouts during netlist optimizations.
+Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 2 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "KEY[1]" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 4
+    Warning (15610): No output dependent on input pin "KEY[2]" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 4
+Info (21057): Implemented 354 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 5 input pins
+    Info (21059): Implemented 52 output pins
+    Info (21061): Implemented 297 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
+    Info: Peak virtual memory: 918 megabytes
+    Info: Processing ended: Wed Dec 07 12:07:26 2016
+    Info: Elapsed time: 00:00:13
+    Info: Total CPU time (on all processors): 00:00:23
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg.
+
+
diff --git a/part_2/ex9/output_files/ex9.map.smsg b/part_2/ex9/output_files/ex9.map.smsg
index 0279e74..f6657db 100644
--- a/part_2/ex9/output_files/ex9.map.smsg
+++ b/part_2/ex9/output_files/ex9.map.smsg
@@ -1,37 +1,37 @@
-Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 38
-Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 7
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 38
+Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
diff --git a/part_2/ex9/output_files/ex9.map.summary b/part_2/ex9/output_files/ex9.map.summary
index f7a9e70..e668523 100644
--- a/part_2/ex9/output_files/ex9.map.summary
+++ b/part_2/ex9/output_files/ex9.map.summary
@@ -1,17 +1,17 @@
-Analysis & Synthesis Status : Successful - Wed Dec 07 12:07:26 2016
-Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex9
-Top-level Entity Name : ex9
-Family : Cyclone V
-Logic utilization (in ALMs) : N/A
-Total registers : 84
-Total pins : 57
-Total virtual pins : 0
-Total block memory bits : 0
-Total DSP Blocks : 0
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0
-Total DLLs : 0
+Analysis & Synthesis Status : Successful - Wed Dec 07 12:07:26 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex9
+Top-level Entity Name : ex9
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 84
+Total pins : 57
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_2/ex9/output_files/ex9.pin b/part_2/ex9/output_files/ex9.pin
index 59318a8..6b2c6db 100644
--- a/part_2/ex9/output_files/ex9.pin
+++ b/part_2/ex9/output_files/ex9.pin
@@ -1,976 +1,976 @@
- -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
- -- Your use of Altera Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Altera Program License 
- -- Subscription Agreement, the Altera Quartus Prime License Agreement,
- -- the Altera MegaCore Function License Agreement, or other 
- -- applicable license agreement, including, without limitation, 
- -- that your use is for the sole purpose of programming logic 
- -- devices manufactured by Altera and sold by Altera or its 
- -- authorized distributors.  Please refer to the applicable 
- -- agreement for further details.
- -- 
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --                  Bank 3A:       2.5V
- --                  Bank 3B:       3.3V
- --                  Bank 4A:       3.3V
- --                  Bank 5A:       3.3V
- --                  Bank 5B:       3.3V
- --                  Bank 6B:       2.5V
- --                  Bank 6A:  2.5V
- --                  Bank 7A:  2.5V
- --                  Bank 7B:  2.5V
- --                  Bank 7C:  2.5V
- --                  Bank 7D:  2.5V
- --                  Bank 8A:  2.5V
- -- RREF          : External reference resistor for the quad, MUST be connected to
- --                 GND via a 2k Ohm resistor.
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --                  It can also be used to report unused dedicated pins. The connection
- --                  on the board for unused dedicated pins depends on whether this will
- --                  be used in a future design. One example is device migration. When
- --                  using device migration, refer to the device pin-tables. If it is a
- --                  GND pin in the pin table or if it will not be used in a future design
- --                  for another purpose the it MUST be connected to GND. If it is an unused
- --                  dedicated pin, then it can be connected to a valid signal on the board
- --                  (low, high, or toggling) if that signal is required for a different
- --                  revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --                  This pin should be connected to GND. It may also be connected  to a
- --                  valid signal  on the board  (low, high, or toggling)  if that signal
- --                  is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --                  or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
- --                 must not be connected.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-CHIP  "ex9"  ASSIGNED TO AN: 5CSEMA5F31C6
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : A2        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
-VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
-GND                          : A12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
-GND                          : A17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
-GND                          : A22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
-GND                          : A26       :        :                   :         : 7A        :                
-GND                          : A27       : gnd    :                   :         :           :                
-HPS_TRST                     : A28       :        :                   :         : 7A        :                
-HPS_TMS                      : A29       :        :                   :         : 7A        :                
-GND                          : AA1       : gnd    :                   :         :           :                
-GND                          : AA2       : gnd    :                   :         :           :                
-GND                          : AA3       : gnd    :                   :         :           :                
-GND                          : AA4       : gnd    :                   :         :           :                
-VCC                          : AA5       : power  :                   : 1.1V    :           :                
-GND                          : AA6       : gnd    :                   :         :           :                
-DNU                          : AA7       :        :                   :         :           :                
-VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
-GND                          : AA9       : gnd    :                   :         :           :                
-VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
-GND                          : AA11      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
-KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
-VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
-GND                          : AA22      : gnd    :                   :         :           :                
-VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[6]                      : AA25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[5]                      : AA26      : output : 3.3-V LVTTL       :         : 5B        : Y              
-VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
-HEX5[1]                      : AA28      : output : 3.3-V LVTTL       :         : 5B        : Y              
-VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
-GND                          : AB1       : gnd    :                   :         :           :                
-GND                          : AB2       : gnd    :                   :         :           :                
-DNU                          : AB3       :        :                   :         :           :                
-DNU                          : AB4       :        :                   :         :           :                
-GND                          : AB5       : gnd    :                   :         :           :                
-VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
-GND                          : AB7       : gnd    :                   :         :           :                
-nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
-TDO                          : AB9       : output :                   :         : 3A        :                
-VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
-VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
-VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
-VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
-GND                          : AB19      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
-HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
-HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[4]                      : AB26      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[3]                      : AB27      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              
-GND                          : AB29      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
-GND                          : AC1       : gnd    :                   :         :           :                
-GND                          : AC2       : gnd    :                   :         :           :                
-GND                          : AC3       : gnd    :                   :         :           :                
-GND                          : AC4       : gnd    :                   :         :           :                
-TCK                          : AC5       : input  :                   :         : 3A        :                
-GND                          : AC6       : gnd    :                   :         :           :                
-AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
-GND                          : AC8       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
-VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
-VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
-VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
-VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
-GND                          : AC16      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
-VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
-VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
-VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
-HEX3[3]                      : AC25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : AC26      : gnd    :                   :         :           :                
-HEX3[1]                      : AC27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
-GND                          : AD1       : gnd    :                   :         :           :                
-GND                          : AD2       : gnd    :                   :         :           :                
-DNU                          : AD3       :        :                   :         :           :                
-DNU                          : AD4       :        :                   :         :           :                
-GND                          : AD5       : gnd    :                   :         :           :                
-VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
-VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
-VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
-DNU                          : AD15      :        :                   :         :           :                
-VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
-VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
-VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
-GND                          : AD23      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
-HEX3[2]                      : AD25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX3[0]                      : AD26      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
-HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
-GND                          : AE1       : gnd    :                   :         :           :                
-GND                          : AE2       : gnd    :                   :         :           :                
-GND                          : AE3       : gnd    :                   :         :           :                
-GND                          : AE4       : gnd    :                   :         :           :                
-AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
-AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
-AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
-GND                          : AE10      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
-VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
-GND                          : AE20      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
-VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
-HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
-GND                          : AF1       : gnd    :                   :         :           :                
-GND                          : AF2       : gnd    :                   :         :           :                
-GND                          : AF3       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
-VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
-GND                          : AF12      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
-CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
-GND                          : AF17      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
-VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
-GND                          : AF27      : gnd    :                   :         :           :                
-HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
-VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
-GND                          : AG9       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
-GND                          : AG14      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
-VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
-GND                          : AG24      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
-HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
-HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : AH1       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
-GND                          : AH6       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
-GND                          : AH11      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
-VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
-GND                          : AH21      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
-VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
-HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
-GND                          : AJ3       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
-VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
-VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
-VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
-GND                          : AJ18      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
-VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
-GND                          : AJ28      : gnd    :                   :         :           :                
-HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : AJ30      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
-GND                          : AK5       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
-VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
-GND                          : AK15      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
-VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
-VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
-GND                          : AK25      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
-VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
-GND                          : B9        : gnd    :                   :         :           :                
-VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
-GND                          : B14       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
-GND                          : B19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
-GND                          : B24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
-HPS_TDI                      : B27       :        :                   :         : 7A        :                
-HPS_TDO                      : B28       :        :                   :         : 7A        :                
-GND                          : B29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
-GND                          : C1        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
-GND                          : C6        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
-VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
-GND                          : C16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
-GND                          : C21       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
-GND                          : C26       : gnd    :                   :         :           :                
-HPS_nRST                     : C27       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
-GND                          : D3        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
-VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
-GND                          : D13       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
-VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
-GND                          : D23       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
-HPS_CLK1                     : D25       :        :                   :         : 7A        :                
-GND                          : D26       :        :                   :         : 7A        :                
-HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
-VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
-GND                          : E10       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
-VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
-VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
-VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
-GND                          : E25       : gnd    :                   :         :           :                
-DNU                          : E26       :        :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
-GND                          : E30       : gnd    :                   :         :           :                
-DNU                          : F1        :        :                   :         :           :                
-GND                          : F2        : gnd    :                   :         :           :                
-CONF_DONE                    : F3        :        :                   :         : 9A        :                
-nSTATUS                      : F4        :        :                   :         : 9A        :                
-GND                          : F5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
-GND                          : F7        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
-VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
-GND                          : F17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
-VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
-HPS_nPOR                     : F23       :        :                   :         : 7A        :                
-HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
-HPS_CLK2                     : F25       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
-GND                          : F27       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
-GND                          : G1        :        :                   :         :           :                
-DNU                          : G2        :        :                   :         :           :                
-GND                          : G3        : gnd    :                   :         :           :                
-GND                          : G4        : gnd    :                   :         :           :                
-nCE                          : G5        :        :                   :         : 9A        :                
-MSEL2                        : G6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
-VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
-VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
-VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
-VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
-GND                          : G24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
-GND                          : H1        : gnd    :                   :         :           :                
-GND                          : H2        : gnd    :                   :         :           :                
-DNU                          : H3        :        :                   :         :           :                
-DNU                          : H4        :        :                   :         :           :                
-GND                          : H5        : gnd    :                   :         :           :                
-VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
-VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
-VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
-GND                          : H11       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
-VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
-VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
-HPS_TCK                      : H22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
-GND                          : J1        : gnd    :                   :         :           :                
-GND                          : J2        : gnd    :                   :         :           :                
-GND                          : J3        : gnd    :                   :         :           :                
-GND                          : J4        : gnd    :                   :         :           :                
-nCONFIG                      : J5        :        :                   :         : 9A        :                
-GND                          : J6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
-GND                          : J8        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
-VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
-VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
-DNU                          : J15       :        :                   :         :           :                
-VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
-VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
-GND                          : J18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
-VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
-GND                          : J22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
-GND                          : J28       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
-GND                          : K1        : gnd    :                   :         :           :                
-GND                          : K2        : gnd    :                   :         :           :                
-DNU                          : K3        :        :                   :         :           :                
-DNU                          : K4        :        :                   :         :           :                
-GND                          : K5        : gnd    :                   :         :           :                
-MSEL1                        : K6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
-VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
-GND                          : K10       : gnd    :                   :         :           :                
-VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
-VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
-GND                          : K15       : gnd    :                   :         :           :                
-VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
-VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
-VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
-GND                          : K20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
-GND                          : K25       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
-GND                          : L1        : gnd    :                   :         :           :                
-GND                          : L2        : gnd    :                   :         :           :                
-GND                          : L3        : gnd    :                   :         :           :                
-GND                          : L4        : gnd    :                   :         :           :                
-VCC                          : L5        : power  :                   : 1.1V    :           :                
-GND                          : L6        : gnd    :                   :         :           :                
-MSEL3                        : L7        :        :                   :         : 9A        :                
-MSEL0                        : L8        :        :                   :         : 9A        :                
-MSEL4                        : L9        :        :                   :         : 9A        :                
-VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
-GND                          : L11       : gnd    :                   :         :           :                
-VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
-GND                          : L13       : gnd    :                   :         :           :                
-VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
-GND                          : L15       : gnd    :                   :         :           :                
-VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
-GND                          : L17       : gnd    :                   :         :           :                
-VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
-GND                          : L19       : gnd    :                   :         :           :                
-VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
-VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
-GND                          : L22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
-GND                          : M1        : gnd    :                   :         :           :                
-GND                          : M2        : gnd    :                   :         :           :                
-DNU                          : M3        :        :                   :         :           :                
-DNU                          : M4        :        :                   :         :           :                
-GND                          : M5        : gnd    :                   :         :           :                
-VCC                          : M6        : power  :                   : 1.1V    :           :                
-GND                          : M7        : gnd    :                   :         :           :                
-GND                          : M8        : gnd    :                   :         :           :                
-VCC                          : M9        : power  :                   : 1.1V    :           :                
-GND                          : M10       : gnd    :                   :         :           :                
-VCC                          : M11       : power  :                   : 1.1V    :           :                
-GND                          : M12       : gnd    :                   :         :           :                
-VCC                          : M13       : power  :                   : 1.1V    :           :                
-GND                          : M14       : gnd    :                   :         :           :                
-VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
-GND                          : M16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
-GND                          : M18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
-GND                          : M20       : gnd    :                   :         :           :                
-VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
-GND                          : M29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
-GND                          : N1        : gnd    :                   :         :           :                
-GND                          : N2        : gnd    :                   :         :           :                
-GND                          : N3        : gnd    :                   :         :           :                
-GND                          : N4        : gnd    :                   :         :           :                
-VCC                          : N5        : power  :                   : 1.1V    :           :                
-GND                          : N6        : gnd    :                   :         :           :                
-VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
-GND                          : N8        : gnd    :                   :         :           :                
-GND                          : N9        : gnd    :                   :         :           :                
-VCC                          : N10       : power  :                   : 1.1V    :           :                
-GND                          : N11       : gnd    :                   :         :           :                
-VCC                          : N12       : power  :                   : 1.1V    :           :                
-GND                          : N13       : gnd    :                   :         :           :                
-VCC                          : N14       : power  :                   : 1.1V    :           :                
-GND                          : N15       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
-GND                          : N17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
-GND                          : N19       : gnd    :                   :         :           :                
-VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
-VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
-VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
-GND                          : N26       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
-GND                          : P1        : gnd    :                   :         :           :                
-GND                          : P2        : gnd    :                   :         :           :                
-DNU                          : P3        :        :                   :         :           :                
-DNU                          : P4        :        :                   :         :           :                
-GND                          : P5        : gnd    :                   :         :           :                
-VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
-GND                          : P7        : gnd    :                   :         :           :                
-GND                          : P8        : gnd    :                   :         :           :                
-GND                          : P9        : gnd    :                   :         :           :                
-GND                          : P10       : gnd    :                   :         :           :                
-VCC                          : P11       : power  :                   : 1.1V    :           :                
-GND                          : P12       : gnd    :                   :         :           :                
-VCC                          : P13       : power  :                   : 1.1V    :           :                
-GND                          : P14       : gnd    :                   :         :           :                
-VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
-GND                          : P16       : gnd    :                   :         :           :                
-VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
-GND                          : P18       : gnd    :                   :         :           :                
-VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
-GND                          : P20       : gnd    :                   :         :           :                
-VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
-GND                          : R1        : gnd    :                   :         :           :                
-GND                          : R2        : gnd    :                   :         :           :                
-GND                          : R3        : gnd    :                   :         :           :                
-GND                          : R4        : gnd    :                   :         :           :                
-VCC                          : R5        : power  :                   : 1.1V    :           :                
-GND                          : R6        : gnd    :                   :         :           :                
-VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
-GND                          : R8        : gnd    :                   :         :           :                
-GND                          : R9        : gnd    :                   :         :           :                
-VCC                          : R10       : power  :                   : 1.1V    :           :                
-GND                          : R11       : gnd    :                   :         :           :                
-VCC                          : R12       : power  :                   : 1.1V    :           :                
-GND                          : R13       : gnd    :                   :         :           :                
-VCC                          : R14       : power  :                   : 1.1V    :           :                
-GND                          : R15       : gnd    :                   :         :           :                
-VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
-GND                          : R17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
-VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
-VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
-GND                          : R30       : gnd    :                   :         :           :                
-GND                          : T1        : gnd    :                   :         :           :                
-GND                          : T2        : gnd    :                   :         :           :                
-DNU                          : T3        :        :                   :         :           :                
-DNU                          : T4        :        :                   :         :           :                
-GND                          : T5        : gnd    :                   :         :           :                
-VCC                          : T6        : power  :                   : 1.1V    :           :                
-GND                          : T7        : gnd    :                   :         :           :                
-GND                          : T8        : gnd    :                   :         :           :                
-GND                          : T9        : gnd    :                   :         :           :                
-GND                          : T10       : gnd    :                   :         :           :                
-VCC                          : T11       : power  :                   : 1.1V    :           :                
-GND                          : T12       : gnd    :                   :         :           :                
-VCC                          : T13       : power  :                   : 1.1V    :           :                
-GND                          : T14       : gnd    :                   :         :           :                
-GND                          : T15       : gnd    :                   :         :           :                
-GND                          : T16       : gnd    :                   :         :           :                
-VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
-GND                          : T18       : gnd    :                   :         :           :                
-VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
-GND                          : T20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
-GND                          : T27       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
-GND                          : U1        : gnd    :                   :         :           :                
-GND                          : U2        : gnd    :                   :         :           :                
-GND                          : U3        : gnd    :                   :         :           :                
-GND                          : U4        : gnd    :                   :         :           :                
-VCC                          : U5        : power  :                   : 1.1V    :           :                
-GND                          : U6        : gnd    :                   :         :           :                
-DCLK                         : U7        :        :                   :         : 3A        :                
-TDI                          : U8        : input  :                   :         : 3A        :                
-GND                          : U9        : gnd    :                   :         :           :                
-VCC                          : U10       : power  :                   : 1.1V    :           :                
-GND                          : U11       : gnd    :                   :         :           :                
-VCC                          : U12       : power  :                   : 1.1V    :           :                
-GND                          : U13       : gnd    :                   :         :           :                
-VCC                          : U14       : power  :                   : 1.1V    :           :                
-GND                          : U15       : gnd    :                   :         :           :                
-VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
-GND                          : U17       : gnd    :                   :         :           :                
-VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
-VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
-VCC                          : U21       : power  :                   : 1.1V    :           :                
-GND                          : U22       : gnd    :                   :         :           :                
-VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
-GND                          : U24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
-GND                          : U29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
-GND                          : V1        : gnd    :                   :         :           :                
-GND                          : V2        : gnd    :                   :         :           :                
-DNU                          : V3        :        :                   :         :           :                
-DNU                          : V4        :        :                   :         :           :                
-GND                          : V5        : gnd    :                   :         :           :                
-VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
-GND                          : V7        : gnd    :                   :         :           :                
-VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
-TMS                          : V9        : input  :                   :         : 3A        :                
-GND                          : V10       : gnd    :                   :         :           :                
-VCC                          : V11       : power  :                   : 1.1V    :           :                
-GND                          : V12       : gnd    :                   :         :           :                
-VCC                          : V13       : power  :                   : 1.1V    :           :                
-GND                          : V14       : gnd    :                   :         :           :                
-VCC                          : V15       : power  :                   : 1.1V    :           :                
-LEDR[0]                      : V16       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[2]                      : V17       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[3]                      : V18       : output : 3.3-V LVTTL       :         : 4A        : Y              
-GND                          : V19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
-GND                          : V21       : gnd    :                   :         :           :                
-VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
-HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
-HEX5[0]                      : V25       : output : 3.3-V LVTTL       :         : 5B        : Y              
-VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
-GND                          : W1        : gnd    :                   :         :           :                
-GND                          : W2        : gnd    :                   :         :           :                
-GND                          : W3        : gnd    :                   :         :           :                
-GND                          : W4        : gnd    :                   :         :           :                
-VCC                          : W5        : power  :                   : 1.1V    :           :                
-GND                          : W6        : gnd    :                   :         :           :                
-GND                          : W7        : gnd    :                   :         :           :                
-GND                          : W8        : gnd    :                   :         :           :                
-GND                          : W9        : gnd    :                   :         :           :                
-VCC                          : W10       : power  :                   : 1.1V    :           :                
-GND                          : W11       : gnd    :                   :         :           :                
-VCC                          : W12       : power  :                   : 1.1V    :           :                
-GND                          : W13       : gnd    :                   :         :           :                
-VCC                          : W14       : power  :                   : 1.1V    :           :                
-KEY[2]                       : W15       : input  : 3.3-V LVTTL       :         : 3B        : Y              
-LEDR[1]                      : W16       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[4]                      : W17       : output : 3.3-V LVTTL       :         : 4A        : Y              
-GND                          : W18       : gnd    :                   :         :           :                
-LEDR[5]                      : W19       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[7]                      : W20       : output : 3.3-V LVTTL       :         : 5A        : Y              
-LEDR[8]                      : W21       : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
-HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX4[6]                      : W25       : output : 3.3-V LVTTL       :         : 5B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
-GND                          : W28       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
-GND                          : Y1        : gnd    :                   :         :           :                
-GND                          : Y2        : gnd    :                   :         :           :                
-DNU                          : Y3        :        :                   :         :           :                
-DNU                          : Y4        :        :                   :         :           :                
-GND                          : Y5        : gnd    :                   :         :           :                
-VCC                          : Y6        : power  :                   : 1.1V    :           :                
-GND                          : Y7        : gnd    :                   :         :           :                
-GND                          : Y8        : gnd    :                   :         :           :                
-VCC                          : Y9        : power  :                   : 1.1V    :           :                
-GND                          : Y10       : gnd    :                   :         :           :                
-VCC                          : Y11       : power  :                   : 1.1V    :           :                
-GND                          : Y12       : gnd    :                   :         :           :                
-VCC                          : Y13       : power  :                   : 1.1V    :           :                
-GND                          : Y14       : gnd    :                   :         :           :                
-GND                          : Y15       : gnd    :                   :         :           :                
-KEY[3]                       : Y16       : input  : 3.3-V LVTTL       :         : 3B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
-LEDR[6]                      : Y19       : output : 3.3-V LVTTL       :         : 4A        : Y              
-GND                          : Y20       : gnd    :                   :         :           :                
-LEDR[9]                      : Y21       : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
-HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : Y25       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
-HEX5[2]                      : Y27       : output : 3.3-V LVTTL       :         : 5B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
-GND                          : Y30       : gnd    :                   :         :           :                
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other 
+ -- applicable license agreement, including, without limitation, 
+ -- that your use is for the sole purpose of programming logic 
+ -- devices manufactured by Altera and sold by Altera or its 
+ -- authorized distributors.  Please refer to the applicable 
+ -- agreement for further details.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       2.5V
+ --                  Bank 3B:       3.3V
+ --                  Bank 4A:       3.3V
+ --                  Bank 5A:       3.3V
+ --                  Bank 5B:       3.3V
+ --                  Bank 6B:       2.5V
+ --                  Bank 6A:  2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 7B:  2.5V
+ --                  Bank 7C:  2.5V
+ --                  Bank 7D:  2.5V
+ --                  Bank 8A:  2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP  "ex9"  ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
+GND                          : A12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
+GND                          : A17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
+GND                          : A26       :        :                   :         : 7A        :                
+GND                          : A27       : gnd    :                   :         :           :                
+HPS_TRST                     : A28       :        :                   :         : 7A        :                
+HPS_TMS                      : A29       :        :                   :         : 7A        :                
+GND                          : AA1       : gnd    :                   :         :           :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+VCC                          : AA5       : power  :                   : 1.1V    :           :                
+GND                          : AA6       : gnd    :                   :         :           :                
+DNU                          : AA7       :        :                   :         :           :                
+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
+GND                          : AA9       : gnd    :                   :         :           :                
+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
+KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
+GND                          : AA22      : gnd    :                   :         :           :                
+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX5[6]                      : AA25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX5[5]                      : AA26      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
+HEX5[1]                      : AA28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+DNU                          : AB3       :        :                   :         :           :                
+DNU                          : AB4       :        :                   :         :           :                
+GND                          : AB5       : gnd    :                   :         :           :                
+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
+GND                          : AB7       : gnd    :                   :         :           :                
+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
+TDO                          : AB9       : output :                   :         : 3A        :                
+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AB19      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
+HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
+HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX5[4]                      : AB26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX5[3]                      : AB27      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AB29      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
+GND                          : AC1       : gnd    :                   :         :           :                
+GND                          : AC2       : gnd    :                   :         :           :                
+GND                          : AC3       : gnd    :                   :         :           :                
+GND                          : AC4       : gnd    :                   :         :           :                
+TCK                          : AC5       : input  :                   :         : 3A        :                
+GND                          : AC6       : gnd    :                   :         :           :                
+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
+GND                          : AC8       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AC16      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
+HEX3[3]                      : AC25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AC26      : gnd    :                   :         :           :                
+HEX3[1]                      : AC27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AD1       : gnd    :                   :         :           :                
+GND                          : AD2       : gnd    :                   :         :           :                
+DNU                          : AD3       :        :                   :         :           :                
+DNU                          : AD4       :        :                   :         :           :                
+GND                          : AD5       : gnd    :                   :         :           :                
+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
+DNU                          : AD15      :        :                   :         :           :                
+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
+GND                          : AD23      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
+HEX3[2]                      : AD25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX3[0]                      : AD26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AE1       : gnd    :                   :         :           :                
+GND                          : AE2       : gnd    :                   :         :           :                
+GND                          : AE3       : gnd    :                   :         :           :                
+GND                          : AE4       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
+GND                          : AE10      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
+GND                          : AE20      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
+GND                          : AF1       : gnd    :                   :         :           :                
+GND                          : AF2       : gnd    :                   :         :           :                
+GND                          : AF3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
+GND                          : AF12      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
+GND                          : AF17      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
+GND                          : AF27      : gnd    :                   :         :           :                
+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
+GND                          : AG9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
+GND                          : AG14      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
+GND                          : AG24      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AH1       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
+GND                          : AH6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
+GND                          : AH11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
+GND                          : AH21      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
+GND                          : AJ3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
+GND                          : AJ18      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
+GND                          : AJ28      : gnd    :                   :         :           :                
+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AJ30      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
+GND                          : AK5       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
+GND                          : AK15      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
+GND                          : AK25      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
+GND                          : B19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
+GND                          : B24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
+HPS_TDI                      : B27       :        :                   :         : 7A        :                
+HPS_TDO                      : B28       :        :                   :         : 7A        :                
+GND                          : B29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
+GND                          : C1        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
+GND                          : C6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
+GND                          : C21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
+GND                          : C26       : gnd    :                   :         :           :                
+HPS_nRST                     : C27       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
+GND                          : D3        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
+GND                          : D13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GND                          : D23       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
+HPS_CLK1                     : D25       :        :                   :         : 7A        :                
+GND                          : D26       :        :                   :         : 7A        :                
+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+GND                          : E10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
+GND                          : E25       : gnd    :                   :         :           :                
+DNU                          : E26       :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
+GND                          : E30       : gnd    :                   :         :           :                
+DNU                          : F1        :        :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+CONF_DONE                    : F3        :        :                   :         : 9A        :                
+nSTATUS                      : F4        :        :                   :         : 9A        :                
+GND                          : F5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
+GND                          : F7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
+GND                          : F17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
+HPS_nPOR                     : F23       :        :                   :         : 7A        :                
+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
+HPS_CLK2                     : F25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
+GND                          : F27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
+GND                          : G1        :        :                   :         :           :                
+DNU                          : G2        :        :                   :         :           :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        : gnd    :                   :         :           :                
+nCE                          : G5        :        :                   :         : 9A        :                
+MSEL2                        : G6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
+GND                          : G24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+DNU                          : H3        :        :                   :         :           :                
+DNU                          : H4        :        :                   :         :           :                
+GND                          : H5        : gnd    :                   :         :           :                
+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
+GND                          : H11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
+HPS_TCK                      : H22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
+GND                          : J1        : gnd    :                   :         :           :                
+GND                          : J2        : gnd    :                   :         :           :                
+GND                          : J3        : gnd    :                   :         :           :                
+GND                          : J4        : gnd    :                   :         :           :                
+nCONFIG                      : J5        :        :                   :         : 9A        :                
+GND                          : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+GND                          : J8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
+DNU                          : J15       :        :                   :         :           :                
+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
+GND                          : J18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
+GND                          : J22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
+GND                          : J28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+DNU                          : K3        :        :                   :         :           :                
+DNU                          : K4        :        :                   :         :           :                
+GND                          : K5        : gnd    :                   :         :           :                
+MSEL1                        : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
+GND                          : K15       : gnd    :                   :         :           :                
+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
+GND                          : K20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
+GND                          : K25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
+GND                          : L1        : gnd    :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+GND                          : L3        : gnd    :                   :         :           :                
+GND                          : L4        : gnd    :                   :         :           :                
+VCC                          : L5        : power  :                   : 1.1V    :           :                
+GND                          : L6        : gnd    :                   :         :           :                
+MSEL3                        : L7        :        :                   :         : 9A        :                
+MSEL0                        : L8        :        :                   :         : 9A        :                
+MSEL4                        : L9        :        :                   :         : 9A        :                
+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
+GND                          : L17       : gnd    :                   :         :           :                
+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
+GND                          : L19       : gnd    :                   :         :           :                
+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
+GND                          : L22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+DNU                          : M3        :        :                   :         :           :                
+DNU                          : M4        :        :                   :         :           :                
+GND                          : M5        : gnd    :                   :         :           :                
+VCC                          : M6        : power  :                   : 1.1V    :           :                
+GND                          : M7        : gnd    :                   :         :           :                
+GND                          : M8        : gnd    :                   :         :           :                
+VCC                          : M9        : power  :                   : 1.1V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
+GND                          : M16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
+GND                          : M18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
+GND                          : M20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
+GND                          : M29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
+GND                          : N1        : gnd    :                   :         :           :                
+GND                          : N2        : gnd    :                   :         :           :                
+GND                          : N3        : gnd    :                   :         :           :                
+GND                          : N4        : gnd    :                   :         :           :                
+VCC                          : N5        : power  :                   : 1.1V    :           :                
+GND                          : N6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
+GND                          : N8        : gnd    :                   :         :           :                
+GND                          : N9        : gnd    :                   :         :           :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
+GND                          : N17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
+GND                          : N19       : gnd    :                   :         :           :                
+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
+GND                          : N26       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+DNU                          : P3        :        :                   :         :           :                
+DNU                          : P4        :        :                   :         :           :                
+GND                          : P5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
+GND                          : P7        : gnd    :                   :         :           :                
+GND                          : P8        : gnd    :                   :         :           :                
+GND                          : P9        : gnd    :                   :         :           :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+GND                          : P14       : gnd    :                   :         :           :                
+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
+GND                          : P16       : gnd    :                   :         :           :                
+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
+GND                          : P18       : gnd    :                   :         :           :                
+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
+GND                          : P20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
+GND                          : R1        : gnd    :                   :         :           :                
+GND                          : R2        : gnd    :                   :         :           :                
+GND                          : R3        : gnd    :                   :         :           :                
+GND                          : R4        : gnd    :                   :         :           :                
+VCC                          : R5        : power  :                   : 1.1V    :           :                
+GND                          : R6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
+GND                          : R8        : gnd    :                   :         :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCC                          : R10       : power  :                   : 1.1V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCC                          : R12       : power  :                   : 1.1V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+VCC                          : R14       : power  :                   : 1.1V    :           :                
+GND                          : R15       : gnd    :                   :         :           :                
+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
+GND                          : R17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
+GND                          : R30       : gnd    :                   :         :           :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+DNU                          : T3        :        :                   :         :           :                
+DNU                          : T4        :        :                   :         :           :                
+GND                          : T5        : gnd    :                   :         :           :                
+VCC                          : T6        : power  :                   : 1.1V    :           :                
+GND                          : T7        : gnd    :                   :         :           :                
+GND                          : T8        : gnd    :                   :         :           :                
+GND                          : T9        : gnd    :                   :         :           :                
+GND                          : T10       : gnd    :                   :         :           :                
+VCC                          : T11       : power  :                   : 1.1V    :           :                
+GND                          : T12       : gnd    :                   :         :           :                
+VCC                          : T13       : power  :                   : 1.1V    :           :                
+GND                          : T14       : gnd    :                   :         :           :                
+GND                          : T15       : gnd    :                   :         :           :                
+GND                          : T16       : gnd    :                   :         :           :                
+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
+GND                          : T18       : gnd    :                   :         :           :                
+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
+GND                          : T20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
+GND                          : T27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
+GND                          : U1        : gnd    :                   :         :           :                
+GND                          : U2        : gnd    :                   :         :           :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        : gnd    :                   :         :           :                
+VCC                          : U5        : power  :                   : 1.1V    :           :                
+GND                          : U6        : gnd    :                   :         :           :                
+DCLK                         : U7        :        :                   :         : 3A        :                
+TDI                          : U8        : input  :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+VCC                          : U10       : power  :                   : 1.1V    :           :                
+GND                          : U11       : gnd    :                   :         :           :                
+VCC                          : U12       : power  :                   : 1.1V    :           :                
+GND                          : U13       : gnd    :                   :         :           :                
+VCC                          : U14       : power  :                   : 1.1V    :           :                
+GND                          : U15       : gnd    :                   :         :           :                
+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
+GND                          : U17       : gnd    :                   :         :           :                
+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
+VCC                          : U21       : power  :                   : 1.1V    :           :                
+GND                          : U22       : gnd    :                   :         :           :                
+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
+GND                          : U24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
+GND                          : U29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DNU                          : V3        :        :                   :         :           :                
+DNU                          : V4        :        :                   :         :           :                
+GND                          : V5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
+TMS                          : V9        : input  :                   :         : 3A        :                
+GND                          : V10       : gnd    :                   :         :           :                
+VCC                          : V11       : power  :                   : 1.1V    :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+VCC                          : V13       : power  :                   : 1.1V    :           :                
+GND                          : V14       : gnd    :                   :         :           :                
+VCC                          : V15       : power  :                   : 1.1V    :           :                
+LEDR[0]                      : V16       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[2]                      : V17       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[3]                      : V18       : output : 3.3-V LVTTL       :         : 4A        : Y              
+GND                          : V19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
+GND                          : V21       : gnd    :                   :         :           :                
+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
+HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
+HEX5[0]                      : V25       : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
+GND                          : W1        : gnd    :                   :         :           :                
+GND                          : W2        : gnd    :                   :         :           :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+VCC                          : W5        : power  :                   : 1.1V    :           :                
+GND                          : W6        : gnd    :                   :         :           :                
+GND                          : W7        : gnd    :                   :         :           :                
+GND                          : W8        : gnd    :                   :         :           :                
+GND                          : W9        : gnd    :                   :         :           :                
+VCC                          : W10       : power  :                   : 1.1V    :           :                
+GND                          : W11       : gnd    :                   :         :           :                
+VCC                          : W12       : power  :                   : 1.1V    :           :                
+GND                          : W13       : gnd    :                   :         :           :                
+VCC                          : W14       : power  :                   : 1.1V    :           :                
+KEY[2]                       : W15       : input  : 3.3-V LVTTL       :         : 3B        : Y              
+LEDR[1]                      : W16       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[4]                      : W17       : output : 3.3-V LVTTL       :         : 4A        : Y              
+GND                          : W18       : gnd    :                   :         :           :                
+LEDR[5]                      : W19       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[7]                      : W20       : output : 3.3-V LVTTL       :         : 5A        : Y              
+LEDR[8]                      : W21       : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
+HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX4[6]                      : W25       : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
+GND                          : W28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+DNU                          : Y3        :        :                   :         :           :                
+DNU                          : Y4        :        :                   :         :           :                
+GND                          : Y5        : gnd    :                   :         :           :                
+VCC                          : Y6        : power  :                   : 1.1V    :           :                
+GND                          : Y7        : gnd    :                   :         :           :                
+GND                          : Y8        : gnd    :                   :         :           :                
+VCC                          : Y9        : power  :                   : 1.1V    :           :                
+GND                          : Y10       : gnd    :                   :         :           :                
+VCC                          : Y11       : power  :                   : 1.1V    :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VCC                          : Y13       : power  :                   : 1.1V    :           :                
+GND                          : Y14       : gnd    :                   :         :           :                
+GND                          : Y15       : gnd    :                   :         :           :                
+KEY[3]                       : Y16       : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
+LEDR[6]                      : Y19       : output : 3.3-V LVTTL       :         : 4A        : Y              
+GND                          : Y20       : gnd    :                   :         :           :                
+LEDR[9]                      : Y21       : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
+HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : Y25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
+HEX5[2]                      : Y27       : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
+GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/part_2/ex9/output_files/ex9.sld b/part_2/ex9/output_files/ex9.sld
index f7d3ed7..41a6030 100644
--- a/part_2/ex9/output_files/ex9.sld
+++ b/part_2/ex9/output_files/ex9.sld
@@ -1 +1 @@
-<sld_project_info/>
+<sld_project_info/>
diff --git a/part_2/ex9/output_files/ex9.sta.rpt b/part_2/ex9/output_files/ex9.sta.rpt
index 59e2e79..1c3b355 100644
--- a/part_2/ex9/output_files/ex9.sta.rpt
+++ b/part_2/ex9/output_files/ex9.sta.rpt
@@ -1,1005 +1,1005 @@
-TimeQuest Timing Analyzer report for ex9
-Wed Dec 07 12:08:30 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. Clocks
-  5. Slow 1100mV 85C Model Fmax Summary
-  6. Timing Closure Recommendations
-  7. Slow 1100mV 85C Model Setup Summary
-  8. Slow 1100mV 85C Model Hold Summary
-  9. Slow 1100mV 85C Model Recovery Summary
- 10. Slow 1100mV 85C Model Removal Summary
- 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1100mV 85C Model Metastability Summary
- 13. Slow 1100mV 0C Model Fmax Summary
- 14. Slow 1100mV 0C Model Setup Summary
- 15. Slow 1100mV 0C Model Hold Summary
- 16. Slow 1100mV 0C Model Recovery Summary
- 17. Slow 1100mV 0C Model Removal Summary
- 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1100mV 0C Model Metastability Summary
- 20. Fast 1100mV 85C Model Setup Summary
- 21. Fast 1100mV 85C Model Hold Summary
- 22. Fast 1100mV 85C Model Recovery Summary
- 23. Fast 1100mV 85C Model Removal Summary
- 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
- 25. Fast 1100mV 85C Model Metastability Summary
- 26. Fast 1100mV 0C Model Setup Summary
- 27. Fast 1100mV 0C Model Hold Summary
- 28. Fast 1100mV 0C Model Recovery Summary
- 29. Fast 1100mV 0C Model Removal Summary
- 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
- 31. Fast 1100mV 0C Model Metastability Summary
- 32. Multicorner Timing Analysis Summary
- 33. Board Trace Model Assignments
- 34. Input Transition Times
- 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
- 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
- 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
- 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
- 39. Setup Transfers
- 40. Hold Transfers
- 41. Report TCCS
- 42. Report RSKM
- 43. Unconstrained Paths Summary
- 44. Clock Status Summary
- 45. Unconstrained Input Ports
- 46. Unconstrained Output Ports
- 47. Unconstrained Input Ports
- 48. Unconstrained Output Ports
- 49. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Altera and sold by Altera or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                               ;
-+-----------------------+---------------------------------------------------------+
-; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Timing Analyzer       ; TimeQuest                                               ;
-; Revision Name         ; ex9                                                     ;
-; Device Family         ; Cyclone V                                               ;
-; Device Name           ; 5CSEMA5F31C6                                            ;
-; Timing Models         ; Final                                                   ;
-; Delay Model           ; Combined                                                ;
-; Rise/Fall Delays      ; Enabled                                                 ;
-+-----------------------+---------------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.10        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   3.3%      ;
-;     Processor 3            ;   3.3%      ;
-;     Processor 4            ;   3.2%      ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                                                                                   ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; Clock Name                          ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                 ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; CLOCK_50                            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                            ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
-; tick_50000:TICK0|CLK_OUT            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_50000:TICK0|CLK_OUT }            ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-
-
-+----------------------------------------------------------------+
-; Slow 1100mV 85C Model Fmax Summary                             ;
-+------------+-----------------+--------------------------+------+
-; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
-+------------+-----------------+--------------------------+------+
-; 224.11 MHz ; 224.11 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
-; 328.19 MHz ; 328.19 MHz      ; CLOCK_50                 ;      ;
-+------------+-----------------+--------------------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Setup Summary                          ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -3.462 ; -161.413      ;
-; CLOCK_50                            ; -2.047 ; -40.775       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675 ; -1.675        ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Slow 1100mV 85C Model Hold Summary                          ;
-+-------------------------------------+-------+---------------+
-; Clock                               ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; 0.179 ; 0.000         ;
-; CLOCK_50                            ; 0.385 ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.629 ; 0.000         ;
-+-------------------------------------+-------+---------------+
-
-
-------------------------------------------
-; Slow 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Minimum Pulse Width Summary            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.637 ; -18.132       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -38.762       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.459  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------------
-; Slow 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------+
-; Slow 1100mV 0C Model Fmax Summary                              ;
-+------------+-----------------+--------------------------+------+
-; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
-+------------+-----------------+--------------------------+------+
-; 226.45 MHz ; 226.45 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
-; 300.93 MHz ; 300.93 MHz      ; CLOCK_50                 ;      ;
-+------------+-----------------+--------------------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Setup Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -3.416 ; -157.230      ;
-; CLOCK_50                            ; -2.323 ; -41.799       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.568 ; -1.568        ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Slow 1100mV 0C Model Hold Summary                           ;
-+-------------------------------------+-------+---------------+
-; Clock                               ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; 0.193 ; 0.000         ;
-; CLOCK_50                            ; 0.405 ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.501 ; 0.000         ;
-+-------------------------------------+-------+---------------+
-
-
------------------------------------------
-; Slow 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Minimum Pulse Width Summary             ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.689 ; -16.816       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -38.286       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.412  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
-----------------------------------------------
-; Slow 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Setup Summary                          ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -1.794 ; -79.872       ;
-; CLOCK_50                            ; -0.918 ; -13.912       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.572 ; -0.572        ;
-+-------------------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Hold Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -0.020 ; -0.037        ;
-; CLOCK_50                            ; 0.185  ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.202  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
-------------------------------------------
-; Fast 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Minimum Pulse Width Summary            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.740 ; -12.957       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.012 ; -0.190        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.478  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------------
-; Fast 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Setup Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -1.581 ; -69.264       ;
-; CLOCK_50                            ; -0.868 ; -11.639       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.462 ; -0.462        ;
-+-------------------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Hold Summary                            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -0.021 ; -0.052        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.122  ; 0.000         ;
-; CLOCK_50                            ; 0.177  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------
-; Fast 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Minimum Pulse Width Summary             ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.789 ; -15.486       ;
-; tick_50000:TICK0|CLK_OUT            ; 0.024  ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.468  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
-----------------------------------------------
-; Fast 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary                                                                 ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-; Clock                                ; Setup    ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-; Worst-case Slack                     ; -3.462   ; -0.021 ; N/A      ; N/A     ; -0.789              ;
-;  CLOCK_50                            ; -2.323   ; 0.177  ; N/A      ; N/A     ; -0.789              ;
-;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675   ; 0.122  ; N/A      ; N/A     ; 0.412               ;
-;  tick_50000:TICK0|CLK_OUT            ; -3.462   ; -0.021 ; N/A      ; N/A     ; -0.394              ;
-; Design-wide TNS                      ; -203.863 ; -0.052 ; 0.0      ; 0.0     ; -56.894             ;
-;  CLOCK_50                            ; -41.799  ; 0.000  ; N/A      ; N/A     ; -18.132             ;
-;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
-;  tick_50000:TICK0|CLK_OUT            ; -161.413 ; -0.052 ; N/A      ; N/A     ; -38.762             ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+-------------------------------------------------------------+
-; Input Transition Times                                      ;
-+----------+--------------+-----------------+-----------------+
-; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+----------+--------------+-----------------+-----------------+
-; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-+----------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Setup Transfers                                                                                                       ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50                            ; CLOCK_50                            ; 416      ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 1042     ; 0        ; 0        ; 0        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Hold Transfers                                                                                                        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50                            ; CLOCK_50                            ; 416      ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 1042     ; 0        ; 0        ; 0        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary                    ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 2     ; 2    ;
-; Unconstrained Input Port Paths  ; 20    ; 20   ;
-; Unconstrained Output Ports      ; 45    ; 45   ;
-; Unconstrained Output Port Paths ; 500   ; 500  ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Clock Status Summary                                                                           ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; Target                              ; Clock                               ; Type ; Status      ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; CLOCK_50                            ; CLOCK_50                            ; Base ; Constrained ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; Base ; Constrained ;
-+-------------------------------------+-------------------------------------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime TimeQuest Timing Analyzer
-    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-    Info: Processing started: Wed Dec 07 12:08:21 2016
-Info: Command: quartus_sta ex9 -c ex9
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
-    Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
-    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
-    Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1100mV 85C Model
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.462
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -3.462            -161.413 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -2.047             -40.775 CLOCK_50 
-    Info (332119):    -1.675              -1.675 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is 0.179
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.179               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.385               0.000 CLOCK_50 
-    Info (332119):     0.629               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.637
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.637             -18.132 CLOCK_50 
-    Info (332119):    -0.394             -38.762 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.459               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info: Analyzing Slow 1100mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.416
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -3.416            -157.230 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -2.323             -41.799 CLOCK_50 
-    Info (332119):    -1.568              -1.568 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is 0.193
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.193               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.405               0.000 CLOCK_50 
-    Info (332119):     0.501               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.689
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.689             -16.816 CLOCK_50 
-    Info (332119):    -0.394             -38.286 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.412               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info: Analyzing Fast 1100mV 85C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.794
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -1.794             -79.872 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -0.918             -13.912 CLOCK_50 
-    Info (332119):    -0.572              -0.572 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is -0.020
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.020              -0.037 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.185               0.000 CLOCK_50 
-    Info (332119):     0.202               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.740
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.740             -12.957 CLOCK_50 
-    Info (332119):    -0.012              -0.190 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.478               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info: Analyzing Fast 1100mV 0C Model
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.581
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -1.581             -69.264 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -0.868             -11.639 CLOCK_50 
-    Info (332119):    -0.462              -0.462 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is -0.021
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.021              -0.052 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.122               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-    Info (332119):     0.177               0.000 CLOCK_50 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.789
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.789             -15.486 CLOCK_50 
-    Info (332119):     0.024               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.468               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
-    Info: Peak virtual memory: 1213 megabytes
-    Info: Processing ended: Wed Dec 07 12:08:30 2016
-    Info: Elapsed time: 00:00:09
-    Info: Total CPU time (on all processors): 00:00:06
-
-
+TimeQuest Timing Analyzer report for ex9
+Wed Dec 07 12:08:30 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1100mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1100mV 85C Model Setup Summary
+  8. Slow 1100mV 85C Model Hold Summary
+  9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Setup Transfers
+ 40. Hold Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths Summary
+ 44. Clock Status Summary
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Unconstrained Input Ports
+ 48. Unconstrained Output Ports
+ 49. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                               ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer       ; TimeQuest                                               ;
+; Revision Name         ; ex9                                                     ;
+; Device Family         ; Cyclone V                                               ;
+; Device Name           ; 5CSEMA5F31C6                                            ;
+; Timing Models         ; Final                                                   ;
+; Delay Model           ; Combined                                                ;
+; Rise/Fall Delays      ; Enabled                                                 ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.10        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   3.3%      ;
+;     Processor 3            ;   3.3%      ;
+;     Processor 4            ;   3.2%      ;
++----------------------------+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                                   ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+; Clock Name                          ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                 ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+; CLOCK_50                            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                            ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
+; tick_50000:TICK0|CLK_OUT            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_50000:TICK0|CLK_OUT }            ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary                             ;
++------------+-----------------+--------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
++------------+-----------------+--------------------------+------+
+; 224.11 MHz ; 224.11 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
+; 328.19 MHz ; 328.19 MHz      ; CLOCK_50                 ;      ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 85C Model Setup Summary                          ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -3.462 ; -161.413      ;
+; CLOCK_50                            ; -2.047 ; -40.775       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675 ; -1.675        ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Slow 1100mV 85C Model Hold Summary                          ;
++-------------------------------------+-------+---------------+
+; Clock                               ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; 0.179 ; 0.000         ;
+; CLOCK_50                            ; 0.385 ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.629 ; 0.000         ;
++-------------------------------------+-------+---------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary            ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.637 ; -18.132       ;
+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -38.762       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.459  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary                              ;
++------------+-----------------+--------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
++------------+-----------------+--------------------------+------+
+; 226.45 MHz ; 226.45 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
+; 300.93 MHz ; 300.93 MHz      ; CLOCK_50                 ;      ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 0C Model Setup Summary                           ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -3.416 ; -157.230      ;
+; CLOCK_50                            ; -2.323 ; -41.799       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.568 ; -1.568        ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Slow 1100mV 0C Model Hold Summary                           ;
++-------------------------------------+-------+---------------+
+; Clock                               ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; 0.193 ; 0.000         ;
+; CLOCK_50                            ; 0.405 ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.501 ; 0.000         ;
++-------------------------------------+-------+---------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary             ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.689 ; -16.816       ;
+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -38.286       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.412  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Setup Summary                          ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -1.794 ; -79.872       ;
+; CLOCK_50                            ; -0.918 ; -13.912       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.572 ; -0.572        ;
++-------------------------------------+--------+---------------+
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Hold Summary                           ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -0.020 ; -0.037        ;
+; CLOCK_50                            ; 0.185  ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.202  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary            ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.740 ; -12.957       ;
+; tick_50000:TICK0|CLK_OUT            ; -0.012 ; -0.190        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.478  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Setup Summary                           ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -1.581 ; -69.264       ;
+; CLOCK_50                            ; -0.868 ; -11.639       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.462 ; -0.462        ;
++-------------------------------------+--------+---------------+
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Hold Summary                            ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -0.021 ; -0.052        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.122  ; 0.000         ;
+; CLOCK_50                            ; 0.177  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary             ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.789 ; -15.486       ;
+; tick_50000:TICK0|CLK_OUT            ; 0.024  ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.468  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-----------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                                 ;
++--------------------------------------+----------+--------+----------+---------+---------------------+
+; Clock                                ; Setup    ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
++--------------------------------------+----------+--------+----------+---------+---------------------+
+; Worst-case Slack                     ; -3.462   ; -0.021 ; N/A      ; N/A     ; -0.789              ;
+;  CLOCK_50                            ; -2.323   ; 0.177  ; N/A      ; N/A     ; -0.789              ;
+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675   ; 0.122  ; N/A      ; N/A     ; 0.412               ;
+;  tick_50000:TICK0|CLK_OUT            ; -3.462   ; -0.021 ; N/A      ; N/A     ; -0.394              ;
+; Design-wide TNS                      ; -203.863 ; -0.052 ; 0.0      ; 0.0     ; -56.894             ;
+;  CLOCK_50                            ; -41.799  ; 0.000  ; N/A      ; N/A     ; -18.132             ;
+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
+;  tick_50000:TICK0|CLK_OUT            ; -161.413 ; -0.052 ; N/A      ; N/A     ; -38.762             ;
++--------------------------------------+----------+--------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times                                      ;
++----------+--------------+-----------------+-----------------+
+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                                       ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                            ; CLOCK_50                            ; 416      ; 0        ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 1042     ; 0        ; 0        ; 0        ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                                        ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                            ; CLOCK_50                            ; 416      ; 0        ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 1042     ; 0        ; 0        ; 0        ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 2     ; 2    ;
+; Unconstrained Input Port Paths  ; 20    ; 20   ;
+; Unconstrained Output Ports      ; 45    ; 45   ;
+; Unconstrained Output Port Paths ; 500   ; 500  ;
++---------------------------------+-------+------+
+
+
++------------------------------------------------------------------------------------------------+
+; Clock Status Summary                                                                           ;
++-------------------------------------+-------------------------------------+------+-------------+
+; Target                              ; Clock                               ; Type ; Status      ;
++-------------------------------------+-------------------------------------+------+-------------+
+; CLOCK_50                            ; CLOCK_50                            ; Base ; Constrained ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; Base ; Constrained ;
++-------------------------------------+-------------------------------------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Wed Dec 07 12:08:21 2016
+Info: Command: quartus_sta ex9 -c ex9
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
+    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
+    Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.462
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.462            -161.413 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -2.047             -40.775 CLOCK_50 
+    Info (332119):    -1.675              -1.675 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is 0.179
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.179               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.385               0.000 CLOCK_50 
+    Info (332119):     0.629               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.637
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.637             -18.132 CLOCK_50 
+    Info (332119):    -0.394             -38.762 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.459               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.416
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.416            -157.230 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -2.323             -41.799 CLOCK_50 
+    Info (332119):    -1.568              -1.568 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is 0.193
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.193               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.405               0.000 CLOCK_50 
+    Info (332119):     0.501               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.689
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.689             -16.816 CLOCK_50 
+    Info (332119):    -0.394             -38.286 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.412               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.794
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.794             -79.872 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -0.918             -13.912 CLOCK_50 
+    Info (332119):    -0.572              -0.572 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is -0.020
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.020              -0.037 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.185               0.000 CLOCK_50 
+    Info (332119):     0.202               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.740
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.740             -12.957 CLOCK_50 
+    Info (332119):    -0.012              -0.190 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.478               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info: Analyzing Fast 1100mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.581
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.581             -69.264 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -0.868             -11.639 CLOCK_50 
+    Info (332119):    -0.462              -0.462 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is -0.021
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.021              -0.052 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.122               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):     0.177               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.789
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.789             -15.486 CLOCK_50 
+    Info (332119):     0.024               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.468               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
+    Info: Peak virtual memory: 1213 megabytes
+    Info: Processing ended: Wed Dec 07 12:08:30 2016
+    Info: Elapsed time: 00:00:09
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_2/ex9/output_files/ex9.sta.summary b/part_2/ex9/output_files/ex9.sta.summary
index 0b9aef6..87e925d 100644
--- a/part_2/ex9/output_files/ex9.sta.summary
+++ b/part_2/ex9/output_files/ex9.sta.summary
@@ -1,149 +1,149 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type  : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.462
-TNS   : -161.413
-
-Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -2.047
-TNS   : -40.775
-
-Type  : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.675
-TNS   : -1.675
-
-Type  : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.179
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.385
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.629
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.637
-TNS   : -18.132
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS   : -38.762
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.459
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.416
-TNS   : -157.230
-
-Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -2.323
-TNS   : -41.799
-
-Type  : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.568
-TNS   : -1.568
-
-Type  : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.193
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.405
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.501
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.689
-TNS   : -16.816
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS   : -38.286
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.412
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.794
-TNS   : -79.872
-
-Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -0.918
-TNS   : -13.912
-
-Type  : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.572
-TNS   : -0.572
-
-Type  : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.020
-TNS   : -0.037
-
-Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.185
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.202
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.740
-TNS   : -12.957
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.012
-TNS   : -0.190
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.478
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.581
-TNS   : -69.264
-
-Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -0.868
-TNS   : -11.639
-
-Type  : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.462
-TNS   : -0.462
-
-Type  : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.021
-TNS   : -0.052
-
-Type  : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.122
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.177
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.789
-TNS   : -15.486
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.024
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.468
-TNS   : 0.000
-
-------------------------------------------------------------
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -3.462
+TNS   : -161.413
+
+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -2.047
+TNS   : -40.775
+
+Type  : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -1.675
+TNS   : -1.675
+
+Type  : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.179
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.385
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.629
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.637
+TNS   : -18.132
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.394
+TNS   : -38.762
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.459
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -3.416
+TNS   : -157.230
+
+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -2.323
+TNS   : -41.799
+
+Type  : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -1.568
+TNS   : -1.568
+
+Type  : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.193
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.405
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.501
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.689
+TNS   : -16.816
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.394
+TNS   : -38.286
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.412
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -1.794
+TNS   : -79.872
+
+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -0.918
+TNS   : -13.912
+
+Type  : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -0.572
+TNS   : -0.572
+
+Type  : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.020
+TNS   : -0.037
+
+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.185
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.202
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.740
+TNS   : -12.957
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.012
+TNS   : -0.190
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.478
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -1.581
+TNS   : -69.264
+
+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -0.868
+TNS   : -11.639
+
+Type  : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -0.462
+TNS   : -0.462
+
+Type  : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.021
+TNS   : -0.052
+
+Type  : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.122
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.177
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.789
+TNS   : -15.486
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.024
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.468
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/part_2/ex9/verilog_files/LFSR.v b/part_2/ex9/verilog_files/LFSR.v
index 6ef9858..46140b2 100644
--- a/part_2/ex9/verilog_files/LFSR.v
+++ b/part_2/ex9/verilog_files/LFSR.v
@@ -1,18 +1,18 @@
-module LFSR(CLK, en, COUNT);
-
-	input CLK;
-	input en;
-	
-	output [7:1] COUNT;
-	
-	reg [7:1] COUNT;
-	initial COUNT = 7'd1;
-		
-	always @ (posedge CLK)
-		if(en == 1'b1)
-			COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};
-		else
-			COUNT <= COUNT;
-		
-endmodule
+module LFSR(CLK, en, COUNT);
+
+	input CLK;
+	input en;
+	
+	output [7:1] COUNT;
+	
+	reg [7:1] COUNT;
+	initial COUNT = 7'd1;
+		
+	always @ (posedge CLK)
+		if(en == 1'b1)
+			COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};
+		else
+			COUNT <= COUNT;
+		
+endmodule
 	
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/LFSR.v.bak b/part_2/ex9/verilog_files/LFSR.v.bak
index f9c38a5..89ec82a 100644
--- a/part_2/ex9/verilog_files/LFSR.v.bak
+++ b/part_2/ex9/verilog_files/LFSR.v.bak
@@ -1,11 +1,11 @@
-module LFSR(CLK, COUNT);
-	input CLK;
-	output[7:1] COUNT;
-	reg[7:1] COUNT;
-	initial COUNT = 7'd1;
-		
-	always @ (posedge CLK)
-		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};
-		
-endmodule
+module LFSR(CLK, COUNT);
+	input CLK;
+	output[7:1] COUNT;
+	reg[7:1] COUNT;
+	initial COUNT = 7'd1;
+		
+	always @ (posedge CLK)
+		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};
+		
+endmodule
 	
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/add3_ge5.v b/part_2/ex9/verilog_files/add3_ge5.v
index 81d53bf..a3cd6a9 100644
--- a/part_2/ex9/verilog_files/add3_ge5.v
+++ b/part_2/ex9/verilog_files/add3_ge5.v
@@ -1,34 +1,34 @@
-//------------------------------
-// Module name: add3_ge5
-// Function: Add 3 to input if it is 5 or above
-// Creator:  Peter Cheung
-// Version:  1.0
-// Date:     21 Jan 2014
-//------------------------------
-
-module add3_ge5(iW,oA);
-
- input [3:0] iW; 
- output reg [3:0] oA;  
- 
-	always @ (iW)
-		case (iW) 
-		//****** input <5, pass to output unchanged ******
-			4'b0000: oA <= 4'b0000; 
-			4'b0001: oA <= 4'b0001; 
-			4'b0010: oA <= 4'b0010; 
-			4'b0011: oA <= 4'b0011; 
-			4'b0100: oA <= 4'b0100;
-			
-		//****** input >=5, output = input + 3	******	
-			4'b0101: oA <= 4'b1000; 
-			4'b0110: oA <= 4'b1001; 
-			4'b0111: oA <= 4'b1010; 
-			4'b1000: oA <= 4'b1011; 
-			4'b1001: oA <= 4'b1100;
-			4'b1010: oA <= 4'b1101;	
-			4'b1011: oA <= 4'b1110;	
-			4'b1100: oA <= 4'b1111;	
-			default: oA <= 4'b0000; // oA cannot be 13 or larger, else overflow
-		endcase 
-endmodule
+//------------------------------
+// Module name: add3_ge5
+// Function: Add 3 to input if it is 5 or above
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     21 Jan 2014
+//------------------------------
+
+module add3_ge5(iW,oA);
+
+ input [3:0] iW; 
+ output reg [3:0] oA;  
+ 
+	always @ (iW)
+		case (iW) 
+		//****** input <5, pass to output unchanged ******
+			4'b0000: oA <= 4'b0000; 
+			4'b0001: oA <= 4'b0001; 
+			4'b0010: oA <= 4'b0010; 
+			4'b0011: oA <= 4'b0011; 
+			4'b0100: oA <= 4'b0100;
+			
+		//****** input >=5, output = input + 3	******	
+			4'b0101: oA <= 4'b1000; 
+			4'b0110: oA <= 4'b1001; 
+			4'b0111: oA <= 4'b1010; 
+			4'b1000: oA <= 4'b1011; 
+			4'b1001: oA <= 4'b1100;
+			4'b1010: oA <= 4'b1101;	
+			4'b1011: oA <= 4'b1110;	
+			4'b1100: oA <= 4'b1111;	
+			default: oA <= 4'b0000; // oA cannot be 13 or larger, else overflow
+		endcase 
+endmodule
diff --git a/part_2/ex9/verilog_files/bin2bcd_16.v b/part_2/ex9/verilog_files/bin2bcd_16.v
index 38772ac..b25d0bd 100644
--- a/part_2/ex9/verilog_files/bin2bcd_16.v
+++ b/part_2/ex9/verilog_files/bin2bcd_16.v
@@ -1,109 +1,109 @@
-//------------------------------
-// Module name: bin2bcd_16
-// Function: Converts a 16-bit binary number to 5 digits BCD
-//            .... it uses a shift-and-add3 algorithm
-// Creator:  Peter Cheung
-// Version:  2.0  (Correct mistake - problem with numbers 0x5000 or larger)
-// Date:     24 Nov 2016
-//------------------------------
-//   For more explanation of how this work, see 
-//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
-
-module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
-
-	input [15:0]	B;		// binary input number
-	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD
-	
-	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
-	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;
-	wire [3:0]	w26,w27,w28,w29,w30,w31,w32,w33,w34,w35;
-	wire [3:0]	a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;
-	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;
-	wire [3:0]	a26,a27,a28,a29,a30,a31,a32,a33,a34,a35;
-
-	// Instantiate a tree of add3-if-greater than or equal to 5 cells
-	//  ... input is w_n, and output is a_n
-	add3_ge5 A1 (w1,a1);
-	add3_ge5 A2 (w2,a2);
-	add3_ge5 A3 (w3,a3);
-	add3_ge5 A4 (w4,a4);
-	add3_ge5 A5 (w5,a5);
-	add3_ge5 A6 (w6,a6);
-	add3_ge5 A7 (w7,a7);
-	add3_ge5 A8 (w8,a8);
-	add3_ge5 A9 (w9,a9);
-	add3_ge5 A10 (w10,a10);
-	add3_ge5 A11 (w11,a11);
-	add3_ge5 A12 (w12,a12);
-	add3_ge5 A13 (w13,a13);
-	add3_ge5 A14 (w14,a14);
-	add3_ge5 A15 (w15,a15);
-	add3_ge5 A16 (w16,a16);
-	add3_ge5 A17 (w17,a17);
-	add3_ge5 A18 (w18,a18);
-	add3_ge5 A19 (w19,a19);
-	add3_ge5 A20 (w20,a20);
-	add3_ge5 A21 (w21,a21);
-	add3_ge5 A22 (w22,a22);
-	add3_ge5 A23 (w23,a23);
-	add3_ge5 A24 (w24,a24);
-	add3_ge5 A25 (w25,a25);
-	add3_ge5 A26 (w26,a26);
-	add3_ge5 A27 (w27,a27);
-	add3_ge5 A28 (w28,a28);
-	add3_ge5 A29 (w29,a29);
-	add3_ge5 A30 (w30,a30);
-	add3_ge5 A31 (w31,a31);
-	add3_ge5 A32 (w32,a32);
-	add3_ge5 A33 (w33,a33);
-	add3_ge5 A34 (w34,a34);
-	add3_ge5 A35 (w35,a35);
-		
-	// wire the tree of add3 modules together
-	assign  w1 = {1'b0,B[15:13]};		// w_n is the input port to module a_n
-	assign  w2 = {a1[2:0], B[12]};		
-	assign  w3 = {a2[2:0], B[11]};		
-	assign  w4 = {1'b0,a1[3],a2[3],a3[3]};
-	assign  w5 = {a3[2:0], B[10]};
-	assign  w6 = {a4[2:0], a5[3]};
-	assign  w7 = {a5[2:0], B[9]};
-	assign  w8 = {a6[2:0], a7[3]};
-	assign  w9 = {a7[2:0], B[8]};
-	assign  w10 = {1'b0, a4[3], a6[3], a8[3]};
-	assign  w11 = {a8[2:0], a9[3]};
-	assign  w12 = {a9[2:0], B[7]};
-	assign  w13 = {a10[2:0], a11[3]};
-	assign  w14 = {a11[2:0], a12[3]};
-	assign  w15 = {a12[2:0], B[6]};
-	assign  w16 = {a13[2:0], a14[3]};
-	assign  w17 = {a14[2:0], a15[3]};
-	assign  w18 = {a15[2:0], B[5]};
-	assign  w19 = {1'b0, a10[3], a13[3], a16[3]};
-	assign  w20 = {a16[2:0], a17[3]};
-	assign  w21 = {a17[2:0], a18[3]};
-	assign  w22 = {a18[2:0], B[4]};
-	assign  w23 = {a19[2:0], a20[3]};
-	assign  w24 = {a20[2:0], a21[3]};
-	assign  w25 = {a21[2:0], a22[3]};
-	assign  w26 = {a22[2:0], B[3]};
-	assign  w27 = {a23[2:0], a24[3]};
-	assign  w28 = {a24[2:0], a25[3]};
-	assign  w29 = {a25[2:0], a26[3]};
-	assign  w30 = {a26[2:0], B[2]};
-	assign  w31 = {1'b0,a19[3], a23[3], a27[3]};
-	assign  w32 = {a27[2:0], a28[3]};
-	assign  w33 = {a28[2:0], a29[3]};
-	assign  w34 = {a29[2:0], a30[3]};
-	assign  w35 = {a30[2:0], B[1]};
-	
-	// connect up to four BCD digit outputs	
-	assign BCD_0 = {a35[2:0],B[0]};
-	assign BCD_1 = {a34[2:0],a35[3]};
-	assign BCD_2 = {a33[2:0],a34[3]};
-	assign BCD_3 = {a32[2:0],a33[3]};
-	assign BCD_4 = {a31[2:0],a32[3]};	
-endmodule
-
-	
-	
-
+//------------------------------
+// Module name: bin2bcd_16
+// Function: Converts a 16-bit binary number to 5 digits BCD
+//            .... it uses a shift-and-add3 algorithm
+// Creator:  Peter Cheung
+// Version:  2.0  (Correct mistake - problem with numbers 0x5000 or larger)
+// Date:     24 Nov 2016
+//------------------------------
+//   For more explanation of how this work, see 
+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
+
+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+	input [15:0]	B;		// binary input number
+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD
+	
+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;
+	wire [3:0]	w26,w27,w28,w29,w30,w31,w32,w33,w34,w35;
+	wire [3:0]	a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;
+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;
+	wire [3:0]	a26,a27,a28,a29,a30,a31,a32,a33,a34,a35;
+
+	// Instantiate a tree of add3-if-greater than or equal to 5 cells
+	//  ... input is w_n, and output is a_n
+	add3_ge5 A1 (w1,a1);
+	add3_ge5 A2 (w2,a2);
+	add3_ge5 A3 (w3,a3);
+	add3_ge5 A4 (w4,a4);
+	add3_ge5 A5 (w5,a5);
+	add3_ge5 A6 (w6,a6);
+	add3_ge5 A7 (w7,a7);
+	add3_ge5 A8 (w8,a8);
+	add3_ge5 A9 (w9,a9);
+	add3_ge5 A10 (w10,a10);
+	add3_ge5 A11 (w11,a11);
+	add3_ge5 A12 (w12,a12);
+	add3_ge5 A13 (w13,a13);
+	add3_ge5 A14 (w14,a14);
+	add3_ge5 A15 (w15,a15);
+	add3_ge5 A16 (w16,a16);
+	add3_ge5 A17 (w17,a17);
+	add3_ge5 A18 (w18,a18);
+	add3_ge5 A19 (w19,a19);
+	add3_ge5 A20 (w20,a20);
+	add3_ge5 A21 (w21,a21);
+	add3_ge5 A22 (w22,a22);
+	add3_ge5 A23 (w23,a23);
+	add3_ge5 A24 (w24,a24);
+	add3_ge5 A25 (w25,a25);
+	add3_ge5 A26 (w26,a26);
+	add3_ge5 A27 (w27,a27);
+	add3_ge5 A28 (w28,a28);
+	add3_ge5 A29 (w29,a29);
+	add3_ge5 A30 (w30,a30);
+	add3_ge5 A31 (w31,a31);
+	add3_ge5 A32 (w32,a32);
+	add3_ge5 A33 (w33,a33);
+	add3_ge5 A34 (w34,a34);
+	add3_ge5 A35 (w35,a35);
+		
+	// wire the tree of add3 modules together
+	assign  w1 = {1'b0,B[15:13]};		// w_n is the input port to module a_n
+	assign  w2 = {a1[2:0], B[12]};		
+	assign  w3 = {a2[2:0], B[11]};		
+	assign  w4 = {1'b0,a1[3],a2[3],a3[3]};
+	assign  w5 = {a3[2:0], B[10]};
+	assign  w6 = {a4[2:0], a5[3]};
+	assign  w7 = {a5[2:0], B[9]};
+	assign  w8 = {a6[2:0], a7[3]};
+	assign  w9 = {a7[2:0], B[8]};
+	assign  w10 = {1'b0, a4[3], a6[3], a8[3]};
+	assign  w11 = {a8[2:0], a9[3]};
+	assign  w12 = {a9[2:0], B[7]};
+	assign  w13 = {a10[2:0], a11[3]};
+	assign  w14 = {a11[2:0], a12[3]};
+	assign  w15 = {a12[2:0], B[6]};
+	assign  w16 = {a13[2:0], a14[3]};
+	assign  w17 = {a14[2:0], a15[3]};
+	assign  w18 = {a15[2:0], B[5]};
+	assign  w19 = {1'b0, a10[3], a13[3], a16[3]};
+	assign  w20 = {a16[2:0], a17[3]};
+	assign  w21 = {a17[2:0], a18[3]};
+	assign  w22 = {a18[2:0], B[4]};
+	assign  w23 = {a19[2:0], a20[3]};
+	assign  w24 = {a20[2:0], a21[3]};
+	assign  w25 = {a21[2:0], a22[3]};
+	assign  w26 = {a22[2:0], B[3]};
+	assign  w27 = {a23[2:0], a24[3]};
+	assign  w28 = {a24[2:0], a25[3]};
+	assign  w29 = {a25[2:0], a26[3]};
+	assign  w30 = {a26[2:0], B[2]};
+	assign  w31 = {1'b0,a19[3], a23[3], a27[3]};
+	assign  w32 = {a27[2:0], a28[3]};
+	assign  w33 = {a28[2:0], a29[3]};
+	assign  w34 = {a29[2:0], a30[3]};
+	assign  w35 = {a30[2:0], B[1]};
+	
+	// connect up to four BCD digit outputs	
+	assign BCD_0 = {a35[2:0],B[0]};
+	assign BCD_1 = {a34[2:0],a35[3]};
+	assign BCD_2 = {a33[2:0],a34[3]};
+	assign BCD_3 = {a32[2:0],a33[3]};
+	assign BCD_4 = {a31[2:0],a32[3]};	
+endmodule
+
+	
+	
+
diff --git a/part_2/ex9/verilog_files/counter_16.v b/part_2/ex9/verilog_files/counter_16.v
index 7d507c8..9c194bb 100644
--- a/part_2/ex9/verilog_files/counter_16.v
+++ b/part_2/ex9/verilog_files/counter_16.v
@@ -1,31 +1,31 @@
-module counter_16(clock, start, stop, count);
-
-	parameter BIT_SZ = 16;
-	input clock, start, stop;
-	output [BIT_SZ-1:0] count;
-	
-	reg [BIT_SZ-1:0] count;
-	
-	reg state;
-	
-	parameter COUNTING = 1'b1, IDLE = 1'b0;
-	
-	initial count = 0;
-	initial state = IDLE;
-	
-	always @ (posedge clock)
-		case(state)
-			IDLE:
-				if(start == 1'b1)
-					begin
-						count <= 0;
-						state <= COUNTING;
-					end
-			COUNTING:
-				if(stop == 1'b1)
-					state <= IDLE;
-				else
-					count <= count + 1'b1;
-		endcase
-	
+module counter_16(clock, start, stop, count);
+
+	parameter BIT_SZ = 16;
+	input clock, start, stop;
+	output [BIT_SZ-1:0] count;
+	
+	reg [BIT_SZ-1:0] count;
+	
+	reg state;
+	
+	parameter COUNTING = 1'b1, IDLE = 1'b0;
+	
+	initial count = 0;
+	initial state = IDLE;
+	
+	always @ (posedge clock)
+		case(state)
+			IDLE:
+				if(start == 1'b1)
+					begin
+						count <= 0;
+						state <= COUNTING;
+					end
+			COUNTING:
+				if(stop == 1'b1)
+					state <= IDLE;
+				else
+					count <= count + 1'b1;
+		endcase
+	
 endmodule
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/counter_16.v.bak b/part_2/ex9/verilog_files/counter_16.v.bak
index e21882e..c0ec549 100644
--- a/part_2/ex9/verilog_files/counter_16.v.bak
+++ b/part_2/ex9/verilog_files/counter_16.v.bak
@@ -1,21 +1,21 @@
-`timescale 1ns / 100ps
-
-module counter_16(clock,enable,reset,count);
-
-	parameter BIT_SZ = 16;
-	input clock, enable, reset;
-	output [BIT_SZ-1:0] count;
-	
-	reg [BIT_SZ-1:0] count;
-	
-	initial count = 0;
-	
-	always @ (posedge clock)
-		begin
-			if(enable == 1'b1)
-				count <= count + 1'b1;
-			if(reset == 1'b1)
-				count <= 16'b0;
-		end
-			
+`timescale 1ns / 100ps
+
+module counter_16(clock,enable,reset,count);
+
+	parameter BIT_SZ = 16;
+	input clock, enable, reset;
+	output [BIT_SZ-1:0] count;
+	
+	reg [BIT_SZ-1:0] count;
+	
+	initial count = 0;
+	
+	always @ (posedge clock)
+		begin
+			if(enable == 1'b1)
+				count <= count + 1'b1;
+			if(reset == 1'b1)
+				count <= 16'b0;
+		end
+			
 endmodule
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/delay.v b/part_2/ex9/verilog_files/delay.v
index b94c715..63455d7 100644
--- a/part_2/ex9/verilog_files/delay.v
+++ b/part_2/ex9/verilog_files/delay.v
@@ -1,58 +1,58 @@
-module delay(clk, N, trigger, time_out);
-
-	parameter BIT_SZ = 14;
-
-	input clk, trigger;
-	input [BIT_SZ-1:0] N;
-	output time_out;
-
-	reg[BIT_SZ-1:0] count;
-	reg time_out;
-
-	reg [1:0] state;
-
-	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;
-
-	initial begin
-		state = IDLE;
-	end
-	
-	always @ (posedge clk)
-		case(state)
-			IDLE: if(trigger == 1'b1)
-				begin
-					count <= N*128;
-					state <= COUNTING;
-				end
-			COUNTING: 
-				begin
-					if(count == 1'b0)
-						begin
-							state <= TIME_OUT;
-						end
-					else 
-						count <= count - 1'b1;
-				end
-			TIME_OUT: 
-				begin
-					if(trigger == 1'b0)
-						state <= IDLE;
-					else
-						state <= WAIT_LOW;
-				end
-			WAIT_LOW: 
-				if(trigger == 1'b0)
-					state <= IDLE;
-			default: ;
-		endcase
-		
-	always @ (*)
-		case(state)
-			IDLE: 		time_out = 1'b0;
-			COUNTING:	time_out = 1'b0;
-			TIME_OUT: 	time_out = 1'b1;
-			WAIT_LOW: 	time_out = 1'b0;
-			default: ;
-		endcase
-
+module delay(clk, N, trigger, time_out);
+
+	parameter BIT_SZ = 14;
+
+	input clk, trigger;
+	input [BIT_SZ-1:0] N;
+	output time_out;
+
+	reg[BIT_SZ-1:0] count;
+	reg time_out;
+
+	reg [1:0] state;
+
+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;
+
+	initial begin
+		state = IDLE;
+	end
+	
+	always @ (posedge clk)
+		case(state)
+			IDLE: if(trigger == 1'b1)
+				begin
+					count <= N*128;
+					state <= COUNTING;
+				end
+			COUNTING: 
+				begin
+					if(count == 1'b0)
+						begin
+							state <= TIME_OUT;
+						end
+					else 
+						count <= count - 1'b1;
+				end
+			TIME_OUT: 
+				begin
+					if(trigger == 1'b0)
+						state <= IDLE;
+					else
+						state <= WAIT_LOW;
+				end
+			WAIT_LOW: 
+				if(trigger == 1'b0)
+					state <= IDLE;
+			default: ;
+		endcase
+		
+	always @ (*)
+		case(state)
+			IDLE: 		time_out = 1'b0;
+			COUNTING:	time_out = 1'b0;
+			TIME_OUT: 	time_out = 1'b1;
+			WAIT_LOW: 	time_out = 1'b0;
+			default: ;
+		endcase
+
 endmodule
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/delay.v.bak b/part_2/ex9/verilog_files/delay.v.bak
index fb1cfab..7b79342 100644
--- a/part_2/ex9/verilog_files/delay.v.bak
+++ b/part_2/ex9/verilog_files/delay.v.bak
@@ -1,47 +1,47 @@
-module delay(clk, N, trigger, time_out);
-
-	parameter BIT_SZ = 7
-
-	input clk, trigger;
-	input [BIT_SZ-1:0] N;
-	output time_out;
-
-	reg[BIT_SZ-1:0] count;
-	reg time_out;
-
-	reg [1:0] state;
-
-	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;
-
-	initial begin
-		state = IDLE;
-		count = N-1'b1;
-	end
-	
-	always @ (posedge clk)
-		case(state)
-			IDLE: if(trigger == 1'b1)
-					state <= COUNTING;
-			COUNTING: if(count == 1'b0) begin
-					count <= n - 1'b1;
-					state <= TIME_OUT;
-				end
-			TIME_OUT: if(trigger == 1'b0)
-					state <= IDLE;
-				else
-					state <= WAIT_LOW;
-			WAIT_LOW: if(trigger == 1'b0)
-					state <= IDLE;
-			defualt: ;
-		endcase
-		
-	always @ (*)
-		case(state)
-			IDLE: time_out = 1'b0;
-			COUNTING: time_out = 1'b0;
-			TIME_OUT: time_out = 1'b1;
-			WAIT_LOW: time_out = 1'b0;
-			default: ;
-		endcase
-
+module delay(clk, N, trigger, time_out);
+
+	parameter BIT_SZ = 7
+
+	input clk, trigger;
+	input [BIT_SZ-1:0] N;
+	output time_out;
+
+	reg[BIT_SZ-1:0] count;
+	reg time_out;
+
+	reg [1:0] state;
+
+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;
+
+	initial begin
+		state = IDLE;
+		count = N-1'b1;
+	end
+	
+	always @ (posedge clk)
+		case(state)
+			IDLE: if(trigger == 1'b1)
+					state <= COUNTING;
+			COUNTING: if(count == 1'b0) begin
+					count <= n - 1'b1;
+					state <= TIME_OUT;
+				end
+			TIME_OUT: if(trigger == 1'b0)
+					state <= IDLE;
+				else
+					state <= WAIT_LOW;
+			WAIT_LOW: if(trigger == 1'b0)
+					state <= IDLE;
+			defualt: ;
+		endcase
+		
+	always @ (*)
+		case(state)
+			IDLE: time_out = 1'b0;
+			COUNTING: time_out = 1'b0;
+			TIME_OUT: time_out = 1'b1;
+			WAIT_LOW: time_out = 1'b0;
+			default: ;
+		endcase
+
 endmodule
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/ex8.v b/part_2/ex9/verilog_files/ex8.v
index 63427f8..6ca51d6 100644
--- a/part_2/ex9/verilog_files/ex8.v
+++ b/part_2/ex9/verilog_files/ex8.v
@@ -1,23 +1,23 @@
-module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
-	
-	input CLOCK_50;
-	input [3:0] KEY;
-	output [9:0] LEDR;
-	output [6:0] HEX0, HEX1, HEX2;
-	
-	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
-	wire [6:0] N;
-	wire [6:0] bcd_to_hex;
-	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
-	
-	tick_50000 TICK0(CLOCK_50, tick_ms);
-	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
-	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
-	LFSR LFSR0(tick_ms, en_lfsr, N);
-	delay DEL0(tick_ms, N, start_delay, time_out);
-	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
-	hex_to_7seg SEG0(HEX0, BCD_0);
-	hex_to_7seg SEG1(HEX1, BCD_1);
-	hex_to_7seg SEG2(HEX2, BCD_2);
-	
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
+	
+	input CLOCK_50;
+	input [3:0] KEY;
+	output [9:0] LEDR;
+	output [6:0] HEX0, HEX1, HEX2;
+	
+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
+	wire [6:0] N;
+	wire [6:0] bcd_to_hex;
+	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
+	
+	tick_50000 TICK0(CLOCK_50, tick_ms);
+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
+	LFSR LFSR0(tick_ms, en_lfsr, N);
+	delay DEL0(tick_ms, N, start_delay, time_out);
+	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+	hex_to_7seg SEG0(HEX0, BCD_0);
+	hex_to_7seg SEG1(HEX1, BCD_1);
+	hex_to_7seg SEG2(HEX2, BCD_2);
+	
 endmodule
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/ex9.v b/part_2/ex9/verilog_files/ex9.v
index 7f6a0f4..15446c2 100644
--- a/part_2/ex9/verilog_files/ex9.v
+++ b/part_2/ex9/verilog_files/ex9.v
@@ -1,33 +1,33 @@
-module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);
-	
-	input CLOCK_50;
-	input [3:0] KEY;
-	output [9:0] LEDR;
-	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
-	
-	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
-	wire [6:0] N;
-	wire [6:0] bcd_to_hex;
-	wire [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
-	wire [15:0] count_out;
-	
-	tick_50000 TICK0(CLOCK_50, tick_ms);
-	
-	formula_fsm FSM(tick_ms, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
-	
-	LFSR LFSR0(tick_ms, en_lfsr, N);
-	
-	delay DEL0(tick_ms, N, start_delay, time_out);
-	
-	counter_16 COUNT0(tick_ms, time_out, ~KEY[0], count_out);
-	
-	bin2bcd_16 BCD(count_out, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
-	
-	hex_to_7seg SEG0(HEX0, BCD_0);
-	hex_to_7seg SEG1(HEX1, BCD_1);
-	hex_to_7seg SEG2(HEX2, BCD_2);
-	hex_to_7seg SEG3(HEX3, BCD_3);
-	hex_to_7seg SEG4(HEX4, BCD_4);
-	hex_to_7seg SEG5(HEX5, 4'b0);
-	
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);
+	
+	input CLOCK_50;
+	input [3:0] KEY;
+	output [9:0] LEDR;
+	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
+	
+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
+	wire [6:0] N;
+	wire [6:0] bcd_to_hex;
+	wire [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
+	wire [15:0] count_out;
+	
+	tick_50000 TICK0(CLOCK_50, tick_ms);
+	
+	formula_fsm FSM(tick_ms, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
+	
+	LFSR LFSR0(tick_ms, en_lfsr, N);
+	
+	delay DEL0(tick_ms, N, start_delay, time_out);
+	
+	counter_16 COUNT0(tick_ms, time_out, ~KEY[0], count_out);
+	
+	bin2bcd_16 BCD(count_out, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+	
+	hex_to_7seg SEG0(HEX0, BCD_0);
+	hex_to_7seg SEG1(HEX1, BCD_1);
+	hex_to_7seg SEG2(HEX2, BCD_2);
+	hex_to_7seg SEG3(HEX3, BCD_3);
+	hex_to_7seg SEG4(HEX4, BCD_4);
+	hex_to_7seg SEG5(HEX5, 4'b0);
+	
 endmodule
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/ex9.v.bak b/part_2/ex9/verilog_files/ex9.v.bak
index 63427f8..6ca51d6 100644
--- a/part_2/ex9/verilog_files/ex9.v.bak
+++ b/part_2/ex9/verilog_files/ex9.v.bak
@@ -1,23 +1,23 @@
-module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
-	
-	input CLOCK_50;
-	input [3:0] KEY;
-	output [9:0] LEDR;
-	output [6:0] HEX0, HEX1, HEX2;
-	
-	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
-	wire [6:0] N;
-	wire [6:0] bcd_to_hex;
-	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
-	
-	tick_50000 TICK0(CLOCK_50, tick_ms);
-	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
-	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
-	LFSR LFSR0(tick_ms, en_lfsr, N);
-	delay DEL0(tick_ms, N, start_delay, time_out);
-	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
-	hex_to_7seg SEG0(HEX0, BCD_0);
-	hex_to_7seg SEG1(HEX1, BCD_1);
-	hex_to_7seg SEG2(HEX2, BCD_2);
-	
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
+	
+	input CLOCK_50;
+	input [3:0] KEY;
+	output [9:0] LEDR;
+	output [6:0] HEX0, HEX1, HEX2;
+	
+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
+	wire [6:0] N;
+	wire [6:0] bcd_to_hex;
+	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
+	
+	tick_50000 TICK0(CLOCK_50, tick_ms);
+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
+	LFSR LFSR0(tick_ms, en_lfsr, N);
+	delay DEL0(tick_ms, N, start_delay, time_out);
+	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+	hex_to_7seg SEG0(HEX0, BCD_0);
+	hex_to_7seg SEG1(HEX1, BCD_1);
+	hex_to_7seg SEG2(HEX2, BCD_2);
+	
 endmodule
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/formula_fsm.v b/part_2/ex9/verilog_files/formula_fsm.v
index 5b3113c..2a79785 100644
--- a/part_2/ex9/verilog_files/formula_fsm.v
+++ b/part_2/ex9/verilog_files/formula_fsm.v
@@ -1,76 +1,76 @@
-module formula_fsm(clk, trigger, time_out, en_lfsr, start_delay, ledr);
-
-input clk, time_out, trigger;
-output en_lfsr, start_delay;
-output [9:0] ledr;
-
-reg [1:0] state;
-reg led_on, en_lfsr, start_delay;
-reg [9:0] ledr;
-reg [11:0] count;
-
-parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;
-
-initial 
-	begin
-		state = WAIT_TRIGGER;
-		en_lfsr = 1'b0;
-		start_delay = 1'b0;
-		count = 12'd2499;
-	end
-
-always @ (posedge clk)
-	case(state)
-		WAIT_TRIGGER: 
-			begin
-				if(trigger == 1'b1)
-					state <= LIGHT_UP_LEDS;
-			end
-		LIGHT_UP_LEDS:
-				if(ledr == 10'h3ff)
-					state <= WAIT_FOR_TIMEOUT;
-		WAIT_FOR_TIMEOUT:
-				if(time_out == 1'b1)
-					 state <= WAIT_TRIGGER;
-		default: ;
-	endcase
-
-always @ (posedge clk)
-	case(state)
-		WAIT_TRIGGER:
-			ledr = 0;
-		LIGHT_UP_LEDS:
-			begin
-				if(count == 1'b0)
-					begin
-						ledr <= {ledr[8:0], 1'b1};
-						count <= 12'd2499;
-					end
-				else
-					begin
-						count <= count - 1'b1;
-					end
-			end
-		default: count <= 12'd2499;
-	endcase
-	
-always @ (*)
-	case(state)
-		WAIT_TRIGGER:
-			begin
-				en_lfsr = 1'b0;
-				start_delay = 1'b0;
-			end
-		LIGHT_UP_LEDS:
-			begin
-				en_lfsr = 1'b1;
-			end
-		WAIT_FOR_TIMEOUT:
-			begin
-				start_delay = 1'b1;
-				en_lfsr = 1'b0;
-			end
-		default: ;
-	endcase
-
+module formula_fsm(clk, trigger, time_out, en_lfsr, start_delay, ledr);
+
+input clk, time_out, trigger;
+output en_lfsr, start_delay;
+output [9:0] ledr;
+
+reg [1:0] state;
+reg led_on, en_lfsr, start_delay;
+reg [9:0] ledr;
+reg [11:0] count;
+
+parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;
+
+initial 
+	begin
+		state = WAIT_TRIGGER;
+		en_lfsr = 1'b0;
+		start_delay = 1'b0;
+		count = 12'd2499;
+	end
+
+always @ (posedge clk)
+	case(state)
+		WAIT_TRIGGER: 
+			begin
+				if(trigger == 1'b1)
+					state <= LIGHT_UP_LEDS;
+			end
+		LIGHT_UP_LEDS:
+				if(ledr == 10'h3ff)
+					state <= WAIT_FOR_TIMEOUT;
+		WAIT_FOR_TIMEOUT:
+				if(time_out == 1'b1)
+					 state <= WAIT_TRIGGER;
+		default: ;
+	endcase
+
+always @ (posedge clk)
+	case(state)
+		WAIT_TRIGGER:
+			ledr = 0;
+		LIGHT_UP_LEDS:
+			begin
+				if(count == 1'b0)
+					begin
+						ledr <= {ledr[8:0], 1'b1};
+						count <= 12'd2499;
+					end
+				else
+					begin
+						count <= count - 1'b1;
+					end
+			end
+		default: count <= 12'd2499;
+	endcase
+	
+always @ (*)
+	case(state)
+		WAIT_TRIGGER:
+			begin
+				en_lfsr = 1'b0;
+				start_delay = 1'b0;
+			end
+		LIGHT_UP_LEDS:
+			begin
+				en_lfsr = 1'b1;
+			end
+		WAIT_FOR_TIMEOUT:
+			begin
+				start_delay = 1'b1;
+				en_lfsr = 1'b0;
+			end
+		default: ;
+	endcase
+
 endmodule
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/hex_to_7seg.v b/part_2/ex9/verilog_files/hex_to_7seg.v
index 825e466..82aa9a5 100644
--- a/part_2/ex9/verilog_files/hex_to_7seg.v
+++ b/part_2/ex9/verilog_files/hex_to_7seg.v
@@ -1,27 +1,27 @@
-module hex_to_7seg (out, in);
-
-	output [6:0] out;
-	input [3:0] in;
-	
-	reg [6:0] out;
-	
-	always @ (*)
-		case(in)
-			4'h0: out = 7'b1000000;
-			4'h1: out = 7'b1111001;
-			4'h2: out = 7'b0100100;
-			4'h3: out = 7'b0110000;
-			4'h4: out = 7'b0011001;
-			4'h5: out = 7'b0010010;
-			4'h6: out = 7'b0000010;
-			4'h7: out = 7'b1111000;
-			4'h8: out = 7'b0000000;
-			4'h9: out = 7'b0011000;
-			4'ha: out = 7'b0001000;
-			4'hb: out = 7'b0000011;
-			4'hc: out = 7'b1000110;
-			4'hd: out = 7'b0100001;
-			4'he: out = 7'b0000110;
-			4'hf: out = 7'b0001110;
-		endcase
-endmodule
+module hex_to_7seg (out, in);
+
+	output [6:0] out;
+	input [3:0] in;
+	
+	reg [6:0] out;
+	
+	always @ (*)
+		case(in)
+			4'h0: out = 7'b1000000;
+			4'h1: out = 7'b1111001;
+			4'h2: out = 7'b0100100;
+			4'h3: out = 7'b0110000;
+			4'h4: out = 7'b0011001;
+			4'h5: out = 7'b0010010;
+			4'h6: out = 7'b0000010;
+			4'h7: out = 7'b1111000;
+			4'h8: out = 7'b0000000;
+			4'h9: out = 7'b0011000;
+			4'ha: out = 7'b0001000;
+			4'hb: out = 7'b0000011;
+			4'hc: out = 7'b1000110;
+			4'hd: out = 7'b0100001;
+			4'he: out = 7'b0000110;
+			4'hf: out = 7'b0001110;
+		endcase
+endmodule
diff --git a/part_2/ex9/verilog_files/tick_2500.v b/part_2/ex9/verilog_files/tick_2500.v
index a455217..e75a131 100644
--- a/part_2/ex9/verilog_files/tick_2500.v
+++ b/part_2/ex9/verilog_files/tick_2500.v
@@ -1,35 +1,35 @@
-module tick_2500(CLOCK_IN, en, CLK_OUT);
-
-	parameter NBIT = 12;
-	
-	input CLOCK_IN, en;
-	output CLK_OUT;
-	
-	reg [NBIT-1:0] count;
-	
-	reg CLK_OUT;
-	
-	initial 
-		begin
-			count = 12'd2499;
-			CLK_OUT = 1'b0;
-		end
-	
-	always @ (posedge CLOCK_IN)
-		if(en == 1'b1)
-			begin
-				if(count == 1'b0)
-					begin
-						CLK_OUT <= 1'b1;
-						count <= 12'd2499;
-					end
-				else
-					begin
-						count <= count - 1'b1;
-						CLK_OUT <= 1'b0;
-					end
-			end
-		else 
-			CLK_OUT <= 1'b0;
-
+module tick_2500(CLOCK_IN, en, CLK_OUT);
+
+	parameter NBIT = 12;
+	
+	input CLOCK_IN, en;
+	output CLK_OUT;
+	
+	reg [NBIT-1:0] count;
+	
+	reg CLK_OUT;
+	
+	initial 
+		begin
+			count = 12'd2499;
+			CLK_OUT = 1'b0;
+		end
+	
+	always @ (posedge CLOCK_IN)
+		if(en == 1'b1)
+			begin
+				if(count == 1'b0)
+					begin
+						CLK_OUT <= 1'b1;
+						count <= 12'd2499;
+					end
+				else
+					begin
+						count <= count - 1'b1;
+						CLK_OUT <= 1'b0;
+					end
+			end
+		else 
+			CLK_OUT <= 1'b0;
+
 endmodule
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/tick_50000.v b/part_2/ex9/verilog_files/tick_50000.v
index dfb07d1..7ccc81b 100644
--- a/part_2/ex9/verilog_files/tick_50000.v
+++ b/part_2/ex9/verilog_files/tick_50000.v
@@ -1,32 +1,32 @@
-module tick_50000(CLOCK_IN, CLK_OUT);
-
-	parameter NBIT = 16;
-	
-	input CLOCK_IN;
-	output CLK_OUT;
-	
-	reg [NBIT-1:0] count;
-	
-	reg CLK_OUT;
-	
-	initial 
-		begin
-			count = 16'd49999;
-			CLK_OUT = 1'b0;
-		end
-	
-	always @ (posedge CLOCK_IN)
-		begin
-			if(count == 16'b0)
-				begin
-					CLK_OUT <= 1'b1;
-					count <= 16'd49999;
-				end
-			else
-				begin
-					count <= count - 1'b1;
-					CLK_OUT <= 1'b0;
-				end
-		end
-
+module tick_50000(CLOCK_IN, CLK_OUT);
+
+	parameter NBIT = 16;
+	
+	input CLOCK_IN;
+	output CLK_OUT;
+	
+	reg [NBIT-1:0] count;
+	
+	reg CLK_OUT;
+	
+	initial 
+		begin
+			count = 16'd49999;
+			CLK_OUT = 1'b0;
+		end
+	
+	always @ (posedge CLOCK_IN)
+		begin
+			if(count == 16'b0)
+				begin
+					CLK_OUT <= 1'b1;
+					count <= 16'd49999;
+				end
+			else
+				begin
+					count <= count - 1'b1;
+					CLK_OUT <= 1'b0;
+				end
+		end
+
 endmodule
 \ No newline at end of file
diff --git a/part_2/ex9/verilog_files/tick_50000.v.bak b/part_2/ex9/verilog_files/tick_50000.v.bak
index f326b58..45c4166 100644
--- a/part_2/ex9/verilog_files/tick_50000.v.bak
+++ b/part_2/ex9/verilog_files/tick_50000.v.bak
@@ -1,31 +1,31 @@
-module tick_50000(CLOCK_IN, CLK_OUT);
-
-	parameter NBIT = 16;
-	
-	input CLOCK_IN;
-	output CLK_OUT;
-	
-	reg [NBIT-1:0] count;
-	
-	reg CLK_OUT;
-	
-	initial 
-		begin
-			count = 16'd24999;
-			CLK_OUT = 1'b0;
-		end
-	
-	always @ (posedge CLOCK_IN)
-		begin
-			if(count == 16'b0)
-				begin
-					CLK_OUT <= ~CLK_OUT;
-					count <= 16'd24999;
-				end
-			else
-				begin
-					count <= count - 1'b1;
-				end
-		end
-
+module tick_50000(CLOCK_IN, CLK_OUT);
+
+	parameter NBIT = 16;
+	
+	input CLOCK_IN;
+	output CLK_OUT;
+	
+	reg [NBIT-1:0] count;
+	
+	reg CLK_OUT;
+	
+	initial 
+		begin
+			count = 16'd24999;
+			CLK_OUT = 1'b0;
+		end
+	
+	always @ (posedge CLOCK_IN)
+		begin
+			if(count == 16'b0)
+				begin
+					CLK_OUT <= ~CLK_OUT;
+					count <= 16'd24999;
+				end
+			else
+				begin
+					count <= count - 1'b1;
+				end
+		end
+
 endmodule
 \ No newline at end of file
diff --git a/part_3/ex10/db/_cmp.kpt b/part_3/ex10/db/_cmp.kpt
new file mode 100644
index 0000000..1a52cce
--- /dev/null
+++ b/part_3/ex10/db/_cmp.kpt
diff --git a/part_3/ex10/ex10.v.bak b/part_3/ex10/ex10.v.bak
index 8b13789..d3f5a12 100755
--- a/part_3/ex10/ex10.v.bak
+++ b/part_3/ex10/ex10.v.bak
@@ -1 +1 @@
-
+
diff --git a/part_3/ex10/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex10/simulation/modelsim/do_files/tb_spi2dac.do
index b12a7d7..52dd5a2 100755
--- a/part_3/ex10/simulation/modelsim/do_files/tb_spi2dac.do
+++ b/part_3/ex10/simulation/modelsim/do_files/tb_spi2dac.do
@@ -1,17 +1,17 @@
-add wave -position end  sysclk
-add wave -position end -hexadecimal data_in
-add wave -position end load
-add wave -position end  dac_sdi
-add wave -position end  dac_cs
-add wave -position end  dac_sck
-add wave -position end  dac_ld
-force sysclk 1 0, 0 10ns -r 20ns
-force data_in 10'h23b
-force load 0
-run 200ns
-force load 1
-run 400ns
-force load 0
-run 20us
-
-
+add wave -position end  sysclk
+add wave -position end -hexadecimal data_in
+add wave -position end load
+add wave -position end  dac_sdi
+add wave -position end  dac_cs
+add wave -position end  dac_sck
+add wave -position end  dac_ld
+force sysclk 1 0, 0 10ns -r 20ns
+force data_in 10'h23b
+force load 0
+run 200ns
+force load 1
+run 400ns
+force load 0
+run 20us
+
+
diff --git a/part_3/ex10/simulation/modelsim/rtl_work/_info b/part_3/ex10/simulation/modelsim/rtl_work/_info
index 499bdd4..63648ac 100755
--- a/part_3/ex10/simulation/modelsim/rtl_work/_info
+++ b/part_3/ex10/simulation/modelsim/rtl_work/_info
@@ -1,25 +1,25 @@
-m255
-K3
-13
-cModel Technology
-Z0 dC:\New folder\ex10\simulation\modelsim
-vspi2dac
-!i10b 1
-!s100 Yc_:?1WP<4LKj7cQXiUbl1
-IzTNjHgWKkeSFYc0]WM5Gm2
-VFNOGDa=aYhJTn=76LYB@A2
-Z1 dC:\New folder\ex10\simulation\modelsim
-w1478805578
-8C:/New folder/ex10/verilog_files/spi2dac.v
-FC:/New folder/ex10/verilog_files/spi2dac.v
-L0 9
-OV;L;10.1d;51
-r1
-!s85 0
-31
-!s108 1480413939.783000
-!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
-!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
-!s101 -O0
-o-vlog01compat -work work -O0
-!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\ex10\simulation\modelsim
+vspi2dac
+!i10b 1
+!s100 Yc_:?1WP<4LKj7cQXiUbl1
+IzTNjHgWKkeSFYc0]WM5Gm2
+VFNOGDa=aYhJTn=76LYB@A2
+Z1 dC:\New folder\ex10\simulation\modelsim
+w1478805578
+8C:/New folder/ex10/verilog_files/spi2dac.v
+FC:/New folder/ex10/verilog_files/spi2dac.v
+L0 9
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1480413939.783000
+!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
diff --git a/part_3/ex10/simulation/modelsim/rtl_work/_vmake b/part_3/ex10/simulation/modelsim/rtl_work/_vmake
index 2f7e729..b51b305 100755
--- a/part_3/ex10/simulation/modelsim/rtl_work/_vmake
+++ b/part_3/ex10/simulation/modelsim/rtl_work/_vmake
@@ -1,3 +1,3 @@
-m255
-K3
-cModel Technology
+m255
+K3
+cModel Technology
diff --git a/part_3/ex10/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex10/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
index e874ed3..2a503c0 100755
--- a/part_3/ex10/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
+++ b/part_3/ex10/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
@@ -1,30 +1,30 @@
-library verilog;
-use verilog.vl_types.all;
-entity spi2dac is
-    generic(
-        BUF             : vl_logic := Hi1;
-        GA_N            : vl_logic := Hi1;
-        SHDN_N          : vl_logic := Hi1;
-        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
-        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
-        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
-        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
-    );
-    port(
-        sysclk          : in     vl_logic;
-        data_in         : in     vl_logic_vector(9 downto 0);
-        load            : in     vl_logic;
-        dac_sdi         : out    vl_logic;
-        dac_cs          : out    vl_logic;
-        dac_sck         : out    vl_logic;
-        dac_ld          : out    vl_logic
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of BUF : constant is 1;
-    attribute mti_svvh_generic_type of GA_N : constant is 1;
-    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
-    attribute mti_svvh_generic_type of TC : constant is 1;
-    attribute mti_svvh_generic_type of IDLE : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
-end spi2dac;
+library verilog;
+use verilog.vl_types.all;
+entity spi2dac is
+    generic(
+        BUF             : vl_logic := Hi1;
+        GA_N            : vl_logic := Hi1;
+        SHDN_N          : vl_logic := Hi1;
+        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
+        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
+    );
+    port(
+        sysclk          : in     vl_logic;
+        data_in         : in     vl_logic_vector(9 downto 0);
+        load            : in     vl_logic;
+        dac_sdi         : out    vl_logic;
+        dac_cs          : out    vl_logic;
+        dac_sck         : out    vl_logic;
+        dac_ld          : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BUF : constant is 1;
+    attribute mti_svvh_generic_type of GA_N : constant is 1;
+    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
+    attribute mti_svvh_generic_type of TC : constant is 1;
+    attribute mti_svvh_generic_type of IDLE : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
+end spi2dac;
diff --git a/part_3/ex11/.qsys_edit/filters.xml b/part_3/ex11/.qsys_edit/filters.xml
index 2c6ab93..25484e0 100755
--- a/part_3/ex11/.qsys_edit/filters.xml
+++ b/part_3/ex11/.qsys_edit/filters.xml
@@ -1,2 +1,2 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<filters version="16.0" />
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="16.0" />
diff --git a/part_3/ex11/.qsys_edit/preferences.xml b/part_3/ex11/.qsys_edit/preferences.xml
index c5b7680..ea0fb24 100755
--- a/part_3/ex11/.qsys_edit/preferences.xml
+++ b/part_3/ex11/.qsys_edit/preferences.xml
@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<preferences>
- <debug showDebugMenu="0" />
- <systemtable filter="All Interfaces">
-  <columns>
-   <connections preferredWidth="47" />
-   <irq preferredWidth="34" />
-  </columns>
- </systemtable>
- <library expandedCategories="Project,Library" />
- <window width="1100" height="800" x="0" y="0" />
-</preferences>
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="47" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Project,Library" />
+ <window width="1100" height="800" x="0" y="0" />
+</preferences>
diff --git a/part_3/ex11/db/_cmp.kpt b/part_3/ex11/db/_cmp.kpt
new file mode 100644
index 0000000..bd9e7c9
--- /dev/null
+++ b/part_3/ex11/db/_cmp.kpt
diff --git a/part_3/ex11/ex10.v.bak b/part_3/ex11/ex10.v.bak
index 8b13789..d3f5a12 100755
--- a/part_3/ex11/ex10.v.bak
+++ b/part_3/ex11/ex10.v.bak
@@ -1 +1 @@
-
+
diff --git a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do
index b12a7d7..52dd5a2 100755
--- a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do
+++ b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do
@@ -1,17 +1,17 @@
-add wave -position end  sysclk
-add wave -position end -hexadecimal data_in
-add wave -position end load
-add wave -position end  dac_sdi
-add wave -position end  dac_cs
-add wave -position end  dac_sck
-add wave -position end  dac_ld
-force sysclk 1 0, 0 10ns -r 20ns
-force data_in 10'h23b
-force load 0
-run 200ns
-force load 1
-run 400ns
-force load 0
-run 20us
-
-
+add wave -position end  sysclk
+add wave -position end -hexadecimal data_in
+add wave -position end load
+add wave -position end  dac_sdi
+add wave -position end  dac_cs
+add wave -position end  dac_sck
+add wave -position end  dac_ld
+force sysclk 1 0, 0 10ns -r 20ns
+force data_in 10'h23b
+force load 0
+run 200ns
+force load 1
+run 400ns
+force load 0
+run 20us
+
+
diff --git a/part_3/ex11/simulation/modelsim/rtl_work/_info b/part_3/ex11/simulation/modelsim/rtl_work/_info
index 499bdd4..63648ac 100755
--- a/part_3/ex11/simulation/modelsim/rtl_work/_info
+++ b/part_3/ex11/simulation/modelsim/rtl_work/_info
@@ -1,25 +1,25 @@
-m255
-K3
-13
-cModel Technology
-Z0 dC:\New folder\ex10\simulation\modelsim
-vspi2dac
-!i10b 1
-!s100 Yc_:?1WP<4LKj7cQXiUbl1
-IzTNjHgWKkeSFYc0]WM5Gm2
-VFNOGDa=aYhJTn=76LYB@A2
-Z1 dC:\New folder\ex10\simulation\modelsim
-w1478805578
-8C:/New folder/ex10/verilog_files/spi2dac.v
-FC:/New folder/ex10/verilog_files/spi2dac.v
-L0 9
-OV;L;10.1d;51
-r1
-!s85 0
-31
-!s108 1480413939.783000
-!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
-!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
-!s101 -O0
-o-vlog01compat -work work -O0
-!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\ex10\simulation\modelsim
+vspi2dac
+!i10b 1
+!s100 Yc_:?1WP<4LKj7cQXiUbl1
+IzTNjHgWKkeSFYc0]WM5Gm2
+VFNOGDa=aYhJTn=76LYB@A2
+Z1 dC:\New folder\ex10\simulation\modelsim
+w1478805578
+8C:/New folder/ex10/verilog_files/spi2dac.v
+FC:/New folder/ex10/verilog_files/spi2dac.v
+L0 9
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1480413939.783000
+!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
diff --git a/part_3/ex11/simulation/modelsim/rtl_work/_vmake b/part_3/ex11/simulation/modelsim/rtl_work/_vmake
index 2f7e729..b51b305 100755
--- a/part_3/ex11/simulation/modelsim/rtl_work/_vmake
+++ b/part_3/ex11/simulation/modelsim/rtl_work/_vmake
@@ -1,3 +1,3 @@
-m255
-K3
-cModel Technology
+m255
+K3
+cModel Technology
diff --git a/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
index e874ed3..2a503c0 100755
--- a/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
+++ b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
@@ -1,30 +1,30 @@
-library verilog;
-use verilog.vl_types.all;
-entity spi2dac is
-    generic(
-        BUF             : vl_logic := Hi1;
-        GA_N            : vl_logic := Hi1;
-        SHDN_N          : vl_logic := Hi1;
-        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
-        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
-        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
-        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
-    );
-    port(
-        sysclk          : in     vl_logic;
-        data_in         : in     vl_logic_vector(9 downto 0);
-        load            : in     vl_logic;
-        dac_sdi         : out    vl_logic;
-        dac_cs          : out    vl_logic;
-        dac_sck         : out    vl_logic;
-        dac_ld          : out    vl_logic
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of BUF : constant is 1;
-    attribute mti_svvh_generic_type of GA_N : constant is 1;
-    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
-    attribute mti_svvh_generic_type of TC : constant is 1;
-    attribute mti_svvh_generic_type of IDLE : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
-end spi2dac;
+library verilog;
+use verilog.vl_types.all;
+entity spi2dac is
+    generic(
+        BUF             : vl_logic := Hi1;
+        GA_N            : vl_logic := Hi1;
+        SHDN_N          : vl_logic := Hi1;
+        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
+        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
+    );
+    port(
+        sysclk          : in     vl_logic;
+        data_in         : in     vl_logic_vector(9 downto 0);
+        load            : in     vl_logic;
+        dac_sdi         : out    vl_logic;
+        dac_cs          : out    vl_logic;
+        dac_sck         : out    vl_logic;
+        dac_ld          : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BUF : constant is 1;
+    attribute mti_svvh_generic_type of GA_N : constant is 1;
+    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
+    attribute mti_svvh_generic_type of TC : constant is 1;
+    attribute mti_svvh_generic_type of IDLE : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
+end spi2dac;
diff --git a/part_3/ex12/db/_cmp.kpt b/part_3/ex12/db/_cmp.kpt
new file mode 100644
index 0000000..fa3c9a7
--- /dev/null
+++ b/part_3/ex12/db/_cmp.kpt
diff --git a/part_3/ex12/rom_data/rom_data.mif b/part_3/ex12/rom_data/rom_data.mif
index a688b6f..45464a9 100755
--- a/part_3/ex12/rom_data/rom_data.mif
+++ b/part_3/ex12/rom_data/rom_data.mif
@@ -1,1032 +1,1032 @@
--- ROM Initialization file
-WIDTH = 10;
-DEPTH = 1024;
-ADDRESS_RADIX = HEX;
-DATA_RADIX = HEX;
-CONTENT
-BEGIN
-   0 :  200;
-   1 :  203;
-   2 :  206;
-   3 :  209;
-   4 :  20C;
-   5 :  20F;
-   6 :  212;
-   7 :  215;
-   8 :  219;
-   9 :  21C;
-   A :  21F;
-   B :  222;
-   C :  225;
-   D :  228;
-   E :  22B;
-   F :  22F;
-  10 :  232;
-  11 :  235;
-  12 :  238;
-  13 :  23B;
-  14 :  23E;
-  15 :  241;
-  16 :  244;
-  17 :  247;
-  18 :  24B;
-  19 :  24E;
-  1A :  251;
-  1B :  254;
-  1C :  257;
-  1D :  25A;
-  1E :  25D;
-  1F :  260;
-  20 :  263;
-  21 :  266;
-  22 :  269;
-  23 :  26D;
-  24 :  270;
-  25 :  273;
-  26 :  276;
-  27 :  279;
-  28 :  27C;
-  29 :  27F;
-  2A :  282;
-  2B :  285;
-  2C :  288;
-  2D :  28B;
-  2E :  28E;
-  2F :  291;
-  30 :  294;
-  31 :  297;
-  32 :  29A;
-  33 :  29D;
-  34 :  2A0;
-  35 :  2A3;
-  36 :  2A6;
-  37 :  2A9;
-  38 :  2AC;
-  39 :  2AF;
-  3A :  2B2;
-  3B :  2B5;
-  3C :  2B8;
-  3D :  2BB;
-  3E :  2BD;
-  3F :  2C0;
-  40 :  2C3;
-  41 :  2C6;
-  42 :  2C9;
-  43 :  2CC;
-  44 :  2CF;
-  45 :  2D2;
-  46 :  2D5;
-  47 :  2D7;
-  48 :  2DA;
-  49 :  2DD;
-  4A :  2E0;
-  4B :  2E3;
-  4C :  2E5;
-  4D :  2E8;
-  4E :  2EB;
-  4F :  2EE;
-  50 :  2F1;
-  51 :  2F3;
-  52 :  2F6;
-  53 :  2F9;
-  54 :  2FC;
-  55 :  2FE;
-  56 :  301;
-  57 :  304;
-  58 :  306;
-  59 :  309;
-  5A :  30C;
-  5B :  30E;
-  5C :  311;
-  5D :  314;
-  5E :  316;
-  5F :  319;
-  60 :  31C;
-  61 :  31E;
-  62 :  321;
-  63 :  323;
-  64 :  326;
-  65 :  329;
-  66 :  32B;
-  67 :  32E;
-  68 :  330;
-  69 :  333;
-  6A :  335;
-  6B :  338;
-  6C :  33A;
-  6D :  33D;
-  6E :  33F;
-  6F :  342;
-  70 :  344;
-  71 :  346;
-  72 :  349;
-  73 :  34B;
-  74 :  34E;
-  75 :  350;
-  76 :  352;
-  77 :  355;
-  78 :  357;
-  79 :  359;
-  7A :  35C;
-  7B :  35E;
-  7C :  360;
-  7D :  362;
-  7E :  365;
-  7F :  367;
-  80 :  369;
-  81 :  36B;
-  82 :  36E;
-  83 :  370;
-  84 :  372;
-  85 :  374;
-  86 :  376;
-  87 :  378;
-  88 :  37A;
-  89 :  37D;
-  8A :  37F;
-  8B :  381;
-  8C :  383;
-  8D :  385;
-  8E :  387;
-  8F :  389;
-  90 :  38B;
-  91 :  38D;
-  92 :  38F;
-  93 :  391;
-  94 :  393;
-  95 :  395;
-  96 :  397;
-  97 :  398;
-  98 :  39A;
-  99 :  39C;
-  9A :  39E;
-  9B :  3A0;
-  9C :  3A2;
-  9D :  3A3;
-  9E :  3A5;
-  9F :  3A7;
-  A0 :  3A9;
-  A1 :  3AB;
-  A2 :  3AC;
-  A3 :  3AE;
-  A4 :  3B0;
-  A5 :  3B1;
-  A6 :  3B3;
-  A7 :  3B5;
-  A8 :  3B6;
-  A9 :  3B8;
-  AA :  3B9;
-  AB :  3BB;
-  AC :  3BD;
-  AD :  3BE;
-  AE :  3C0;
-  AF :  3C1;
-  B0 :  3C3;
-  B1 :  3C4;
-  B2 :  3C6;
-  B3 :  3C7;
-  B4 :  3C8;
-  B5 :  3CA;
-  B6 :  3CB;
-  B7 :  3CD;
-  B8 :  3CE;
-  B9 :  3CF;
-  BA :  3D1;
-  BB :  3D2;
-  BC :  3D3;
-  BD :  3D4;
-  BE :  3D6;
-  BF :  3D7;
-  C0 :  3D8;
-  C1 :  3D9;
-  C2 :  3DA;
-  C3 :  3DC;
-  C4 :  3DD;
-  C5 :  3DE;
-  C6 :  3DF;
-  C7 :  3E0;
-  C8 :  3E1;
-  C9 :  3E2;
-  CA :  3E3;
-  CB :  3E4;
-  CC :  3E5;
-  CD :  3E6;
-  CE :  3E7;
-  CF :  3E8;
-  D0 :  3E9;
-  D1 :  3EA;
-  D2 :  3EB;
-  D3 :  3EC;
-  D4 :  3EC;
-  D5 :  3ED;
-  D6 :  3EE;
-  D7 :  3EF;
-  D8 :  3F0;
-  D9 :  3F0;
-  DA :  3F1;
-  DB :  3F2;
-  DC :  3F3;
-  DD :  3F3;
-  DE :  3F4;
-  DF :  3F5;
-  E0 :  3F5;
-  E1 :  3F6;
-  E2 :  3F6;
-  E3 :  3F7;
-  E4 :  3F7;
-  E5 :  3F8;
-  E6 :  3F9;
-  E7 :  3F9;
-  E8 :  3F9;
-  E9 :  3FA;
-  EA :  3FA;
-  EB :  3FB;
-  EC :  3FB;
-  ED :  3FC;
-  EE :  3FC;
-  EF :  3FC;
-  F0 :  3FD;
-  F1 :  3FD;
-  F2 :  3FD;
-  F3 :  3FD;
-  F4 :  3FE;
-  F5 :  3FE;
-  F6 :  3FE;
-  F7 :  3FE;
-  F8 :  3FE;
-  F9 :  3FF;
-  FA :  3FF;
-  FB :  3FF;
-  FC :  3FF;
-  FD :  3FF;
-  FE :  3FF;
-  FF :  3FF;
- 100 :  3FF;
- 101 :  3FF;
- 102 :  3FF;
- 103 :  3FF;
- 104 :  3FF;
- 105 :  3FF;
- 106 :  3FF;
- 107 :  3FF;
- 108 :  3FE;
- 109 :  3FE;
- 10A :  3FE;
- 10B :  3FE;
- 10C :  3FE;
- 10D :  3FD;
- 10E :  3FD;
- 10F :  3FD;
- 110 :  3FD;
- 111 :  3FC;
- 112 :  3FC;
- 113 :  3FC;
- 114 :  3FB;
- 115 :  3FB;
- 116 :  3FA;
- 117 :  3FA;
- 118 :  3F9;
- 119 :  3F9;
- 11A :  3F9;
- 11B :  3F8;
- 11C :  3F7;
- 11D :  3F7;
- 11E :  3F6;
- 11F :  3F6;
- 120 :  3F5;
- 121 :  3F5;
- 122 :  3F4;
- 123 :  3F3;
- 124 :  3F3;
- 125 :  3F2;
- 126 :  3F1;
- 127 :  3F0;
- 128 :  3F0;
- 129 :  3EF;
- 12A :  3EE;
- 12B :  3ED;
- 12C :  3EC;
- 12D :  3EC;
- 12E :  3EB;
- 12F :  3EA;
- 130 :  3E9;
- 131 :  3E8;
- 132 :  3E7;
- 133 :  3E6;
- 134 :  3E5;
- 135 :  3E4;
- 136 :  3E3;
- 137 :  3E2;
- 138 :  3E1;
- 139 :  3E0;
- 13A :  3DF;
- 13B :  3DE;
- 13C :  3DD;
- 13D :  3DC;
- 13E :  3DA;
- 13F :  3D9;
- 140 :  3D8;
- 141 :  3D7;
- 142 :  3D6;
- 143 :  3D4;
- 144 :  3D3;
- 145 :  3D2;
- 146 :  3D1;
- 147 :  3CF;
- 148 :  3CE;
- 149 :  3CD;
- 14A :  3CB;
- 14B :  3CA;
- 14C :  3C8;
- 14D :  3C7;
- 14E :  3C6;
- 14F :  3C4;
- 150 :  3C3;
- 151 :  3C1;
- 152 :  3C0;
- 153 :  3BE;
- 154 :  3BD;
- 155 :  3BB;
- 156 :  3B9;
- 157 :  3B8;
- 158 :  3B6;
- 159 :  3B5;
- 15A :  3B3;
- 15B :  3B1;
- 15C :  3B0;
- 15D :  3AE;
- 15E :  3AC;
- 15F :  3AB;
- 160 :  3A9;
- 161 :  3A7;
- 162 :  3A5;
- 163 :  3A3;
- 164 :  3A2;
- 165 :  3A0;
- 166 :  39E;
- 167 :  39C;
- 168 :  39A;
- 169 :  398;
- 16A :  397;
- 16B :  395;
- 16C :  393;
- 16D :  391;
- 16E :  38F;
- 16F :  38D;
- 170 :  38B;
- 171 :  389;
- 172 :  387;
- 173 :  385;
- 174 :  383;
- 175 :  381;
- 176 :  37F;
- 177 :  37D;
- 178 :  37A;
- 179 :  378;
- 17A :  376;
- 17B :  374;
- 17C :  372;
- 17D :  370;
- 17E :  36E;
- 17F :  36B;
- 180 :  369;
- 181 :  367;
- 182 :  365;
- 183 :  362;
- 184 :  360;
- 185 :  35E;
- 186 :  35C;
- 187 :  359;
- 188 :  357;
- 189 :  355;
- 18A :  352;
- 18B :  350;
- 18C :  34E;
- 18D :  34B;
- 18E :  349;
- 18F :  346;
- 190 :  344;
- 191 :  342;
- 192 :  33F;
- 193 :  33D;
- 194 :  33A;
- 195 :  338;
- 196 :  335;
- 197 :  333;
- 198 :  330;
- 199 :  32E;
- 19A :  32B;
- 19B :  329;
- 19C :  326;
- 19D :  323;
- 19E :  321;
- 19F :  31E;
- 1A0 :  31C;
- 1A1 :  319;
- 1A2 :  316;
- 1A3 :  314;
- 1A4 :  311;
- 1A5 :  30E;
- 1A6 :  30C;
- 1A7 :  309;
- 1A8 :  306;
- 1A9 :  304;
- 1AA :  301;
- 1AB :  2FE;
- 1AC :  2FC;
- 1AD :  2F9;
- 1AE :  2F6;
- 1AF :  2F3;
- 1B0 :  2F1;
- 1B1 :  2EE;
- 1B2 :  2EB;
- 1B3 :  2E8;
- 1B4 :  2E5;
- 1B5 :  2E3;
- 1B6 :  2E0;
- 1B7 :  2DD;
- 1B8 :  2DA;
- 1B9 :  2D7;
- 1BA :  2D5;
- 1BB :  2D2;
- 1BC :  2CF;
- 1BD :  2CC;
- 1BE :  2C9;
- 1BF :  2C6;
- 1C0 :  2C3;
- 1C1 :  2C0;
- 1C2 :  2BD;
- 1C3 :  2BB;
- 1C4 :  2B8;
- 1C5 :  2B5;
- 1C6 :  2B2;
- 1C7 :  2AF;
- 1C8 :  2AC;
- 1C9 :  2A9;
- 1CA :  2A6;
- 1CB :  2A3;
- 1CC :  2A0;
- 1CD :  29D;
- 1CE :  29A;
- 1CF :  297;
- 1D0 :  294;
- 1D1 :  291;
- 1D2 :  28E;
- 1D3 :  28B;
- 1D4 :  288;
- 1D5 :  285;
- 1D6 :  282;
- 1D7 :  27F;
- 1D8 :  27C;
- 1D9 :  279;
- 1DA :  276;
- 1DB :  273;
- 1DC :  270;
- 1DD :  26D;
- 1DE :  269;
- 1DF :  266;
- 1E0 :  263;
- 1E1 :  260;
- 1E2 :  25D;
- 1E3 :  25A;
- 1E4 :  257;
- 1E5 :  254;
- 1E6 :  251;
- 1E7 :  24E;
- 1E8 :  24B;
- 1E9 :  247;
- 1EA :  244;
- 1EB :  241;
- 1EC :  23E;
- 1ED :  23B;
- 1EE :  238;
- 1EF :  235;
- 1F0 :  232;
- 1F1 :  22F;
- 1F2 :  22B;
- 1F3 :  228;
- 1F4 :  225;
- 1F5 :  222;
- 1F6 :  21F;
- 1F7 :  21C;
- 1F8 :  219;
- 1F9 :  215;
- 1FA :  212;
- 1FB :  20F;
- 1FC :  20C;
- 1FD :  209;
- 1FE :  206;
- 1FF :  203;
- 200 :  200;
- 201 :  1FC;
- 202 :  1F9;
- 203 :  1F6;
- 204 :  1F3;
- 205 :  1F0;
- 206 :  1ED;
- 207 :  1EA;
- 208 :  1E6;
- 209 :  1E3;
- 20A :  1E0;
- 20B :  1DD;
- 20C :  1DA;
- 20D :  1D7;
- 20E :  1D4;
- 20F :  1D0;
- 210 :  1CD;
- 211 :  1CA;
- 212 :  1C7;
- 213 :  1C4;
- 214 :  1C1;
- 215 :  1BE;
- 216 :  1BB;
- 217 :  1B8;
- 218 :  1B4;
- 219 :  1B1;
- 21A :  1AE;
- 21B :  1AB;
- 21C :  1A8;
- 21D :  1A5;
- 21E :  1A2;
- 21F :  19F;
- 220 :  19C;
- 221 :  199;
- 222 :  196;
- 223 :  192;
- 224 :  18F;
- 225 :  18C;
- 226 :  189;
- 227 :  186;
- 228 :  183;
- 229 :  180;
- 22A :  17D;
- 22B :  17A;
- 22C :  177;
- 22D :  174;
- 22E :  171;
- 22F :  16E;
- 230 :  16B;
- 231 :  168;
- 232 :  165;
- 233 :  162;
- 234 :  15F;
- 235 :  15C;
- 236 :  159;
- 237 :  156;
- 238 :  153;
- 239 :  150;
- 23A :  14D;
- 23B :  14A;
- 23C :  147;
- 23D :  144;
- 23E :  142;
- 23F :  13F;
- 240 :  13C;
- 241 :  139;
- 242 :  136;
- 243 :  133;
- 244 :  130;
- 245 :  12D;
- 246 :  12A;
- 247 :  128;
- 248 :  125;
- 249 :  122;
- 24A :  11F;
- 24B :  11C;
- 24C :  11A;
- 24D :  117;
- 24E :  114;
- 24F :  111;
- 250 :  10E;
- 251 :  10C;
- 252 :  109;
- 253 :  106;
- 254 :  103;
- 255 :  101;
- 256 :   FE;
- 257 :   FB;
- 258 :   F9;
- 259 :   F6;
- 25A :   F3;
- 25B :   F1;
- 25C :   EE;
- 25D :   EB;
- 25E :   E9;
- 25F :   E6;
- 260 :   E3;
- 261 :   E1;
- 262 :   DE;
- 263 :   DC;
- 264 :   D9;
- 265 :   D6;
- 266 :   D4;
- 267 :   D1;
- 268 :   CF;
- 269 :   CC;
- 26A :   CA;
- 26B :   C7;
- 26C :   C5;
- 26D :   C2;
- 26E :   C0;
- 26F :   BD;
- 270 :   BB;
- 271 :   B9;
- 272 :   B6;
- 273 :   B4;
- 274 :   B1;
- 275 :   AF;
- 276 :   AD;
- 277 :   AA;
- 278 :   A8;
- 279 :   A6;
- 27A :   A3;
- 27B :   A1;
- 27C :   9F;
- 27D :   9D;
- 27E :   9A;
- 27F :   98;
- 280 :   96;
- 281 :   94;
- 282 :   91;
- 283 :   8F;
- 284 :   8D;
- 285 :   8B;
- 286 :   89;
- 287 :   87;
- 288 :   85;
- 289 :   82;
- 28A :   80;
- 28B :   7E;
- 28C :   7C;
- 28D :   7A;
- 28E :   78;
- 28F :   76;
- 290 :   74;
- 291 :   72;
- 292 :   70;
- 293 :   6E;
- 294 :   6C;
- 295 :   6A;
- 296 :   68;
- 297 :   67;
- 298 :   65;
- 299 :   63;
- 29A :   61;
- 29B :   5F;
- 29C :   5D;
- 29D :   5C;
- 29E :   5A;
- 29F :   58;
- 2A0 :   56;
- 2A1 :   54;
- 2A2 :   53;
- 2A3 :   51;
- 2A4 :   4F;
- 2A5 :   4E;
- 2A6 :   4C;
- 2A7 :   4A;
- 2A8 :   49;
- 2A9 :   47;
- 2AA :   46;
- 2AB :   44;
- 2AC :   42;
- 2AD :   41;
- 2AE :   3F;
- 2AF :   3E;
- 2B0 :   3C;
- 2B1 :   3B;
- 2B2 :   39;
- 2B3 :   38;
- 2B4 :   37;
- 2B5 :   35;
- 2B6 :   34;
- 2B7 :   32;
- 2B8 :   31;
- 2B9 :   30;
- 2BA :   2E;
- 2BB :   2D;
- 2BC :   2C;
- 2BD :   2B;
- 2BE :   29;
- 2BF :   28;
- 2C0 :   27;
- 2C1 :   26;
- 2C2 :   25;
- 2C3 :   23;
- 2C4 :   22;
- 2C5 :   21;
- 2C6 :   20;
- 2C7 :   1F;
- 2C8 :   1E;
- 2C9 :   1D;
- 2CA :   1C;
- 2CB :   1B;
- 2CC :   1A;
- 2CD :   19;
- 2CE :   18;
- 2CF :   17;
- 2D0 :   16;
- 2D1 :   15;
- 2D2 :   14;
- 2D3 :   13;
- 2D4 :   13;
- 2D5 :   12;
- 2D6 :   11;
- 2D7 :   10;
- 2D8 :    F;
- 2D9 :    F;
- 2DA :    E;
- 2DB :    D;
- 2DC :    C;
- 2DD :    C;
- 2DE :    B;
- 2DF :    A;
- 2E0 :    A;
- 2E1 :    9;
- 2E2 :    9;
- 2E3 :    8;
- 2E4 :    8;
- 2E5 :    7;
- 2E6 :    6;
- 2E7 :    6;
- 2E8 :    6;
- 2E9 :    5;
- 2EA :    5;
- 2EB :    4;
- 2EC :    4;
- 2ED :    3;
- 2EE :    3;
- 2EF :    3;
- 2F0 :    2;
- 2F1 :    2;
- 2F2 :    2;
- 2F3 :    2;
- 2F4 :    1;
- 2F5 :    1;
- 2F6 :    1;
- 2F7 :    1;
- 2F8 :    1;
- 2F9 :    0;
- 2FA :    0;
- 2FB :    0;
- 2FC :    0;
- 2FD :    0;
- 2FE :    0;
- 2FF :    0;
- 300 :    0;
- 301 :    0;
- 302 :    0;
- 303 :    0;
- 304 :    0;
- 305 :    0;
- 306 :    0;
- 307 :    0;
- 308 :    1;
- 309 :    1;
- 30A :    1;
- 30B :    1;
- 30C :    1;
- 30D :    2;
- 30E :    2;
- 30F :    2;
- 310 :    2;
- 311 :    3;
- 312 :    3;
- 313 :    3;
- 314 :    4;
- 315 :    4;
- 316 :    5;
- 317 :    5;
- 318 :    6;
- 319 :    6;
- 31A :    6;
- 31B :    7;
- 31C :    8;
- 31D :    8;
- 31E :    9;
- 31F :    9;
- 320 :    A;
- 321 :    A;
- 322 :    B;
- 323 :    C;
- 324 :    C;
- 325 :    D;
- 326 :    E;
- 327 :    F;
- 328 :    F;
- 329 :   10;
- 32A :   11;
- 32B :   12;
- 32C :   13;
- 32D :   13;
- 32E :   14;
- 32F :   15;
- 330 :   16;
- 331 :   17;
- 332 :   18;
- 333 :   19;
- 334 :   1A;
- 335 :   1B;
- 336 :   1C;
- 337 :   1D;
- 338 :   1E;
- 339 :   1F;
- 33A :   20;
- 33B :   21;
- 33C :   22;
- 33D :   23;
- 33E :   25;
- 33F :   26;
- 340 :   27;
- 341 :   28;
- 342 :   29;
- 343 :   2B;
- 344 :   2C;
- 345 :   2D;
- 346 :   2E;
- 347 :   30;
- 348 :   31;
- 349 :   32;
- 34A :   34;
- 34B :   35;
- 34C :   37;
- 34D :   38;
- 34E :   39;
- 34F :   3B;
- 350 :   3C;
- 351 :   3E;
- 352 :   3F;
- 353 :   41;
- 354 :   42;
- 355 :   44;
- 356 :   46;
- 357 :   47;
- 358 :   49;
- 359 :   4A;
- 35A :   4C;
- 35B :   4E;
- 35C :   4F;
- 35D :   51;
- 35E :   53;
- 35F :   54;
- 360 :   56;
- 361 :   58;
- 362 :   5A;
- 363 :   5C;
- 364 :   5D;
- 365 :   5F;
- 366 :   61;
- 367 :   63;
- 368 :   65;
- 369 :   67;
- 36A :   68;
- 36B :   6A;
- 36C :   6C;
- 36D :   6E;
- 36E :   70;
- 36F :   72;
- 370 :   74;
- 371 :   76;
- 372 :   78;
- 373 :   7A;
- 374 :   7C;
- 375 :   7E;
- 376 :   80;
- 377 :   82;
- 378 :   85;
- 379 :   87;
- 37A :   89;
- 37B :   8B;
- 37C :   8D;
- 37D :   8F;
- 37E :   91;
- 37F :   94;
- 380 :   96;
- 381 :   98;
- 382 :   9A;
- 383 :   9D;
- 384 :   9F;
- 385 :   A1;
- 386 :   A3;
- 387 :   A6;
- 388 :   A8;
- 389 :   AA;
- 38A :   AD;
- 38B :   AF;
- 38C :   B1;
- 38D :   B4;
- 38E :   B6;
- 38F :   B9;
- 390 :   BB;
- 391 :   BD;
- 392 :   C0;
- 393 :   C2;
- 394 :   C5;
- 395 :   C7;
- 396 :   CA;
- 397 :   CC;
- 398 :   CF;
- 399 :   D1;
- 39A :   D4;
- 39B :   D6;
- 39C :   D9;
- 39D :   DC;
- 39E :   DE;
- 39F :   E1;
- 3A0 :   E3;
- 3A1 :   E6;
- 3A2 :   E9;
- 3A3 :   EB;
- 3A4 :   EE;
- 3A5 :   F1;
- 3A6 :   F3;
- 3A7 :   F6;
- 3A8 :   F9;
- 3A9 :   FB;
- 3AA :   FE;
- 3AB :  101;
- 3AC :  103;
- 3AD :  106;
- 3AE :  109;
- 3AF :  10C;
- 3B0 :  10E;
- 3B1 :  111;
- 3B2 :  114;
- 3B3 :  117;
- 3B4 :  11A;
- 3B5 :  11C;
- 3B6 :  11F;
- 3B7 :  122;
- 3B8 :  125;
- 3B9 :  128;
- 3BA :  12A;
- 3BB :  12D;
- 3BC :  130;
- 3BD :  133;
- 3BE :  136;
- 3BF :  139;
- 3C0 :  13C;
- 3C1 :  13F;
- 3C2 :  142;
- 3C3 :  144;
- 3C4 :  147;
- 3C5 :  14A;
- 3C6 :  14D;
- 3C7 :  150;
- 3C8 :  153;
- 3C9 :  156;
- 3CA :  159;
- 3CB :  15C;
- 3CC :  15F;
- 3CD :  162;
- 3CE :  165;
- 3CF :  168;
- 3D0 :  16B;
- 3D1 :  16E;
- 3D2 :  171;
- 3D3 :  174;
- 3D4 :  177;
- 3D5 :  17A;
- 3D6 :  17D;
- 3D7 :  180;
- 3D8 :  183;
- 3D9 :  186;
- 3DA :  189;
- 3DB :  18C;
- 3DC :  18F;
- 3DD :  192;
- 3DE :  196;
- 3DF :  199;
- 3E0 :  19C;
- 3E1 :  19F;
- 3E2 :  1A2;
- 3E3 :  1A5;
- 3E4 :  1A8;
- 3E5 :  1AB;
- 3E6 :  1AE;
- 3E7 :  1B1;
- 3E8 :  1B4;
- 3E9 :  1B8;
- 3EA :  1BB;
- 3EB :  1BE;
- 3EC :  1C1;
- 3ED :  1C4;
- 3EE :  1C7;
- 3EF :  1CA;
- 3F0 :  1CD;
- 3F1 :  1D0;
- 3F2 :  1D4;
- 3F3 :  1D7;
- 3F4 :  1DA;
- 3F5 :  1DD;
- 3F6 :  1E0;
- 3F7 :  1E3;
- 3F8 :  1E6;
- 3F9 :  1EA;
- 3FA :  1ED;
- 3FB :  1F0;
- 3FC :  1F3;
- 3FD :  1F6;
- 3FE :  1F9;
- 3FF :  1FC;
-END
+-- ROM Initialization file
+WIDTH = 10;
+DEPTH = 1024;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+   0 :  200;
+   1 :  203;
+   2 :  206;
+   3 :  209;
+   4 :  20C;
+   5 :  20F;
+   6 :  212;
+   7 :  215;
+   8 :  219;
+   9 :  21C;
+   A :  21F;
+   B :  222;
+   C :  225;
+   D :  228;
+   E :  22B;
+   F :  22F;
+  10 :  232;
+  11 :  235;
+  12 :  238;
+  13 :  23B;
+  14 :  23E;
+  15 :  241;
+  16 :  244;
+  17 :  247;
+  18 :  24B;
+  19 :  24E;
+  1A :  251;
+  1B :  254;
+  1C :  257;
+  1D :  25A;
+  1E :  25D;
+  1F :  260;
+  20 :  263;
+  21 :  266;
+  22 :  269;
+  23 :  26D;
+  24 :  270;
+  25 :  273;
+  26 :  276;
+  27 :  279;
+  28 :  27C;
+  29 :  27F;
+  2A :  282;
+  2B :  285;
+  2C :  288;
+  2D :  28B;
+  2E :  28E;
+  2F :  291;
+  30 :  294;
+  31 :  297;
+  32 :  29A;
+  33 :  29D;
+  34 :  2A0;
+  35 :  2A3;
+  36 :  2A6;
+  37 :  2A9;
+  38 :  2AC;
+  39 :  2AF;
+  3A :  2B2;
+  3B :  2B5;
+  3C :  2B8;
+  3D :  2BB;
+  3E :  2BD;
+  3F :  2C0;
+  40 :  2C3;
+  41 :  2C6;
+  42 :  2C9;
+  43 :  2CC;
+  44 :  2CF;
+  45 :  2D2;
+  46 :  2D5;
+  47 :  2D7;
+  48 :  2DA;
+  49 :  2DD;
+  4A :  2E0;
+  4B :  2E3;
+  4C :  2E5;
+  4D :  2E8;
+  4E :  2EB;
+  4F :  2EE;
+  50 :  2F1;
+  51 :  2F3;
+  52 :  2F6;
+  53 :  2F9;
+  54 :  2FC;
+  55 :  2FE;
+  56 :  301;
+  57 :  304;
+  58 :  306;
+  59 :  309;
+  5A :  30C;
+  5B :  30E;
+  5C :  311;
+  5D :  314;
+  5E :  316;
+  5F :  319;
+  60 :  31C;
+  61 :  31E;
+  62 :  321;
+  63 :  323;
+  64 :  326;
+  65 :  329;
+  66 :  32B;
+  67 :  32E;
+  68 :  330;
+  69 :  333;
+  6A :  335;
+  6B :  338;
+  6C :  33A;
+  6D :  33D;
+  6E :  33F;
+  6F :  342;
+  70 :  344;
+  71 :  346;
+  72 :  349;
+  73 :  34B;
+  74 :  34E;
+  75 :  350;
+  76 :  352;
+  77 :  355;
+  78 :  357;
+  79 :  359;
+  7A :  35C;
+  7B :  35E;
+  7C :  360;
+  7D :  362;
+  7E :  365;
+  7F :  367;
+  80 :  369;
+  81 :  36B;
+  82 :  36E;
+  83 :  370;
+  84 :  372;
+  85 :  374;
+  86 :  376;
+  87 :  378;
+  88 :  37A;
+  89 :  37D;
+  8A :  37F;
+  8B :  381;
+  8C :  383;
+  8D :  385;
+  8E :  387;
+  8F :  389;
+  90 :  38B;
+  91 :  38D;
+  92 :  38F;
+  93 :  391;
+  94 :  393;
+  95 :  395;
+  96 :  397;
+  97 :  398;
+  98 :  39A;
+  99 :  39C;
+  9A :  39E;
+  9B :  3A0;
+  9C :  3A2;
+  9D :  3A3;
+  9E :  3A5;
+  9F :  3A7;
+  A0 :  3A9;
+  A1 :  3AB;
+  A2 :  3AC;
+  A3 :  3AE;
+  A4 :  3B0;
+  A5 :  3B1;
+  A6 :  3B3;
+  A7 :  3B5;
+  A8 :  3B6;
+  A9 :  3B8;
+  AA :  3B9;
+  AB :  3BB;
+  AC :  3BD;
+  AD :  3BE;
+  AE :  3C0;
+  AF :  3C1;
+  B0 :  3C3;
+  B1 :  3C4;
+  B2 :  3C6;
+  B3 :  3C7;
+  B4 :  3C8;
+  B5 :  3CA;
+  B6 :  3CB;
+  B7 :  3CD;
+  B8 :  3CE;
+  B9 :  3CF;
+  BA :  3D1;
+  BB :  3D2;
+  BC :  3D3;
+  BD :  3D4;
+  BE :  3D6;
+  BF :  3D7;
+  C0 :  3D8;
+  C1 :  3D9;
+  C2 :  3DA;
+  C3 :  3DC;
+  C4 :  3DD;
+  C5 :  3DE;
+  C6 :  3DF;
+  C7 :  3E0;
+  C8 :  3E1;
+  C9 :  3E2;
+  CA :  3E3;
+  CB :  3E4;
+  CC :  3E5;
+  CD :  3E6;
+  CE :  3E7;
+  CF :  3E8;
+  D0 :  3E9;
+  D1 :  3EA;
+  D2 :  3EB;
+  D3 :  3EC;
+  D4 :  3EC;
+  D5 :  3ED;
+  D6 :  3EE;
+  D7 :  3EF;
+  D8 :  3F0;
+  D9 :  3F0;
+  DA :  3F1;
+  DB :  3F2;
+  DC :  3F3;
+  DD :  3F3;
+  DE :  3F4;
+  DF :  3F5;
+  E0 :  3F5;
+  E1 :  3F6;
+  E2 :  3F6;
+  E3 :  3F7;
+  E4 :  3F7;
+  E5 :  3F8;
+  E6 :  3F9;
+  E7 :  3F9;
+  E8 :  3F9;
+  E9 :  3FA;
+  EA :  3FA;
+  EB :  3FB;
+  EC :  3FB;
+  ED :  3FC;
+  EE :  3FC;
+  EF :  3FC;
+  F0 :  3FD;
+  F1 :  3FD;
+  F2 :  3FD;
+  F3 :  3FD;
+  F4 :  3FE;
+  F5 :  3FE;
+  F6 :  3FE;
+  F7 :  3FE;
+  F8 :  3FE;
+  F9 :  3FF;
+  FA :  3FF;
+  FB :  3FF;
+  FC :  3FF;
+  FD :  3FF;
+  FE :  3FF;
+  FF :  3FF;
+ 100 :  3FF;
+ 101 :  3FF;
+ 102 :  3FF;
+ 103 :  3FF;
+ 104 :  3FF;
+ 105 :  3FF;
+ 106 :  3FF;
+ 107 :  3FF;
+ 108 :  3FE;
+ 109 :  3FE;
+ 10A :  3FE;
+ 10B :  3FE;
+ 10C :  3FE;
+ 10D :  3FD;
+ 10E :  3FD;
+ 10F :  3FD;
+ 110 :  3FD;
+ 111 :  3FC;
+ 112 :  3FC;
+ 113 :  3FC;
+ 114 :  3FB;
+ 115 :  3FB;
+ 116 :  3FA;
+ 117 :  3FA;
+ 118 :  3F9;
+ 119 :  3F9;
+ 11A :  3F9;
+ 11B :  3F8;
+ 11C :  3F7;
+ 11D :  3F7;
+ 11E :  3F6;
+ 11F :  3F6;
+ 120 :  3F5;
+ 121 :  3F5;
+ 122 :  3F4;
+ 123 :  3F3;
+ 124 :  3F3;
+ 125 :  3F2;
+ 126 :  3F1;
+ 127 :  3F0;
+ 128 :  3F0;
+ 129 :  3EF;
+ 12A :  3EE;
+ 12B :  3ED;
+ 12C :  3EC;
+ 12D :  3EC;
+ 12E :  3EB;
+ 12F :  3EA;
+ 130 :  3E9;
+ 131 :  3E8;
+ 132 :  3E7;
+ 133 :  3E6;
+ 134 :  3E5;
+ 135 :  3E4;
+ 136 :  3E3;
+ 137 :  3E2;
+ 138 :  3E1;
+ 139 :  3E0;
+ 13A :  3DF;
+ 13B :  3DE;
+ 13C :  3DD;
+ 13D :  3DC;
+ 13E :  3DA;
+ 13F :  3D9;
+ 140 :  3D8;
+ 141 :  3D7;
+ 142 :  3D6;
+ 143 :  3D4;
+ 144 :  3D3;
+ 145 :  3D2;
+ 146 :  3D1;
+ 147 :  3CF;
+ 148 :  3CE;
+ 149 :  3CD;
+ 14A :  3CB;
+ 14B :  3CA;
+ 14C :  3C8;
+ 14D :  3C7;
+ 14E :  3C6;
+ 14F :  3C4;
+ 150 :  3C3;
+ 151 :  3C1;
+ 152 :  3C0;
+ 153 :  3BE;
+ 154 :  3BD;
+ 155 :  3BB;
+ 156 :  3B9;
+ 157 :  3B8;
+ 158 :  3B6;
+ 159 :  3B5;
+ 15A :  3B3;
+ 15B :  3B1;
+ 15C :  3B0;
+ 15D :  3AE;
+ 15E :  3AC;
+ 15F :  3AB;
+ 160 :  3A9;
+ 161 :  3A7;
+ 162 :  3A5;
+ 163 :  3A3;
+ 164 :  3A2;
+ 165 :  3A0;
+ 166 :  39E;
+ 167 :  39C;
+ 168 :  39A;
+ 169 :  398;
+ 16A :  397;
+ 16B :  395;
+ 16C :  393;
+ 16D :  391;
+ 16E :  38F;
+ 16F :  38D;
+ 170 :  38B;
+ 171 :  389;
+ 172 :  387;
+ 173 :  385;
+ 174 :  383;
+ 175 :  381;
+ 176 :  37F;
+ 177 :  37D;
+ 178 :  37A;
+ 179 :  378;
+ 17A :  376;
+ 17B :  374;
+ 17C :  372;
+ 17D :  370;
+ 17E :  36E;
+ 17F :  36B;
+ 180 :  369;
+ 181 :  367;
+ 182 :  365;
+ 183 :  362;
+ 184 :  360;
+ 185 :  35E;
+ 186 :  35C;
+ 187 :  359;
+ 188 :  357;
+ 189 :  355;
+ 18A :  352;
+ 18B :  350;
+ 18C :  34E;
+ 18D :  34B;
+ 18E :  349;
+ 18F :  346;
+ 190 :  344;
+ 191 :  342;
+ 192 :  33F;
+ 193 :  33D;
+ 194 :  33A;
+ 195 :  338;
+ 196 :  335;
+ 197 :  333;
+ 198 :  330;
+ 199 :  32E;
+ 19A :  32B;
+ 19B :  329;
+ 19C :  326;
+ 19D :  323;
+ 19E :  321;
+ 19F :  31E;
+ 1A0 :  31C;
+ 1A1 :  319;
+ 1A2 :  316;
+ 1A3 :  314;
+ 1A4 :  311;
+ 1A5 :  30E;
+ 1A6 :  30C;
+ 1A7 :  309;
+ 1A8 :  306;
+ 1A9 :  304;
+ 1AA :  301;
+ 1AB :  2FE;
+ 1AC :  2FC;
+ 1AD :  2F9;
+ 1AE :  2F6;
+ 1AF :  2F3;
+ 1B0 :  2F1;
+ 1B1 :  2EE;
+ 1B2 :  2EB;
+ 1B3 :  2E8;
+ 1B4 :  2E5;
+ 1B5 :  2E3;
+ 1B6 :  2E0;
+ 1B7 :  2DD;
+ 1B8 :  2DA;
+ 1B9 :  2D7;
+ 1BA :  2D5;
+ 1BB :  2D2;
+ 1BC :  2CF;
+ 1BD :  2CC;
+ 1BE :  2C9;
+ 1BF :  2C6;
+ 1C0 :  2C3;
+ 1C1 :  2C0;
+ 1C2 :  2BD;
+ 1C3 :  2BB;
+ 1C4 :  2B8;
+ 1C5 :  2B5;
+ 1C6 :  2B2;
+ 1C7 :  2AF;
+ 1C8 :  2AC;
+ 1C9 :  2A9;
+ 1CA :  2A6;
+ 1CB :  2A3;
+ 1CC :  2A0;
+ 1CD :  29D;
+ 1CE :  29A;
+ 1CF :  297;
+ 1D0 :  294;
+ 1D1 :  291;
+ 1D2 :  28E;
+ 1D3 :  28B;
+ 1D4 :  288;
+ 1D5 :  285;
+ 1D6 :  282;
+ 1D7 :  27F;
+ 1D8 :  27C;
+ 1D9 :  279;
+ 1DA :  276;
+ 1DB :  273;
+ 1DC :  270;
+ 1DD :  26D;
+ 1DE :  269;
+ 1DF :  266;
+ 1E0 :  263;
+ 1E1 :  260;
+ 1E2 :  25D;
+ 1E3 :  25A;
+ 1E4 :  257;
+ 1E5 :  254;
+ 1E6 :  251;
+ 1E7 :  24E;
+ 1E8 :  24B;
+ 1E9 :  247;
+ 1EA :  244;
+ 1EB :  241;
+ 1EC :  23E;
+ 1ED :  23B;
+ 1EE :  238;
+ 1EF :  235;
+ 1F0 :  232;
+ 1F1 :  22F;
+ 1F2 :  22B;
+ 1F3 :  228;
+ 1F4 :  225;
+ 1F5 :  222;
+ 1F6 :  21F;
+ 1F7 :  21C;
+ 1F8 :  219;
+ 1F9 :  215;
+ 1FA :  212;
+ 1FB :  20F;
+ 1FC :  20C;
+ 1FD :  209;
+ 1FE :  206;
+ 1FF :  203;
+ 200 :  200;
+ 201 :  1FC;
+ 202 :  1F9;
+ 203 :  1F6;
+ 204 :  1F3;
+ 205 :  1F0;
+ 206 :  1ED;
+ 207 :  1EA;
+ 208 :  1E6;
+ 209 :  1E3;
+ 20A :  1E0;
+ 20B :  1DD;
+ 20C :  1DA;
+ 20D :  1D7;
+ 20E :  1D4;
+ 20F :  1D0;
+ 210 :  1CD;
+ 211 :  1CA;
+ 212 :  1C7;
+ 213 :  1C4;
+ 214 :  1C1;
+ 215 :  1BE;
+ 216 :  1BB;
+ 217 :  1B8;
+ 218 :  1B4;
+ 219 :  1B1;
+ 21A :  1AE;
+ 21B :  1AB;
+ 21C :  1A8;
+ 21D :  1A5;
+ 21E :  1A2;
+ 21F :  19F;
+ 220 :  19C;
+ 221 :  199;
+ 222 :  196;
+ 223 :  192;
+ 224 :  18F;
+ 225 :  18C;
+ 226 :  189;
+ 227 :  186;
+ 228 :  183;
+ 229 :  180;
+ 22A :  17D;
+ 22B :  17A;
+ 22C :  177;
+ 22D :  174;
+ 22E :  171;
+ 22F :  16E;
+ 230 :  16B;
+ 231 :  168;
+ 232 :  165;
+ 233 :  162;
+ 234 :  15F;
+ 235 :  15C;
+ 236 :  159;
+ 237 :  156;
+ 238 :  153;
+ 239 :  150;
+ 23A :  14D;
+ 23B :  14A;
+ 23C :  147;
+ 23D :  144;
+ 23E :  142;
+ 23F :  13F;
+ 240 :  13C;
+ 241 :  139;
+ 242 :  136;
+ 243 :  133;
+ 244 :  130;
+ 245 :  12D;
+ 246 :  12A;
+ 247 :  128;
+ 248 :  125;
+ 249 :  122;
+ 24A :  11F;
+ 24B :  11C;
+ 24C :  11A;
+ 24D :  117;
+ 24E :  114;
+ 24F :  111;
+ 250 :  10E;
+ 251 :  10C;
+ 252 :  109;
+ 253 :  106;
+ 254 :  103;
+ 255 :  101;
+ 256 :   FE;
+ 257 :   FB;
+ 258 :   F9;
+ 259 :   F6;
+ 25A :   F3;
+ 25B :   F1;
+ 25C :   EE;
+ 25D :   EB;
+ 25E :   E9;
+ 25F :   E6;
+ 260 :   E3;
+ 261 :   E1;
+ 262 :   DE;
+ 263 :   DC;
+ 264 :   D9;
+ 265 :   D6;
+ 266 :   D4;
+ 267 :   D1;
+ 268 :   CF;
+ 269 :   CC;
+ 26A :   CA;
+ 26B :   C7;
+ 26C :   C5;
+ 26D :   C2;
+ 26E :   C0;
+ 26F :   BD;
+ 270 :   BB;
+ 271 :   B9;
+ 272 :   B6;
+ 273 :   B4;
+ 274 :   B1;
+ 275 :   AF;
+ 276 :   AD;
+ 277 :   AA;
+ 278 :   A8;
+ 279 :   A6;
+ 27A :   A3;
+ 27B :   A1;
+ 27C :   9F;
+ 27D :   9D;
+ 27E :   9A;
+ 27F :   98;
+ 280 :   96;
+ 281 :   94;
+ 282 :   91;
+ 283 :   8F;
+ 284 :   8D;
+ 285 :   8B;
+ 286 :   89;
+ 287 :   87;
+ 288 :   85;
+ 289 :   82;
+ 28A :   80;
+ 28B :   7E;
+ 28C :   7C;
+ 28D :   7A;
+ 28E :   78;
+ 28F :   76;
+ 290 :   74;
+ 291 :   72;
+ 292 :   70;
+ 293 :   6E;
+ 294 :   6C;
+ 295 :   6A;
+ 296 :   68;
+ 297 :   67;
+ 298 :   65;
+ 299 :   63;
+ 29A :   61;
+ 29B :   5F;
+ 29C :   5D;
+ 29D :   5C;
+ 29E :   5A;
+ 29F :   58;
+ 2A0 :   56;
+ 2A1 :   54;
+ 2A2 :   53;
+ 2A3 :   51;
+ 2A4 :   4F;
+ 2A5 :   4E;
+ 2A6 :   4C;
+ 2A7 :   4A;
+ 2A8 :   49;
+ 2A9 :   47;
+ 2AA :   46;
+ 2AB :   44;
+ 2AC :   42;
+ 2AD :   41;
+ 2AE :   3F;
+ 2AF :   3E;
+ 2B0 :   3C;
+ 2B1 :   3B;
+ 2B2 :   39;
+ 2B3 :   38;
+ 2B4 :   37;
+ 2B5 :   35;
+ 2B6 :   34;
+ 2B7 :   32;
+ 2B8 :   31;
+ 2B9 :   30;
+ 2BA :   2E;
+ 2BB :   2D;
+ 2BC :   2C;
+ 2BD :   2B;
+ 2BE :   29;
+ 2BF :   28;
+ 2C0 :   27;
+ 2C1 :   26;
+ 2C2 :   25;
+ 2C3 :   23;
+ 2C4 :   22;
+ 2C5 :   21;
+ 2C6 :   20;
+ 2C7 :   1F;
+ 2C8 :   1E;
+ 2C9 :   1D;
+ 2CA :   1C;
+ 2CB :   1B;
+ 2CC :   1A;
+ 2CD :   19;
+ 2CE :   18;
+ 2CF :   17;
+ 2D0 :   16;
+ 2D1 :   15;
+ 2D2 :   14;
+ 2D3 :   13;
+ 2D4 :   13;
+ 2D5 :   12;
+ 2D6 :   11;
+ 2D7 :   10;
+ 2D8 :    F;
+ 2D9 :    F;
+ 2DA :    E;
+ 2DB :    D;
+ 2DC :    C;
+ 2DD :    C;
+ 2DE :    B;
+ 2DF :    A;
+ 2E0 :    A;
+ 2E1 :    9;
+ 2E2 :    9;
+ 2E3 :    8;
+ 2E4 :    8;
+ 2E5 :    7;
+ 2E6 :    6;
+ 2E7 :    6;
+ 2E8 :    6;
+ 2E9 :    5;
+ 2EA :    5;
+ 2EB :    4;
+ 2EC :    4;
+ 2ED :    3;
+ 2EE :    3;
+ 2EF :    3;
+ 2F0 :    2;
+ 2F1 :    2;
+ 2F2 :    2;
+ 2F3 :    2;
+ 2F4 :    1;
+ 2F5 :    1;
+ 2F6 :    1;
+ 2F7 :    1;
+ 2F8 :    1;
+ 2F9 :    0;
+ 2FA :    0;
+ 2FB :    0;
+ 2FC :    0;
+ 2FD :    0;
+ 2FE :    0;
+ 2FF :    0;
+ 300 :    0;
+ 301 :    0;
+ 302 :    0;
+ 303 :    0;
+ 304 :    0;
+ 305 :    0;
+ 306 :    0;
+ 307 :    0;
+ 308 :    1;
+ 309 :    1;
+ 30A :    1;
+ 30B :    1;
+ 30C :    1;
+ 30D :    2;
+ 30E :    2;
+ 30F :    2;
+ 310 :    2;
+ 311 :    3;
+ 312 :    3;
+ 313 :    3;
+ 314 :    4;
+ 315 :    4;
+ 316 :    5;
+ 317 :    5;
+ 318 :    6;
+ 319 :    6;
+ 31A :    6;
+ 31B :    7;
+ 31C :    8;
+ 31D :    8;
+ 31E :    9;
+ 31F :    9;
+ 320 :    A;
+ 321 :    A;
+ 322 :    B;
+ 323 :    C;
+ 324 :    C;
+ 325 :    D;
+ 326 :    E;
+ 327 :    F;
+ 328 :    F;
+ 329 :   10;
+ 32A :   11;
+ 32B :   12;
+ 32C :   13;
+ 32D :   13;
+ 32E :   14;
+ 32F :   15;
+ 330 :   16;
+ 331 :   17;
+ 332 :   18;
+ 333 :   19;
+ 334 :   1A;
+ 335 :   1B;
+ 336 :   1C;
+ 337 :   1D;
+ 338 :   1E;
+ 339 :   1F;
+ 33A :   20;
+ 33B :   21;
+ 33C :   22;
+ 33D :   23;
+ 33E :   25;
+ 33F :   26;
+ 340 :   27;
+ 341 :   28;
+ 342 :   29;
+ 343 :   2B;
+ 344 :   2C;
+ 345 :   2D;
+ 346 :   2E;
+ 347 :   30;
+ 348 :   31;
+ 349 :   32;
+ 34A :   34;
+ 34B :   35;
+ 34C :   37;
+ 34D :   38;
+ 34E :   39;
+ 34F :   3B;
+ 350 :   3C;
+ 351 :   3E;
+ 352 :   3F;
+ 353 :   41;
+ 354 :   42;
+ 355 :   44;
+ 356 :   46;
+ 357 :   47;
+ 358 :   49;
+ 359 :   4A;
+ 35A :   4C;
+ 35B :   4E;
+ 35C :   4F;
+ 35D :   51;
+ 35E :   53;
+ 35F :   54;
+ 360 :   56;
+ 361 :   58;
+ 362 :   5A;
+ 363 :   5C;
+ 364 :   5D;
+ 365 :   5F;
+ 366 :   61;
+ 367 :   63;
+ 368 :   65;
+ 369 :   67;
+ 36A :   68;
+ 36B :   6A;
+ 36C :   6C;
+ 36D :   6E;
+ 36E :   70;
+ 36F :   72;
+ 370 :   74;
+ 371 :   76;
+ 372 :   78;
+ 373 :   7A;
+ 374 :   7C;
+ 375 :   7E;
+ 376 :   80;
+ 377 :   82;
+ 378 :   85;
+ 379 :   87;
+ 37A :   89;
+ 37B :   8B;
+ 37C :   8D;
+ 37D :   8F;
+ 37E :   91;
+ 37F :   94;
+ 380 :   96;
+ 381 :   98;
+ 382 :   9A;
+ 383 :   9D;
+ 384 :   9F;
+ 385 :   A1;
+ 386 :   A3;
+ 387 :   A6;
+ 388 :   A8;
+ 389 :   AA;
+ 38A :   AD;
+ 38B :   AF;
+ 38C :   B1;
+ 38D :   B4;
+ 38E :   B6;
+ 38F :   B9;
+ 390 :   BB;
+ 391 :   BD;
+ 392 :   C0;
+ 393 :   C2;
+ 394 :   C5;
+ 395 :   C7;
+ 396 :   CA;
+ 397 :   CC;
+ 398 :   CF;
+ 399 :   D1;
+ 39A :   D4;
+ 39B :   D6;
+ 39C :   D9;
+ 39D :   DC;
+ 39E :   DE;
+ 39F :   E1;
+ 3A0 :   E3;
+ 3A1 :   E6;
+ 3A2 :   E9;
+ 3A3 :   EB;
+ 3A4 :   EE;
+ 3A5 :   F1;
+ 3A6 :   F3;
+ 3A7 :   F6;
+ 3A8 :   F9;
+ 3A9 :   FB;
+ 3AA :   FE;
+ 3AB :  101;
+ 3AC :  103;
+ 3AD :  106;
+ 3AE :  109;
+ 3AF :  10C;
+ 3B0 :  10E;
+ 3B1 :  111;
+ 3B2 :  114;
+ 3B3 :  117;
+ 3B4 :  11A;
+ 3B5 :  11C;
+ 3B6 :  11F;
+ 3B7 :  122;
+ 3B8 :  125;
+ 3B9 :  128;
+ 3BA :  12A;
+ 3BB :  12D;
+ 3BC :  130;
+ 3BD :  133;
+ 3BE :  136;
+ 3BF :  139;
+ 3C0 :  13C;
+ 3C1 :  13F;
+ 3C2 :  142;
+ 3C3 :  144;
+ 3C4 :  147;
+ 3C5 :  14A;
+ 3C6 :  14D;
+ 3C7 :  150;
+ 3C8 :  153;
+ 3C9 :  156;
+ 3CA :  159;
+ 3CB :  15C;
+ 3CC :  15F;
+ 3CD :  162;
+ 3CE :  165;
+ 3CF :  168;
+ 3D0 :  16B;
+ 3D1 :  16E;
+ 3D2 :  171;
+ 3D3 :  174;
+ 3D4 :  177;
+ 3D5 :  17A;
+ 3D6 :  17D;
+ 3D7 :  180;
+ 3D8 :  183;
+ 3D9 :  186;
+ 3DA :  189;
+ 3DB :  18C;
+ 3DC :  18F;
+ 3DD :  192;
+ 3DE :  196;
+ 3DF :  199;
+ 3E0 :  19C;
+ 3E1 :  19F;
+ 3E2 :  1A2;
+ 3E3 :  1A5;
+ 3E4 :  1A8;
+ 3E5 :  1AB;
+ 3E6 :  1AE;
+ 3E7 :  1B1;
+ 3E8 :  1B4;
+ 3E9 :  1B8;
+ 3EA :  1BB;
+ 3EB :  1BE;
+ 3EC :  1C1;
+ 3ED :  1C4;
+ 3EE :  1C7;
+ 3EF :  1CA;
+ 3F0 :  1CD;
+ 3F1 :  1D0;
+ 3F2 :  1D4;
+ 3F3 :  1D7;
+ 3F4 :  1DA;
+ 3F5 :  1DD;
+ 3F6 :  1E0;
+ 3F7 :  1E3;
+ 3F8 :  1E6;
+ 3F9 :  1EA;
+ 3FA :  1ED;
+ 3FB :  1F0;
+ 3FC :  1F3;
+ 3FD :  1F6;
+ 3FE :  1F9;
+ 3FF :  1FC;
+END
diff --git a/part_3/ex12/sin_gen_scripts/rom_data.mif b/part_3/ex12/sin_gen_scripts/rom_data.mif
index a688b6f..45464a9 100755
--- a/part_3/ex12/sin_gen_scripts/rom_data.mif
+++ b/part_3/ex12/sin_gen_scripts/rom_data.mif
@@ -1,1032 +1,1032 @@
--- ROM Initialization file
-WIDTH = 10;
-DEPTH = 1024;
-ADDRESS_RADIX = HEX;
-DATA_RADIX = HEX;
-CONTENT
-BEGIN
-   0 :  200;
-   1 :  203;
-   2 :  206;
-   3 :  209;
-   4 :  20C;
-   5 :  20F;
-   6 :  212;
-   7 :  215;
-   8 :  219;
-   9 :  21C;
-   A :  21F;
-   B :  222;
-   C :  225;
-   D :  228;
-   E :  22B;
-   F :  22F;
-  10 :  232;
-  11 :  235;
-  12 :  238;
-  13 :  23B;
-  14 :  23E;
-  15 :  241;
-  16 :  244;
-  17 :  247;
-  18 :  24B;
-  19 :  24E;
-  1A :  251;
-  1B :  254;
-  1C :  257;
-  1D :  25A;
-  1E :  25D;
-  1F :  260;
-  20 :  263;
-  21 :  266;
-  22 :  269;
-  23 :  26D;
-  24 :  270;
-  25 :  273;
-  26 :  276;
-  27 :  279;
-  28 :  27C;
-  29 :  27F;
-  2A :  282;
-  2B :  285;
-  2C :  288;
-  2D :  28B;
-  2E :  28E;
-  2F :  291;
-  30 :  294;
-  31 :  297;
-  32 :  29A;
-  33 :  29D;
-  34 :  2A0;
-  35 :  2A3;
-  36 :  2A6;
-  37 :  2A9;
-  38 :  2AC;
-  39 :  2AF;
-  3A :  2B2;
-  3B :  2B5;
-  3C :  2B8;
-  3D :  2BB;
-  3E :  2BD;
-  3F :  2C0;
-  40 :  2C3;
-  41 :  2C6;
-  42 :  2C9;
-  43 :  2CC;
-  44 :  2CF;
-  45 :  2D2;
-  46 :  2D5;
-  47 :  2D7;
-  48 :  2DA;
-  49 :  2DD;
-  4A :  2E0;
-  4B :  2E3;
-  4C :  2E5;
-  4D :  2E8;
-  4E :  2EB;
-  4F :  2EE;
-  50 :  2F1;
-  51 :  2F3;
-  52 :  2F6;
-  53 :  2F9;
-  54 :  2FC;
-  55 :  2FE;
-  56 :  301;
-  57 :  304;
-  58 :  306;
-  59 :  309;
-  5A :  30C;
-  5B :  30E;
-  5C :  311;
-  5D :  314;
-  5E :  316;
-  5F :  319;
-  60 :  31C;
-  61 :  31E;
-  62 :  321;
-  63 :  323;
-  64 :  326;
-  65 :  329;
-  66 :  32B;
-  67 :  32E;
-  68 :  330;
-  69 :  333;
-  6A :  335;
-  6B :  338;
-  6C :  33A;
-  6D :  33D;
-  6E :  33F;
-  6F :  342;
-  70 :  344;
-  71 :  346;
-  72 :  349;
-  73 :  34B;
-  74 :  34E;
-  75 :  350;
-  76 :  352;
-  77 :  355;
-  78 :  357;
-  79 :  359;
-  7A :  35C;
-  7B :  35E;
-  7C :  360;
-  7D :  362;
-  7E :  365;
-  7F :  367;
-  80 :  369;
-  81 :  36B;
-  82 :  36E;
-  83 :  370;
-  84 :  372;
-  85 :  374;
-  86 :  376;
-  87 :  378;
-  88 :  37A;
-  89 :  37D;
-  8A :  37F;
-  8B :  381;
-  8C :  383;
-  8D :  385;
-  8E :  387;
-  8F :  389;
-  90 :  38B;
-  91 :  38D;
-  92 :  38F;
-  93 :  391;
-  94 :  393;
-  95 :  395;
-  96 :  397;
-  97 :  398;
-  98 :  39A;
-  99 :  39C;
-  9A :  39E;
-  9B :  3A0;
-  9C :  3A2;
-  9D :  3A3;
-  9E :  3A5;
-  9F :  3A7;
-  A0 :  3A9;
-  A1 :  3AB;
-  A2 :  3AC;
-  A3 :  3AE;
-  A4 :  3B0;
-  A5 :  3B1;
-  A6 :  3B3;
-  A7 :  3B5;
-  A8 :  3B6;
-  A9 :  3B8;
-  AA :  3B9;
-  AB :  3BB;
-  AC :  3BD;
-  AD :  3BE;
-  AE :  3C0;
-  AF :  3C1;
-  B0 :  3C3;
-  B1 :  3C4;
-  B2 :  3C6;
-  B3 :  3C7;
-  B4 :  3C8;
-  B5 :  3CA;
-  B6 :  3CB;
-  B7 :  3CD;
-  B8 :  3CE;
-  B9 :  3CF;
-  BA :  3D1;
-  BB :  3D2;
-  BC :  3D3;
-  BD :  3D4;
-  BE :  3D6;
-  BF :  3D7;
-  C0 :  3D8;
-  C1 :  3D9;
-  C2 :  3DA;
-  C3 :  3DC;
-  C4 :  3DD;
-  C5 :  3DE;
-  C6 :  3DF;
-  C7 :  3E0;
-  C8 :  3E1;
-  C9 :  3E2;
-  CA :  3E3;
-  CB :  3E4;
-  CC :  3E5;
-  CD :  3E6;
-  CE :  3E7;
-  CF :  3E8;
-  D0 :  3E9;
-  D1 :  3EA;
-  D2 :  3EB;
-  D3 :  3EC;
-  D4 :  3EC;
-  D5 :  3ED;
-  D6 :  3EE;
-  D7 :  3EF;
-  D8 :  3F0;
-  D9 :  3F0;
-  DA :  3F1;
-  DB :  3F2;
-  DC :  3F3;
-  DD :  3F3;
-  DE :  3F4;
-  DF :  3F5;
-  E0 :  3F5;
-  E1 :  3F6;
-  E2 :  3F6;
-  E3 :  3F7;
-  E4 :  3F7;
-  E5 :  3F8;
-  E6 :  3F9;
-  E7 :  3F9;
-  E8 :  3F9;
-  E9 :  3FA;
-  EA :  3FA;
-  EB :  3FB;
-  EC :  3FB;
-  ED :  3FC;
-  EE :  3FC;
-  EF :  3FC;
-  F0 :  3FD;
-  F1 :  3FD;
-  F2 :  3FD;
-  F3 :  3FD;
-  F4 :  3FE;
-  F5 :  3FE;
-  F6 :  3FE;
-  F7 :  3FE;
-  F8 :  3FE;
-  F9 :  3FF;
-  FA :  3FF;
-  FB :  3FF;
-  FC :  3FF;
-  FD :  3FF;
-  FE :  3FF;
-  FF :  3FF;
- 100 :  3FF;
- 101 :  3FF;
- 102 :  3FF;
- 103 :  3FF;
- 104 :  3FF;
- 105 :  3FF;
- 106 :  3FF;
- 107 :  3FF;
- 108 :  3FE;
- 109 :  3FE;
- 10A :  3FE;
- 10B :  3FE;
- 10C :  3FE;
- 10D :  3FD;
- 10E :  3FD;
- 10F :  3FD;
- 110 :  3FD;
- 111 :  3FC;
- 112 :  3FC;
- 113 :  3FC;
- 114 :  3FB;
- 115 :  3FB;
- 116 :  3FA;
- 117 :  3FA;
- 118 :  3F9;
- 119 :  3F9;
- 11A :  3F9;
- 11B :  3F8;
- 11C :  3F7;
- 11D :  3F7;
- 11E :  3F6;
- 11F :  3F6;
- 120 :  3F5;
- 121 :  3F5;
- 122 :  3F4;
- 123 :  3F3;
- 124 :  3F3;
- 125 :  3F2;
- 126 :  3F1;
- 127 :  3F0;
- 128 :  3F0;
- 129 :  3EF;
- 12A :  3EE;
- 12B :  3ED;
- 12C :  3EC;
- 12D :  3EC;
- 12E :  3EB;
- 12F :  3EA;
- 130 :  3E9;
- 131 :  3E8;
- 132 :  3E7;
- 133 :  3E6;
- 134 :  3E5;
- 135 :  3E4;
- 136 :  3E3;
- 137 :  3E2;
- 138 :  3E1;
- 139 :  3E0;
- 13A :  3DF;
- 13B :  3DE;
- 13C :  3DD;
- 13D :  3DC;
- 13E :  3DA;
- 13F :  3D9;
- 140 :  3D8;
- 141 :  3D7;
- 142 :  3D6;
- 143 :  3D4;
- 144 :  3D3;
- 145 :  3D2;
- 146 :  3D1;
- 147 :  3CF;
- 148 :  3CE;
- 149 :  3CD;
- 14A :  3CB;
- 14B :  3CA;
- 14C :  3C8;
- 14D :  3C7;
- 14E :  3C6;
- 14F :  3C4;
- 150 :  3C3;
- 151 :  3C1;
- 152 :  3C0;
- 153 :  3BE;
- 154 :  3BD;
- 155 :  3BB;
- 156 :  3B9;
- 157 :  3B8;
- 158 :  3B6;
- 159 :  3B5;
- 15A :  3B3;
- 15B :  3B1;
- 15C :  3B0;
- 15D :  3AE;
- 15E :  3AC;
- 15F :  3AB;
- 160 :  3A9;
- 161 :  3A7;
- 162 :  3A5;
- 163 :  3A3;
- 164 :  3A2;
- 165 :  3A0;
- 166 :  39E;
- 167 :  39C;
- 168 :  39A;
- 169 :  398;
- 16A :  397;
- 16B :  395;
- 16C :  393;
- 16D :  391;
- 16E :  38F;
- 16F :  38D;
- 170 :  38B;
- 171 :  389;
- 172 :  387;
- 173 :  385;
- 174 :  383;
- 175 :  381;
- 176 :  37F;
- 177 :  37D;
- 178 :  37A;
- 179 :  378;
- 17A :  376;
- 17B :  374;
- 17C :  372;
- 17D :  370;
- 17E :  36E;
- 17F :  36B;
- 180 :  369;
- 181 :  367;
- 182 :  365;
- 183 :  362;
- 184 :  360;
- 185 :  35E;
- 186 :  35C;
- 187 :  359;
- 188 :  357;
- 189 :  355;
- 18A :  352;
- 18B :  350;
- 18C :  34E;
- 18D :  34B;
- 18E :  349;
- 18F :  346;
- 190 :  344;
- 191 :  342;
- 192 :  33F;
- 193 :  33D;
- 194 :  33A;
- 195 :  338;
- 196 :  335;
- 197 :  333;
- 198 :  330;
- 199 :  32E;
- 19A :  32B;
- 19B :  329;
- 19C :  326;
- 19D :  323;
- 19E :  321;
- 19F :  31E;
- 1A0 :  31C;
- 1A1 :  319;
- 1A2 :  316;
- 1A3 :  314;
- 1A4 :  311;
- 1A5 :  30E;
- 1A6 :  30C;
- 1A7 :  309;
- 1A8 :  306;
- 1A9 :  304;
- 1AA :  301;
- 1AB :  2FE;
- 1AC :  2FC;
- 1AD :  2F9;
- 1AE :  2F6;
- 1AF :  2F3;
- 1B0 :  2F1;
- 1B1 :  2EE;
- 1B2 :  2EB;
- 1B3 :  2E8;
- 1B4 :  2E5;
- 1B5 :  2E3;
- 1B6 :  2E0;
- 1B7 :  2DD;
- 1B8 :  2DA;
- 1B9 :  2D7;
- 1BA :  2D5;
- 1BB :  2D2;
- 1BC :  2CF;
- 1BD :  2CC;
- 1BE :  2C9;
- 1BF :  2C6;
- 1C0 :  2C3;
- 1C1 :  2C0;
- 1C2 :  2BD;
- 1C3 :  2BB;
- 1C4 :  2B8;
- 1C5 :  2B5;
- 1C6 :  2B2;
- 1C7 :  2AF;
- 1C8 :  2AC;
- 1C9 :  2A9;
- 1CA :  2A6;
- 1CB :  2A3;
- 1CC :  2A0;
- 1CD :  29D;
- 1CE :  29A;
- 1CF :  297;
- 1D0 :  294;
- 1D1 :  291;
- 1D2 :  28E;
- 1D3 :  28B;
- 1D4 :  288;
- 1D5 :  285;
- 1D6 :  282;
- 1D7 :  27F;
- 1D8 :  27C;
- 1D9 :  279;
- 1DA :  276;
- 1DB :  273;
- 1DC :  270;
- 1DD :  26D;
- 1DE :  269;
- 1DF :  266;
- 1E0 :  263;
- 1E1 :  260;
- 1E2 :  25D;
- 1E3 :  25A;
- 1E4 :  257;
- 1E5 :  254;
- 1E6 :  251;
- 1E7 :  24E;
- 1E8 :  24B;
- 1E9 :  247;
- 1EA :  244;
- 1EB :  241;
- 1EC :  23E;
- 1ED :  23B;
- 1EE :  238;
- 1EF :  235;
- 1F0 :  232;
- 1F1 :  22F;
- 1F2 :  22B;
- 1F3 :  228;
- 1F4 :  225;
- 1F5 :  222;
- 1F6 :  21F;
- 1F7 :  21C;
- 1F8 :  219;
- 1F9 :  215;
- 1FA :  212;
- 1FB :  20F;
- 1FC :  20C;
- 1FD :  209;
- 1FE :  206;
- 1FF :  203;
- 200 :  200;
- 201 :  1FC;
- 202 :  1F9;
- 203 :  1F6;
- 204 :  1F3;
- 205 :  1F0;
- 206 :  1ED;
- 207 :  1EA;
- 208 :  1E6;
- 209 :  1E3;
- 20A :  1E0;
- 20B :  1DD;
- 20C :  1DA;
- 20D :  1D7;
- 20E :  1D4;
- 20F :  1D0;
- 210 :  1CD;
- 211 :  1CA;
- 212 :  1C7;
- 213 :  1C4;
- 214 :  1C1;
- 215 :  1BE;
- 216 :  1BB;
- 217 :  1B8;
- 218 :  1B4;
- 219 :  1B1;
- 21A :  1AE;
- 21B :  1AB;
- 21C :  1A8;
- 21D :  1A5;
- 21E :  1A2;
- 21F :  19F;
- 220 :  19C;
- 221 :  199;
- 222 :  196;
- 223 :  192;
- 224 :  18F;
- 225 :  18C;
- 226 :  189;
- 227 :  186;
- 228 :  183;
- 229 :  180;
- 22A :  17D;
- 22B :  17A;
- 22C :  177;
- 22D :  174;
- 22E :  171;
- 22F :  16E;
- 230 :  16B;
- 231 :  168;
- 232 :  165;
- 233 :  162;
- 234 :  15F;
- 235 :  15C;
- 236 :  159;
- 237 :  156;
- 238 :  153;
- 239 :  150;
- 23A :  14D;
- 23B :  14A;
- 23C :  147;
- 23D :  144;
- 23E :  142;
- 23F :  13F;
- 240 :  13C;
- 241 :  139;
- 242 :  136;
- 243 :  133;
- 244 :  130;
- 245 :  12D;
- 246 :  12A;
- 247 :  128;
- 248 :  125;
- 249 :  122;
- 24A :  11F;
- 24B :  11C;
- 24C :  11A;
- 24D :  117;
- 24E :  114;
- 24F :  111;
- 250 :  10E;
- 251 :  10C;
- 252 :  109;
- 253 :  106;
- 254 :  103;
- 255 :  101;
- 256 :   FE;
- 257 :   FB;
- 258 :   F9;
- 259 :   F6;
- 25A :   F3;
- 25B :   F1;
- 25C :   EE;
- 25D :   EB;
- 25E :   E9;
- 25F :   E6;
- 260 :   E3;
- 261 :   E1;
- 262 :   DE;
- 263 :   DC;
- 264 :   D9;
- 265 :   D6;
- 266 :   D4;
- 267 :   D1;
- 268 :   CF;
- 269 :   CC;
- 26A :   CA;
- 26B :   C7;
- 26C :   C5;
- 26D :   C2;
- 26E :   C0;
- 26F :   BD;
- 270 :   BB;
- 271 :   B9;
- 272 :   B6;
- 273 :   B4;
- 274 :   B1;
- 275 :   AF;
- 276 :   AD;
- 277 :   AA;
- 278 :   A8;
- 279 :   A6;
- 27A :   A3;
- 27B :   A1;
- 27C :   9F;
- 27D :   9D;
- 27E :   9A;
- 27F :   98;
- 280 :   96;
- 281 :   94;
- 282 :   91;
- 283 :   8F;
- 284 :   8D;
- 285 :   8B;
- 286 :   89;
- 287 :   87;
- 288 :   85;
- 289 :   82;
- 28A :   80;
- 28B :   7E;
- 28C :   7C;
- 28D :   7A;
- 28E :   78;
- 28F :   76;
- 290 :   74;
- 291 :   72;
- 292 :   70;
- 293 :   6E;
- 294 :   6C;
- 295 :   6A;
- 296 :   68;
- 297 :   67;
- 298 :   65;
- 299 :   63;
- 29A :   61;
- 29B :   5F;
- 29C :   5D;
- 29D :   5C;
- 29E :   5A;
- 29F :   58;
- 2A0 :   56;
- 2A1 :   54;
- 2A2 :   53;
- 2A3 :   51;
- 2A4 :   4F;
- 2A5 :   4E;
- 2A6 :   4C;
- 2A7 :   4A;
- 2A8 :   49;
- 2A9 :   47;
- 2AA :   46;
- 2AB :   44;
- 2AC :   42;
- 2AD :   41;
- 2AE :   3F;
- 2AF :   3E;
- 2B0 :   3C;
- 2B1 :   3B;
- 2B2 :   39;
- 2B3 :   38;
- 2B4 :   37;
- 2B5 :   35;
- 2B6 :   34;
- 2B7 :   32;
- 2B8 :   31;
- 2B9 :   30;
- 2BA :   2E;
- 2BB :   2D;
- 2BC :   2C;
- 2BD :   2B;
- 2BE :   29;
- 2BF :   28;
- 2C0 :   27;
- 2C1 :   26;
- 2C2 :   25;
- 2C3 :   23;
- 2C4 :   22;
- 2C5 :   21;
- 2C6 :   20;
- 2C7 :   1F;
- 2C8 :   1E;
- 2C9 :   1D;
- 2CA :   1C;
- 2CB :   1B;
- 2CC :   1A;
- 2CD :   19;
- 2CE :   18;
- 2CF :   17;
- 2D0 :   16;
- 2D1 :   15;
- 2D2 :   14;
- 2D3 :   13;
- 2D4 :   13;
- 2D5 :   12;
- 2D6 :   11;
- 2D7 :   10;
- 2D8 :    F;
- 2D9 :    F;
- 2DA :    E;
- 2DB :    D;
- 2DC :    C;
- 2DD :    C;
- 2DE :    B;
- 2DF :    A;
- 2E0 :    A;
- 2E1 :    9;
- 2E2 :    9;
- 2E3 :    8;
- 2E4 :    8;
- 2E5 :    7;
- 2E6 :    6;
- 2E7 :    6;
- 2E8 :    6;
- 2E9 :    5;
- 2EA :    5;
- 2EB :    4;
- 2EC :    4;
- 2ED :    3;
- 2EE :    3;
- 2EF :    3;
- 2F0 :    2;
- 2F1 :    2;
- 2F2 :    2;
- 2F3 :    2;
- 2F4 :    1;
- 2F5 :    1;
- 2F6 :    1;
- 2F7 :    1;
- 2F8 :    1;
- 2F9 :    0;
- 2FA :    0;
- 2FB :    0;
- 2FC :    0;
- 2FD :    0;
- 2FE :    0;
- 2FF :    0;
- 300 :    0;
- 301 :    0;
- 302 :    0;
- 303 :    0;
- 304 :    0;
- 305 :    0;
- 306 :    0;
- 307 :    0;
- 308 :    1;
- 309 :    1;
- 30A :    1;
- 30B :    1;
- 30C :    1;
- 30D :    2;
- 30E :    2;
- 30F :    2;
- 310 :    2;
- 311 :    3;
- 312 :    3;
- 313 :    3;
- 314 :    4;
- 315 :    4;
- 316 :    5;
- 317 :    5;
- 318 :    6;
- 319 :    6;
- 31A :    6;
- 31B :    7;
- 31C :    8;
- 31D :    8;
- 31E :    9;
- 31F :    9;
- 320 :    A;
- 321 :    A;
- 322 :    B;
- 323 :    C;
- 324 :    C;
- 325 :    D;
- 326 :    E;
- 327 :    F;
- 328 :    F;
- 329 :   10;
- 32A :   11;
- 32B :   12;
- 32C :   13;
- 32D :   13;
- 32E :   14;
- 32F :   15;
- 330 :   16;
- 331 :   17;
- 332 :   18;
- 333 :   19;
- 334 :   1A;
- 335 :   1B;
- 336 :   1C;
- 337 :   1D;
- 338 :   1E;
- 339 :   1F;
- 33A :   20;
- 33B :   21;
- 33C :   22;
- 33D :   23;
- 33E :   25;
- 33F :   26;
- 340 :   27;
- 341 :   28;
- 342 :   29;
- 343 :   2B;
- 344 :   2C;
- 345 :   2D;
- 346 :   2E;
- 347 :   30;
- 348 :   31;
- 349 :   32;
- 34A :   34;
- 34B :   35;
- 34C :   37;
- 34D :   38;
- 34E :   39;
- 34F :   3B;
- 350 :   3C;
- 351 :   3E;
- 352 :   3F;
- 353 :   41;
- 354 :   42;
- 355 :   44;
- 356 :   46;
- 357 :   47;
- 358 :   49;
- 359 :   4A;
- 35A :   4C;
- 35B :   4E;
- 35C :   4F;
- 35D :   51;
- 35E :   53;
- 35F :   54;
- 360 :   56;
- 361 :   58;
- 362 :   5A;
- 363 :   5C;
- 364 :   5D;
- 365 :   5F;
- 366 :   61;
- 367 :   63;
- 368 :   65;
- 369 :   67;
- 36A :   68;
- 36B :   6A;
- 36C :   6C;
- 36D :   6E;
- 36E :   70;
- 36F :   72;
- 370 :   74;
- 371 :   76;
- 372 :   78;
- 373 :   7A;
- 374 :   7C;
- 375 :   7E;
- 376 :   80;
- 377 :   82;
- 378 :   85;
- 379 :   87;
- 37A :   89;
- 37B :   8B;
- 37C :   8D;
- 37D :   8F;
- 37E :   91;
- 37F :   94;
- 380 :   96;
- 381 :   98;
- 382 :   9A;
- 383 :   9D;
- 384 :   9F;
- 385 :   A1;
- 386 :   A3;
- 387 :   A6;
- 388 :   A8;
- 389 :   AA;
- 38A :   AD;
- 38B :   AF;
- 38C :   B1;
- 38D :   B4;
- 38E :   B6;
- 38F :   B9;
- 390 :   BB;
- 391 :   BD;
- 392 :   C0;
- 393 :   C2;
- 394 :   C5;
- 395 :   C7;
- 396 :   CA;
- 397 :   CC;
- 398 :   CF;
- 399 :   D1;
- 39A :   D4;
- 39B :   D6;
- 39C :   D9;
- 39D :   DC;
- 39E :   DE;
- 39F :   E1;
- 3A0 :   E3;
- 3A1 :   E6;
- 3A2 :   E9;
- 3A3 :   EB;
- 3A4 :   EE;
- 3A5 :   F1;
- 3A6 :   F3;
- 3A7 :   F6;
- 3A8 :   F9;
- 3A9 :   FB;
- 3AA :   FE;
- 3AB :  101;
- 3AC :  103;
- 3AD :  106;
- 3AE :  109;
- 3AF :  10C;
- 3B0 :  10E;
- 3B1 :  111;
- 3B2 :  114;
- 3B3 :  117;
- 3B4 :  11A;
- 3B5 :  11C;
- 3B6 :  11F;
- 3B7 :  122;
- 3B8 :  125;
- 3B9 :  128;
- 3BA :  12A;
- 3BB :  12D;
- 3BC :  130;
- 3BD :  133;
- 3BE :  136;
- 3BF :  139;
- 3C0 :  13C;
- 3C1 :  13F;
- 3C2 :  142;
- 3C3 :  144;
- 3C4 :  147;
- 3C5 :  14A;
- 3C6 :  14D;
- 3C7 :  150;
- 3C8 :  153;
- 3C9 :  156;
- 3CA :  159;
- 3CB :  15C;
- 3CC :  15F;
- 3CD :  162;
- 3CE :  165;
- 3CF :  168;
- 3D0 :  16B;
- 3D1 :  16E;
- 3D2 :  171;
- 3D3 :  174;
- 3D4 :  177;
- 3D5 :  17A;
- 3D6 :  17D;
- 3D7 :  180;
- 3D8 :  183;
- 3D9 :  186;
- 3DA :  189;
- 3DB :  18C;
- 3DC :  18F;
- 3DD :  192;
- 3DE :  196;
- 3DF :  199;
- 3E0 :  19C;
- 3E1 :  19F;
- 3E2 :  1A2;
- 3E3 :  1A5;
- 3E4 :  1A8;
- 3E5 :  1AB;
- 3E6 :  1AE;
- 3E7 :  1B1;
- 3E8 :  1B4;
- 3E9 :  1B8;
- 3EA :  1BB;
- 3EB :  1BE;
- 3EC :  1C1;
- 3ED :  1C4;
- 3EE :  1C7;
- 3EF :  1CA;
- 3F0 :  1CD;
- 3F1 :  1D0;
- 3F2 :  1D4;
- 3F3 :  1D7;
- 3F4 :  1DA;
- 3F5 :  1DD;
- 3F6 :  1E0;
- 3F7 :  1E3;
- 3F8 :  1E6;
- 3F9 :  1EA;
- 3FA :  1ED;
- 3FB :  1F0;
- 3FC :  1F3;
- 3FD :  1F6;
- 3FE :  1F9;
- 3FF :  1FC;
-END
+-- ROM Initialization file
+WIDTH = 10;
+DEPTH = 1024;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+   0 :  200;
+   1 :  203;
+   2 :  206;
+   3 :  209;
+   4 :  20C;
+   5 :  20F;
+   6 :  212;
+   7 :  215;
+   8 :  219;
+   9 :  21C;
+   A :  21F;
+   B :  222;
+   C :  225;
+   D :  228;
+   E :  22B;
+   F :  22F;
+  10 :  232;
+  11 :  235;
+  12 :  238;
+  13 :  23B;
+  14 :  23E;
+  15 :  241;
+  16 :  244;
+  17 :  247;
+  18 :  24B;
+  19 :  24E;
+  1A :  251;
+  1B :  254;
+  1C :  257;
+  1D :  25A;
+  1E :  25D;
+  1F :  260;
+  20 :  263;
+  21 :  266;
+  22 :  269;
+  23 :  26D;
+  24 :  270;
+  25 :  273;
+  26 :  276;
+  27 :  279;
+  28 :  27C;
+  29 :  27F;
+  2A :  282;
+  2B :  285;
+  2C :  288;
+  2D :  28B;
+  2E :  28E;
+  2F :  291;
+  30 :  294;
+  31 :  297;
+  32 :  29A;
+  33 :  29D;
+  34 :  2A0;
+  35 :  2A3;
+  36 :  2A6;
+  37 :  2A9;
+  38 :  2AC;
+  39 :  2AF;
+  3A :  2B2;
+  3B :  2B5;
+  3C :  2B8;
+  3D :  2BB;
+  3E :  2BD;
+  3F :  2C0;
+  40 :  2C3;
+  41 :  2C6;
+  42 :  2C9;
+  43 :  2CC;
+  44 :  2CF;
+  45 :  2D2;
+  46 :  2D5;
+  47 :  2D7;
+  48 :  2DA;
+  49 :  2DD;
+  4A :  2E0;
+  4B :  2E3;
+  4C :  2E5;
+  4D :  2E8;
+  4E :  2EB;
+  4F :  2EE;
+  50 :  2F1;
+  51 :  2F3;
+  52 :  2F6;
+  53 :  2F9;
+  54 :  2FC;
+  55 :  2FE;
+  56 :  301;
+  57 :  304;
+  58 :  306;
+  59 :  309;
+  5A :  30C;
+  5B :  30E;
+  5C :  311;
+  5D :  314;
+  5E :  316;
+  5F :  319;
+  60 :  31C;
+  61 :  31E;
+  62 :  321;
+  63 :  323;
+  64 :  326;
+  65 :  329;
+  66 :  32B;
+  67 :  32E;
+  68 :  330;
+  69 :  333;
+  6A :  335;
+  6B :  338;
+  6C :  33A;
+  6D :  33D;
+  6E :  33F;
+  6F :  342;
+  70 :  344;
+  71 :  346;
+  72 :  349;
+  73 :  34B;
+  74 :  34E;
+  75 :  350;
+  76 :  352;
+  77 :  355;
+  78 :  357;
+  79 :  359;
+  7A :  35C;
+  7B :  35E;
+  7C :  360;
+  7D :  362;
+  7E :  365;
+  7F :  367;
+  80 :  369;
+  81 :  36B;
+  82 :  36E;
+  83 :  370;
+  84 :  372;
+  85 :  374;
+  86 :  376;
+  87 :  378;
+  88 :  37A;
+  89 :  37D;
+  8A :  37F;
+  8B :  381;
+  8C :  383;
+  8D :  385;
+  8E :  387;
+  8F :  389;
+  90 :  38B;
+  91 :  38D;
+  92 :  38F;
+  93 :  391;
+  94 :  393;
+  95 :  395;
+  96 :  397;
+  97 :  398;
+  98 :  39A;
+  99 :  39C;
+  9A :  39E;
+  9B :  3A0;
+  9C :  3A2;
+  9D :  3A3;
+  9E :  3A5;
+  9F :  3A7;
+  A0 :  3A9;
+  A1 :  3AB;
+  A2 :  3AC;
+  A3 :  3AE;
+  A4 :  3B0;
+  A5 :  3B1;
+  A6 :  3B3;
+  A7 :  3B5;
+  A8 :  3B6;
+  A9 :  3B8;
+  AA :  3B9;
+  AB :  3BB;
+  AC :  3BD;
+  AD :  3BE;
+  AE :  3C0;
+  AF :  3C1;
+  B0 :  3C3;
+  B1 :  3C4;
+  B2 :  3C6;
+  B3 :  3C7;
+  B4 :  3C8;
+  B5 :  3CA;
+  B6 :  3CB;
+  B7 :  3CD;
+  B8 :  3CE;
+  B9 :  3CF;
+  BA :  3D1;
+  BB :  3D2;
+  BC :  3D3;
+  BD :  3D4;
+  BE :  3D6;
+  BF :  3D7;
+  C0 :  3D8;
+  C1 :  3D9;
+  C2 :  3DA;
+  C3 :  3DC;
+  C4 :  3DD;
+  C5 :  3DE;
+  C6 :  3DF;
+  C7 :  3E0;
+  C8 :  3E1;
+  C9 :  3E2;
+  CA :  3E3;
+  CB :  3E4;
+  CC :  3E5;
+  CD :  3E6;
+  CE :  3E7;
+  CF :  3E8;
+  D0 :  3E9;
+  D1 :  3EA;
+  D2 :  3EB;
+  D3 :  3EC;
+  D4 :  3EC;
+  D5 :  3ED;
+  D6 :  3EE;
+  D7 :  3EF;
+  D8 :  3F0;
+  D9 :  3F0;
+  DA :  3F1;
+  DB :  3F2;
+  DC :  3F3;
+  DD :  3F3;
+  DE :  3F4;
+  DF :  3F5;
+  E0 :  3F5;
+  E1 :  3F6;
+  E2 :  3F6;
+  E3 :  3F7;
+  E4 :  3F7;
+  E5 :  3F8;
+  E6 :  3F9;
+  E7 :  3F9;
+  E8 :  3F9;
+  E9 :  3FA;
+  EA :  3FA;
+  EB :  3FB;
+  EC :  3FB;
+  ED :  3FC;
+  EE :  3FC;
+  EF :  3FC;
+  F0 :  3FD;
+  F1 :  3FD;
+  F2 :  3FD;
+  F3 :  3FD;
+  F4 :  3FE;
+  F5 :  3FE;
+  F6 :  3FE;
+  F7 :  3FE;
+  F8 :  3FE;
+  F9 :  3FF;
+  FA :  3FF;
+  FB :  3FF;
+  FC :  3FF;
+  FD :  3FF;
+  FE :  3FF;
+  FF :  3FF;
+ 100 :  3FF;
+ 101 :  3FF;
+ 102 :  3FF;
+ 103 :  3FF;
+ 104 :  3FF;
+ 105 :  3FF;
+ 106 :  3FF;
+ 107 :  3FF;
+ 108 :  3FE;
+ 109 :  3FE;
+ 10A :  3FE;
+ 10B :  3FE;
+ 10C :  3FE;
+ 10D :  3FD;
+ 10E :  3FD;
+ 10F :  3FD;
+ 110 :  3FD;
+ 111 :  3FC;
+ 112 :  3FC;
+ 113 :  3FC;
+ 114 :  3FB;
+ 115 :  3FB;
+ 116 :  3FA;
+ 117 :  3FA;
+ 118 :  3F9;
+ 119 :  3F9;
+ 11A :  3F9;
+ 11B :  3F8;
+ 11C :  3F7;
+ 11D :  3F7;
+ 11E :  3F6;
+ 11F :  3F6;
+ 120 :  3F5;
+ 121 :  3F5;
+ 122 :  3F4;
+ 123 :  3F3;
+ 124 :  3F3;
+ 125 :  3F2;
+ 126 :  3F1;
+ 127 :  3F0;
+ 128 :  3F0;
+ 129 :  3EF;
+ 12A :  3EE;
+ 12B :  3ED;
+ 12C :  3EC;
+ 12D :  3EC;
+ 12E :  3EB;
+ 12F :  3EA;
+ 130 :  3E9;
+ 131 :  3E8;
+ 132 :  3E7;
+ 133 :  3E6;
+ 134 :  3E5;
+ 135 :  3E4;
+ 136 :  3E3;
+ 137 :  3E2;
+ 138 :  3E1;
+ 139 :  3E0;
+ 13A :  3DF;
+ 13B :  3DE;
+ 13C :  3DD;
+ 13D :  3DC;
+ 13E :  3DA;
+ 13F :  3D9;
+ 140 :  3D8;
+ 141 :  3D7;
+ 142 :  3D6;
+ 143 :  3D4;
+ 144 :  3D3;
+ 145 :  3D2;
+ 146 :  3D1;
+ 147 :  3CF;
+ 148 :  3CE;
+ 149 :  3CD;
+ 14A :  3CB;
+ 14B :  3CA;
+ 14C :  3C8;
+ 14D :  3C7;
+ 14E :  3C6;
+ 14F :  3C4;
+ 150 :  3C3;
+ 151 :  3C1;
+ 152 :  3C0;
+ 153 :  3BE;
+ 154 :  3BD;
+ 155 :  3BB;
+ 156 :  3B9;
+ 157 :  3B8;
+ 158 :  3B6;
+ 159 :  3B5;
+ 15A :  3B3;
+ 15B :  3B1;
+ 15C :  3B0;
+ 15D :  3AE;
+ 15E :  3AC;
+ 15F :  3AB;
+ 160 :  3A9;
+ 161 :  3A7;
+ 162 :  3A5;
+ 163 :  3A3;
+ 164 :  3A2;
+ 165 :  3A0;
+ 166 :  39E;
+ 167 :  39C;
+ 168 :  39A;
+ 169 :  398;
+ 16A :  397;
+ 16B :  395;
+ 16C :  393;
+ 16D :  391;
+ 16E :  38F;
+ 16F :  38D;
+ 170 :  38B;
+ 171 :  389;
+ 172 :  387;
+ 173 :  385;
+ 174 :  383;
+ 175 :  381;
+ 176 :  37F;
+ 177 :  37D;
+ 178 :  37A;
+ 179 :  378;
+ 17A :  376;
+ 17B :  374;
+ 17C :  372;
+ 17D :  370;
+ 17E :  36E;
+ 17F :  36B;
+ 180 :  369;
+ 181 :  367;
+ 182 :  365;
+ 183 :  362;
+ 184 :  360;
+ 185 :  35E;
+ 186 :  35C;
+ 187 :  359;
+ 188 :  357;
+ 189 :  355;
+ 18A :  352;
+ 18B :  350;
+ 18C :  34E;
+ 18D :  34B;
+ 18E :  349;
+ 18F :  346;
+ 190 :  344;
+ 191 :  342;
+ 192 :  33F;
+ 193 :  33D;
+ 194 :  33A;
+ 195 :  338;
+ 196 :  335;
+ 197 :  333;
+ 198 :  330;
+ 199 :  32E;
+ 19A :  32B;
+ 19B :  329;
+ 19C :  326;
+ 19D :  323;
+ 19E :  321;
+ 19F :  31E;
+ 1A0 :  31C;
+ 1A1 :  319;
+ 1A2 :  316;
+ 1A3 :  314;
+ 1A4 :  311;
+ 1A5 :  30E;
+ 1A6 :  30C;
+ 1A7 :  309;
+ 1A8 :  306;
+ 1A9 :  304;
+ 1AA :  301;
+ 1AB :  2FE;
+ 1AC :  2FC;
+ 1AD :  2F9;
+ 1AE :  2F6;
+ 1AF :  2F3;
+ 1B0 :  2F1;
+ 1B1 :  2EE;
+ 1B2 :  2EB;
+ 1B3 :  2E8;
+ 1B4 :  2E5;
+ 1B5 :  2E3;
+ 1B6 :  2E0;
+ 1B7 :  2DD;
+ 1B8 :  2DA;
+ 1B9 :  2D7;
+ 1BA :  2D5;
+ 1BB :  2D2;
+ 1BC :  2CF;
+ 1BD :  2CC;
+ 1BE :  2C9;
+ 1BF :  2C6;
+ 1C0 :  2C3;
+ 1C1 :  2C0;
+ 1C2 :  2BD;
+ 1C3 :  2BB;
+ 1C4 :  2B8;
+ 1C5 :  2B5;
+ 1C6 :  2B2;
+ 1C7 :  2AF;
+ 1C8 :  2AC;
+ 1C9 :  2A9;
+ 1CA :  2A6;
+ 1CB :  2A3;
+ 1CC :  2A0;
+ 1CD :  29D;
+ 1CE :  29A;
+ 1CF :  297;
+ 1D0 :  294;
+ 1D1 :  291;
+ 1D2 :  28E;
+ 1D3 :  28B;
+ 1D4 :  288;
+ 1D5 :  285;
+ 1D6 :  282;
+ 1D7 :  27F;
+ 1D8 :  27C;
+ 1D9 :  279;
+ 1DA :  276;
+ 1DB :  273;
+ 1DC :  270;
+ 1DD :  26D;
+ 1DE :  269;
+ 1DF :  266;
+ 1E0 :  263;
+ 1E1 :  260;
+ 1E2 :  25D;
+ 1E3 :  25A;
+ 1E4 :  257;
+ 1E5 :  254;
+ 1E6 :  251;
+ 1E7 :  24E;
+ 1E8 :  24B;
+ 1E9 :  247;
+ 1EA :  244;
+ 1EB :  241;
+ 1EC :  23E;
+ 1ED :  23B;
+ 1EE :  238;
+ 1EF :  235;
+ 1F0 :  232;
+ 1F1 :  22F;
+ 1F2 :  22B;
+ 1F3 :  228;
+ 1F4 :  225;
+ 1F5 :  222;
+ 1F6 :  21F;
+ 1F7 :  21C;
+ 1F8 :  219;
+ 1F9 :  215;
+ 1FA :  212;
+ 1FB :  20F;
+ 1FC :  20C;
+ 1FD :  209;
+ 1FE :  206;
+ 1FF :  203;
+ 200 :  200;
+ 201 :  1FC;
+ 202 :  1F9;
+ 203 :  1F6;
+ 204 :  1F3;
+ 205 :  1F0;
+ 206 :  1ED;
+ 207 :  1EA;
+ 208 :  1E6;
+ 209 :  1E3;
+ 20A :  1E0;
+ 20B :  1DD;
+ 20C :  1DA;
+ 20D :  1D7;
+ 20E :  1D4;
+ 20F :  1D0;
+ 210 :  1CD;
+ 211 :  1CA;
+ 212 :  1C7;
+ 213 :  1C4;
+ 214 :  1C1;
+ 215 :  1BE;
+ 216 :  1BB;
+ 217 :  1B8;
+ 218 :  1B4;
+ 219 :  1B1;
+ 21A :  1AE;
+ 21B :  1AB;
+ 21C :  1A8;
+ 21D :  1A5;
+ 21E :  1A2;
+ 21F :  19F;
+ 220 :  19C;
+ 221 :  199;
+ 222 :  196;
+ 223 :  192;
+ 224 :  18F;
+ 225 :  18C;
+ 226 :  189;
+ 227 :  186;
+ 228 :  183;
+ 229 :  180;
+ 22A :  17D;
+ 22B :  17A;
+ 22C :  177;
+ 22D :  174;
+ 22E :  171;
+ 22F :  16E;
+ 230 :  16B;
+ 231 :  168;
+ 232 :  165;
+ 233 :  162;
+ 234 :  15F;
+ 235 :  15C;
+ 236 :  159;
+ 237 :  156;
+ 238 :  153;
+ 239 :  150;
+ 23A :  14D;
+ 23B :  14A;
+ 23C :  147;
+ 23D :  144;
+ 23E :  142;
+ 23F :  13F;
+ 240 :  13C;
+ 241 :  139;
+ 242 :  136;
+ 243 :  133;
+ 244 :  130;
+ 245 :  12D;
+ 246 :  12A;
+ 247 :  128;
+ 248 :  125;
+ 249 :  122;
+ 24A :  11F;
+ 24B :  11C;
+ 24C :  11A;
+ 24D :  117;
+ 24E :  114;
+ 24F :  111;
+ 250 :  10E;
+ 251 :  10C;
+ 252 :  109;
+ 253 :  106;
+ 254 :  103;
+ 255 :  101;
+ 256 :   FE;
+ 257 :   FB;
+ 258 :   F9;
+ 259 :   F6;
+ 25A :   F3;
+ 25B :   F1;
+ 25C :   EE;
+ 25D :   EB;
+ 25E :   E9;
+ 25F :   E6;
+ 260 :   E3;
+ 261 :   E1;
+ 262 :   DE;
+ 263 :   DC;
+ 264 :   D9;
+ 265 :   D6;
+ 266 :   D4;
+ 267 :   D1;
+ 268 :   CF;
+ 269 :   CC;
+ 26A :   CA;
+ 26B :   C7;
+ 26C :   C5;
+ 26D :   C2;
+ 26E :   C0;
+ 26F :   BD;
+ 270 :   BB;
+ 271 :   B9;
+ 272 :   B6;
+ 273 :   B4;
+ 274 :   B1;
+ 275 :   AF;
+ 276 :   AD;
+ 277 :   AA;
+ 278 :   A8;
+ 279 :   A6;
+ 27A :   A3;
+ 27B :   A1;
+ 27C :   9F;
+ 27D :   9D;
+ 27E :   9A;
+ 27F :   98;
+ 280 :   96;
+ 281 :   94;
+ 282 :   91;
+ 283 :   8F;
+ 284 :   8D;
+ 285 :   8B;
+ 286 :   89;
+ 287 :   87;
+ 288 :   85;
+ 289 :   82;
+ 28A :   80;
+ 28B :   7E;
+ 28C :   7C;
+ 28D :   7A;
+ 28E :   78;
+ 28F :   76;
+ 290 :   74;
+ 291 :   72;
+ 292 :   70;
+ 293 :   6E;
+ 294 :   6C;
+ 295 :   6A;
+ 296 :   68;
+ 297 :   67;
+ 298 :   65;
+ 299 :   63;
+ 29A :   61;
+ 29B :   5F;
+ 29C :   5D;
+ 29D :   5C;
+ 29E :   5A;
+ 29F :   58;
+ 2A0 :   56;
+ 2A1 :   54;
+ 2A2 :   53;
+ 2A3 :   51;
+ 2A4 :   4F;
+ 2A5 :   4E;
+ 2A6 :   4C;
+ 2A7 :   4A;
+ 2A8 :   49;
+ 2A9 :   47;
+ 2AA :   46;
+ 2AB :   44;
+ 2AC :   42;
+ 2AD :   41;
+ 2AE :   3F;
+ 2AF :   3E;
+ 2B0 :   3C;
+ 2B1 :   3B;
+ 2B2 :   39;
+ 2B3 :   38;
+ 2B4 :   37;
+ 2B5 :   35;
+ 2B6 :   34;
+ 2B7 :   32;
+ 2B8 :   31;
+ 2B9 :   30;
+ 2BA :   2E;
+ 2BB :   2D;
+ 2BC :   2C;
+ 2BD :   2B;
+ 2BE :   29;
+ 2BF :   28;
+ 2C0 :   27;
+ 2C1 :   26;
+ 2C2 :   25;
+ 2C3 :   23;
+ 2C4 :   22;
+ 2C5 :   21;
+ 2C6 :   20;
+ 2C7 :   1F;
+ 2C8 :   1E;
+ 2C9 :   1D;
+ 2CA :   1C;
+ 2CB :   1B;
+ 2CC :   1A;
+ 2CD :   19;
+ 2CE :   18;
+ 2CF :   17;
+ 2D0 :   16;
+ 2D1 :   15;
+ 2D2 :   14;
+ 2D3 :   13;
+ 2D4 :   13;
+ 2D5 :   12;
+ 2D6 :   11;
+ 2D7 :   10;
+ 2D8 :    F;
+ 2D9 :    F;
+ 2DA :    E;
+ 2DB :    D;
+ 2DC :    C;
+ 2DD :    C;
+ 2DE :    B;
+ 2DF :    A;
+ 2E0 :    A;
+ 2E1 :    9;
+ 2E2 :    9;
+ 2E3 :    8;
+ 2E4 :    8;
+ 2E5 :    7;
+ 2E6 :    6;
+ 2E7 :    6;
+ 2E8 :    6;
+ 2E9 :    5;
+ 2EA :    5;
+ 2EB :    4;
+ 2EC :    4;
+ 2ED :    3;
+ 2EE :    3;
+ 2EF :    3;
+ 2F0 :    2;
+ 2F1 :    2;
+ 2F2 :    2;
+ 2F3 :    2;
+ 2F4 :    1;
+ 2F5 :    1;
+ 2F6 :    1;
+ 2F7 :    1;
+ 2F8 :    1;
+ 2F9 :    0;
+ 2FA :    0;
+ 2FB :    0;
+ 2FC :    0;
+ 2FD :    0;
+ 2FE :    0;
+ 2FF :    0;
+ 300 :    0;
+ 301 :    0;
+ 302 :    0;
+ 303 :    0;
+ 304 :    0;
+ 305 :    0;
+ 306 :    0;
+ 307 :    0;
+ 308 :    1;
+ 309 :    1;
+ 30A :    1;
+ 30B :    1;
+ 30C :    1;
+ 30D :    2;
+ 30E :    2;
+ 30F :    2;
+ 310 :    2;
+ 311 :    3;
+ 312 :    3;
+ 313 :    3;
+ 314 :    4;
+ 315 :    4;
+ 316 :    5;
+ 317 :    5;
+ 318 :    6;
+ 319 :    6;
+ 31A :    6;
+ 31B :    7;
+ 31C :    8;
+ 31D :    8;
+ 31E :    9;
+ 31F :    9;
+ 320 :    A;
+ 321 :    A;
+ 322 :    B;
+ 323 :    C;
+ 324 :    C;
+ 325 :    D;
+ 326 :    E;
+ 327 :    F;
+ 328 :    F;
+ 329 :   10;
+ 32A :   11;
+ 32B :   12;
+ 32C :   13;
+ 32D :   13;
+ 32E :   14;
+ 32F :   15;
+ 330 :   16;
+ 331 :   17;
+ 332 :   18;
+ 333 :   19;
+ 334 :   1A;
+ 335 :   1B;
+ 336 :   1C;
+ 337 :   1D;
+ 338 :   1E;
+ 339 :   1F;
+ 33A :   20;
+ 33B :   21;
+ 33C :   22;
+ 33D :   23;
+ 33E :   25;
+ 33F :   26;
+ 340 :   27;
+ 341 :   28;
+ 342 :   29;
+ 343 :   2B;
+ 344 :   2C;
+ 345 :   2D;
+ 346 :   2E;
+ 347 :   30;
+ 348 :   31;
+ 349 :   32;
+ 34A :   34;
+ 34B :   35;
+ 34C :   37;
+ 34D :   38;
+ 34E :   39;
+ 34F :   3B;
+ 350 :   3C;
+ 351 :   3E;
+ 352 :   3F;
+ 353 :   41;
+ 354 :   42;
+ 355 :   44;
+ 356 :   46;
+ 357 :   47;
+ 358 :   49;
+ 359 :   4A;
+ 35A :   4C;
+ 35B :   4E;
+ 35C :   4F;
+ 35D :   51;
+ 35E :   53;
+ 35F :   54;
+ 360 :   56;
+ 361 :   58;
+ 362 :   5A;
+ 363 :   5C;
+ 364 :   5D;
+ 365 :   5F;
+ 366 :   61;
+ 367 :   63;
+ 368 :   65;
+ 369 :   67;
+ 36A :   68;
+ 36B :   6A;
+ 36C :   6C;
+ 36D :   6E;
+ 36E :   70;
+ 36F :   72;
+ 370 :   74;
+ 371 :   76;
+ 372 :   78;
+ 373 :   7A;
+ 374 :   7C;
+ 375 :   7E;
+ 376 :   80;
+ 377 :   82;
+ 378 :   85;
+ 379 :   87;
+ 37A :   89;
+ 37B :   8B;
+ 37C :   8D;
+ 37D :   8F;
+ 37E :   91;
+ 37F :   94;
+ 380 :   96;
+ 381 :   98;
+ 382 :   9A;
+ 383 :   9D;
+ 384 :   9F;
+ 385 :   A1;
+ 386 :   A3;
+ 387 :   A6;
+ 388 :   A8;
+ 389 :   AA;
+ 38A :   AD;
+ 38B :   AF;
+ 38C :   B1;
+ 38D :   B4;
+ 38E :   B6;
+ 38F :   B9;
+ 390 :   BB;
+ 391 :   BD;
+ 392 :   C0;
+ 393 :   C2;
+ 394 :   C5;
+ 395 :   C7;
+ 396 :   CA;
+ 397 :   CC;
+ 398 :   CF;
+ 399 :   D1;
+ 39A :   D4;
+ 39B :   D6;
+ 39C :   D9;
+ 39D :   DC;
+ 39E :   DE;
+ 39F :   E1;
+ 3A0 :   E3;
+ 3A1 :   E6;
+ 3A2 :   E9;
+ 3A3 :   EB;
+ 3A4 :   EE;
+ 3A5 :   F1;
+ 3A6 :   F3;
+ 3A7 :   F6;
+ 3A8 :   F9;
+ 3A9 :   FB;
+ 3AA :   FE;
+ 3AB :  101;
+ 3AC :  103;
+ 3AD :  106;
+ 3AE :  109;
+ 3AF :  10C;
+ 3B0 :  10E;
+ 3B1 :  111;
+ 3B2 :  114;
+ 3B3 :  117;
+ 3B4 :  11A;
+ 3B5 :  11C;
+ 3B6 :  11F;
+ 3B7 :  122;
+ 3B8 :  125;
+ 3B9 :  128;
+ 3BA :  12A;
+ 3BB :  12D;
+ 3BC :  130;
+ 3BD :  133;
+ 3BE :  136;
+ 3BF :  139;
+ 3C0 :  13C;
+ 3C1 :  13F;
+ 3C2 :  142;
+ 3C3 :  144;
+ 3C4 :  147;
+ 3C5 :  14A;
+ 3C6 :  14D;
+ 3C7 :  150;
+ 3C8 :  153;
+ 3C9 :  156;
+ 3CA :  159;
+ 3CB :  15C;
+ 3CC :  15F;
+ 3CD :  162;
+ 3CE :  165;
+ 3CF :  168;
+ 3D0 :  16B;
+ 3D1 :  16E;
+ 3D2 :  171;
+ 3D3 :  174;
+ 3D4 :  177;
+ 3D5 :  17A;
+ 3D6 :  17D;
+ 3D7 :  180;
+ 3D8 :  183;
+ 3D9 :  186;
+ 3DA :  189;
+ 3DB :  18C;
+ 3DC :  18F;
+ 3DD :  192;
+ 3DE :  196;
+ 3DF :  199;
+ 3E0 :  19C;
+ 3E1 :  19F;
+ 3E2 :  1A2;
+ 3E3 :  1A5;
+ 3E4 :  1A8;
+ 3E5 :  1AB;
+ 3E6 :  1AE;
+ 3E7 :  1B1;
+ 3E8 :  1B4;
+ 3E9 :  1B8;
+ 3EA :  1BB;
+ 3EB :  1BE;
+ 3EC :  1C1;
+ 3ED :  1C4;
+ 3EE :  1C7;
+ 3EF :  1CA;
+ 3F0 :  1CD;
+ 3F1 :  1D0;
+ 3F2 :  1D4;
+ 3F3 :  1D7;
+ 3F4 :  1DA;
+ 3F5 :  1DD;
+ 3F6 :  1E0;
+ 3F7 :  1E3;
+ 3F8 :  1E6;
+ 3F9 :  1EA;
+ 3FA :  1ED;
+ 3FB :  1F0;
+ 3FC :  1F3;
+ 3FD :  1F6;
+ 3FE :  1F9;
+ 3FF :  1FC;
+END
diff --git a/part_3/ex12/sin_gen_scripts/sinegen.m b/part_3/ex12/sin_gen_scripts/sinegen.m
index 1c0f400..f459f5c 100755
--- a/part_3/ex12/sin_gen_scripts/sinegen.m
+++ b/part_3/ex12/sin_gen_scripts/sinegen.m
@@ -1,43 +1,43 @@
-% Purpose:  MATLAB script to produce contents of a ROM that stores
-%           one cycle of sinewave
-% Inputs:   None
-% Outputs:  rom_data.mif file
-% Author:   Peter Cheung
-% Version: 	1.0
-% Date:			20 Nov 2011
-	
-DEPTH = 1024;		% Size of ROM
-WIDTH = 10;			% Size of data in bits
-OUTMAX = 2^WIDTH - 1;	% Amplitude of sinewave
-
-filename = 'rom_data.mif';
-fid = fopen(filename,'w');
-
-fprintf(fid,'-- ROM Initialization file\n');
-fprintf(fid,'WIDTH = %d;\n',WIDTH);
-fprintf(fid,'DEPTH = %d;\n',DEPTH);
-fprintf(fid,'ADDRESS_RADIX = HEX;\n');
-fprintf(fid,'DATA_RADIX = HEX;\n');
-fprintf(fid,'CONTENT\nBEGIN\n');
-
-for address = 0:1023
-	angle = (address*2*pi)/DEPTH;
-	sine_value = sin(angle);
-	data = (sine_value*0.5*OUTMAX) + OUTMAX*0.5;
-	
-	fprintf(fid,'%4X : %4X;\n',address,int16(data));
-end
-
-fprintf(fid,'END\n');
-fclose(fid);
-disp('Finished');
-
-
-
-
-
-
-
-
-
-
+% Purpose:  MATLAB script to produce contents of a ROM that stores
+%           one cycle of sinewave
+% Inputs:   None
+% Outputs:  rom_data.mif file
+% Author:   Peter Cheung
+% Version: 	1.0
+% Date:			20 Nov 2011
+	
+DEPTH = 1024;		% Size of ROM
+WIDTH = 10;			% Size of data in bits
+OUTMAX = 2^WIDTH - 1;	% Amplitude of sinewave
+
+filename = 'rom_data.mif';
+fid = fopen(filename,'w');
+
+fprintf(fid,'-- ROM Initialization file\n');
+fprintf(fid,'WIDTH = %d;\n',WIDTH);
+fprintf(fid,'DEPTH = %d;\n',DEPTH);
+fprintf(fid,'ADDRESS_RADIX = HEX;\n');
+fprintf(fid,'DATA_RADIX = HEX;\n');
+fprintf(fid,'CONTENT\nBEGIN\n');
+
+for address = 0:1023
+	angle = (address*2*pi)/DEPTH;
+	sine_value = sin(angle);
+	data = (sine_value*0.5*OUTMAX) + OUTMAX*0.5;
+	
+	fprintf(fid,'%4X : %4X;\n',address,int16(data));
+end
+
+fprintf(fid,'END\n');
+fclose(fid);
+disp('Finished');
+
+
+
+
+
+
+
+
+
+
diff --git a/part_3/ex12/sin_gen_scripts/sinegen.py b/part_3/ex12/sin_gen_scripts/sinegen.py
index 9dba855..f0318d8 100755
--- a/part_3/ex12/sin_gen_scripts/sinegen.py
+++ b/part_3/ex12/sin_gen_scripts/sinegen.py
@@ -1,33 +1,33 @@
-# sinegen.py - Generate sinewave table
-#  ... for use with Altera ROMs
-# 
-from math import sin, cos, radians
-
-DEPTH = 1024  # Size of ROM
-WIDTH = 10   # Size of data in bits
-OUTMAX = 2**WIDTH - 1   # Amplitude of sinewave
-
-filename = "rom_data.mif"
-f = open(filename,'w')
-
-#  Header for the .mif file
-print >> f, "-- ROM Initialization file\n"
-print >> f, "DEPTH = %d;" % DEPTH
-print >> f, "WIDTH = %d;" % WIDTH
-print >> f, "ADDRESS_RADIX = HEX;"
-print >> f, "DATA_RADIX = HEX;\n"
-print >> f, "CONTENT\nBEGIN\n"
-
-for address in range(DEPTH):
-	angle = (address*2*pi)/DEPTH
-	sine_value = sin(angle)
-	data = int((sine_value)*0.5*OUTMAX)+OUTMAX/2
-	
-	print "%4x : %4x;" % (address, data)
-	print >> f, "%4x : %4x;" % (address, data)
-
-print >> f, "END;\n"
-
-f.close()
-
-
+# sinegen.py - Generate sinewave table
+#  ... for use with Altera ROMs
+# 
+from math import sin, cos, radians
+
+DEPTH = 1024  # Size of ROM
+WIDTH = 10   # Size of data in bits
+OUTMAX = 2**WIDTH - 1   # Amplitude of sinewave
+
+filename = "rom_data.mif"
+f = open(filename,'w')
+
+#  Header for the .mif file
+print >> f, "-- ROM Initialization file\n"
+print >> f, "DEPTH = %d;" % DEPTH
+print >> f, "WIDTH = %d;" % WIDTH
+print >> f, "ADDRESS_RADIX = HEX;"
+print >> f, "DATA_RADIX = HEX;\n"
+print >> f, "CONTENT\nBEGIN\n"
+
+for address in range(DEPTH):
+	angle = (address*2*pi)/DEPTH
+	sine_value = sin(angle)
+	data = int((sine_value)*0.5*OUTMAX)+OUTMAX/2
+	
+	print "%4x : %4x;" % (address, data)
+	print >> f, "%4x : %4x;" % (address, data)
+
+print >> f, "END;\n"
+
+f.close()
+
+
diff --git a/part_3/ex13/.qsys_edit/filters.xml b/part_3/ex13/.qsys_edit/filters.xml
index 2c6ab93..25484e0 100755
--- a/part_3/ex13/.qsys_edit/filters.xml
+++ b/part_3/ex13/.qsys_edit/filters.xml
@@ -1,2 +1,2 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<filters version="16.0" />
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="16.0" />
diff --git a/part_3/ex13/.qsys_edit/preferences.xml b/part_3/ex13/.qsys_edit/preferences.xml
index c5b7680..ea0fb24 100755
--- a/part_3/ex13/.qsys_edit/preferences.xml
+++ b/part_3/ex13/.qsys_edit/preferences.xml
@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<preferences>
- <debug showDebugMenu="0" />
- <systemtable filter="All Interfaces">
-  <columns>
-   <connections preferredWidth="47" />
-   <irq preferredWidth="34" />
-  </columns>
- </systemtable>
- <library expandedCategories="Project,Library" />
- <window width="1100" height="800" x="0" y="0" />
-</preferences>
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="47" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Project,Library" />
+ <window width="1100" height="800" x="0" y="0" />
+</preferences>
diff --git a/part_3/ex13/db/_cmp.kpt b/part_3/ex13/db/_cmp.kpt
new file mode 100644
index 0000000..957fbc6
--- /dev/null
+++ b/part_3/ex13/db/_cmp.kpt
diff --git a/part_3/ex13/ex10.v.bak b/part_3/ex13/ex10.v.bak
index 8b13789..d3f5a12 100755
--- a/part_3/ex13/ex10.v.bak
+++ b/part_3/ex13/ex10.v.bak
@@ -1 +1 @@
-
+
diff --git a/part_3/ex13/rom_data/rom_data.mif b/part_3/ex13/rom_data/rom_data.mif
index a688b6f..45464a9 100755
--- a/part_3/ex13/rom_data/rom_data.mif
+++ b/part_3/ex13/rom_data/rom_data.mif
@@ -1,1032 +1,1032 @@
--- ROM Initialization file
-WIDTH = 10;
-DEPTH = 1024;
-ADDRESS_RADIX = HEX;
-DATA_RADIX = HEX;
-CONTENT
-BEGIN
-   0 :  200;
-   1 :  203;
-   2 :  206;
-   3 :  209;
-   4 :  20C;
-   5 :  20F;
-   6 :  212;
-   7 :  215;
-   8 :  219;
-   9 :  21C;
-   A :  21F;
-   B :  222;
-   C :  225;
-   D :  228;
-   E :  22B;
-   F :  22F;
-  10 :  232;
-  11 :  235;
-  12 :  238;
-  13 :  23B;
-  14 :  23E;
-  15 :  241;
-  16 :  244;
-  17 :  247;
-  18 :  24B;
-  19 :  24E;
-  1A :  251;
-  1B :  254;
-  1C :  257;
-  1D :  25A;
-  1E :  25D;
-  1F :  260;
-  20 :  263;
-  21 :  266;
-  22 :  269;
-  23 :  26D;
-  24 :  270;
-  25 :  273;
-  26 :  276;
-  27 :  279;
-  28 :  27C;
-  29 :  27F;
-  2A :  282;
-  2B :  285;
-  2C :  288;
-  2D :  28B;
-  2E :  28E;
-  2F :  291;
-  30 :  294;
-  31 :  297;
-  32 :  29A;
-  33 :  29D;
-  34 :  2A0;
-  35 :  2A3;
-  36 :  2A6;
-  37 :  2A9;
-  38 :  2AC;
-  39 :  2AF;
-  3A :  2B2;
-  3B :  2B5;
-  3C :  2B8;
-  3D :  2BB;
-  3E :  2BD;
-  3F :  2C0;
-  40 :  2C3;
-  41 :  2C6;
-  42 :  2C9;
-  43 :  2CC;
-  44 :  2CF;
-  45 :  2D2;
-  46 :  2D5;
-  47 :  2D7;
-  48 :  2DA;
-  49 :  2DD;
-  4A :  2E0;
-  4B :  2E3;
-  4C :  2E5;
-  4D :  2E8;
-  4E :  2EB;
-  4F :  2EE;
-  50 :  2F1;
-  51 :  2F3;
-  52 :  2F6;
-  53 :  2F9;
-  54 :  2FC;
-  55 :  2FE;
-  56 :  301;
-  57 :  304;
-  58 :  306;
-  59 :  309;
-  5A :  30C;
-  5B :  30E;
-  5C :  311;
-  5D :  314;
-  5E :  316;
-  5F :  319;
-  60 :  31C;
-  61 :  31E;
-  62 :  321;
-  63 :  323;
-  64 :  326;
-  65 :  329;
-  66 :  32B;
-  67 :  32E;
-  68 :  330;
-  69 :  333;
-  6A :  335;
-  6B :  338;
-  6C :  33A;
-  6D :  33D;
-  6E :  33F;
-  6F :  342;
-  70 :  344;
-  71 :  346;
-  72 :  349;
-  73 :  34B;
-  74 :  34E;
-  75 :  350;
-  76 :  352;
-  77 :  355;
-  78 :  357;
-  79 :  359;
-  7A :  35C;
-  7B :  35E;
-  7C :  360;
-  7D :  362;
-  7E :  365;
-  7F :  367;
-  80 :  369;
-  81 :  36B;
-  82 :  36E;
-  83 :  370;
-  84 :  372;
-  85 :  374;
-  86 :  376;
-  87 :  378;
-  88 :  37A;
-  89 :  37D;
-  8A :  37F;
-  8B :  381;
-  8C :  383;
-  8D :  385;
-  8E :  387;
-  8F :  389;
-  90 :  38B;
-  91 :  38D;
-  92 :  38F;
-  93 :  391;
-  94 :  393;
-  95 :  395;
-  96 :  397;
-  97 :  398;
-  98 :  39A;
-  99 :  39C;
-  9A :  39E;
-  9B :  3A0;
-  9C :  3A2;
-  9D :  3A3;
-  9E :  3A5;
-  9F :  3A7;
-  A0 :  3A9;
-  A1 :  3AB;
-  A2 :  3AC;
-  A3 :  3AE;
-  A4 :  3B0;
-  A5 :  3B1;
-  A6 :  3B3;
-  A7 :  3B5;
-  A8 :  3B6;
-  A9 :  3B8;
-  AA :  3B9;
-  AB :  3BB;
-  AC :  3BD;
-  AD :  3BE;
-  AE :  3C0;
-  AF :  3C1;
-  B0 :  3C3;
-  B1 :  3C4;
-  B2 :  3C6;
-  B3 :  3C7;
-  B4 :  3C8;
-  B5 :  3CA;
-  B6 :  3CB;
-  B7 :  3CD;
-  B8 :  3CE;
-  B9 :  3CF;
-  BA :  3D1;
-  BB :  3D2;
-  BC :  3D3;
-  BD :  3D4;
-  BE :  3D6;
-  BF :  3D7;
-  C0 :  3D8;
-  C1 :  3D9;
-  C2 :  3DA;
-  C3 :  3DC;
-  C4 :  3DD;
-  C5 :  3DE;
-  C6 :  3DF;
-  C7 :  3E0;
-  C8 :  3E1;
-  C9 :  3E2;
-  CA :  3E3;
-  CB :  3E4;
-  CC :  3E5;
-  CD :  3E6;
-  CE :  3E7;
-  CF :  3E8;
-  D0 :  3E9;
-  D1 :  3EA;
-  D2 :  3EB;
-  D3 :  3EC;
-  D4 :  3EC;
-  D5 :  3ED;
-  D6 :  3EE;
-  D7 :  3EF;
-  D8 :  3F0;
-  D9 :  3F0;
-  DA :  3F1;
-  DB :  3F2;
-  DC :  3F3;
-  DD :  3F3;
-  DE :  3F4;
-  DF :  3F5;
-  E0 :  3F5;
-  E1 :  3F6;
-  E2 :  3F6;
-  E3 :  3F7;
-  E4 :  3F7;
-  E5 :  3F8;
-  E6 :  3F9;
-  E7 :  3F9;
-  E8 :  3F9;
-  E9 :  3FA;
-  EA :  3FA;
-  EB :  3FB;
-  EC :  3FB;
-  ED :  3FC;
-  EE :  3FC;
-  EF :  3FC;
-  F0 :  3FD;
-  F1 :  3FD;
-  F2 :  3FD;
-  F3 :  3FD;
-  F4 :  3FE;
-  F5 :  3FE;
-  F6 :  3FE;
-  F7 :  3FE;
-  F8 :  3FE;
-  F9 :  3FF;
-  FA :  3FF;
-  FB :  3FF;
-  FC :  3FF;
-  FD :  3FF;
-  FE :  3FF;
-  FF :  3FF;
- 100 :  3FF;
- 101 :  3FF;
- 102 :  3FF;
- 103 :  3FF;
- 104 :  3FF;
- 105 :  3FF;
- 106 :  3FF;
- 107 :  3FF;
- 108 :  3FE;
- 109 :  3FE;
- 10A :  3FE;
- 10B :  3FE;
- 10C :  3FE;
- 10D :  3FD;
- 10E :  3FD;
- 10F :  3FD;
- 110 :  3FD;
- 111 :  3FC;
- 112 :  3FC;
- 113 :  3FC;
- 114 :  3FB;
- 115 :  3FB;
- 116 :  3FA;
- 117 :  3FA;
- 118 :  3F9;
- 119 :  3F9;
- 11A :  3F9;
- 11B :  3F8;
- 11C :  3F7;
- 11D :  3F7;
- 11E :  3F6;
- 11F :  3F6;
- 120 :  3F5;
- 121 :  3F5;
- 122 :  3F4;
- 123 :  3F3;
- 124 :  3F3;
- 125 :  3F2;
- 126 :  3F1;
- 127 :  3F0;
- 128 :  3F0;
- 129 :  3EF;
- 12A :  3EE;
- 12B :  3ED;
- 12C :  3EC;
- 12D :  3EC;
- 12E :  3EB;
- 12F :  3EA;
- 130 :  3E9;
- 131 :  3E8;
- 132 :  3E7;
- 133 :  3E6;
- 134 :  3E5;
- 135 :  3E4;
- 136 :  3E3;
- 137 :  3E2;
- 138 :  3E1;
- 139 :  3E0;
- 13A :  3DF;
- 13B :  3DE;
- 13C :  3DD;
- 13D :  3DC;
- 13E :  3DA;
- 13F :  3D9;
- 140 :  3D8;
- 141 :  3D7;
- 142 :  3D6;
- 143 :  3D4;
- 144 :  3D3;
- 145 :  3D2;
- 146 :  3D1;
- 147 :  3CF;
- 148 :  3CE;
- 149 :  3CD;
- 14A :  3CB;
- 14B :  3CA;
- 14C :  3C8;
- 14D :  3C7;
- 14E :  3C6;
- 14F :  3C4;
- 150 :  3C3;
- 151 :  3C1;
- 152 :  3C0;
- 153 :  3BE;
- 154 :  3BD;
- 155 :  3BB;
- 156 :  3B9;
- 157 :  3B8;
- 158 :  3B6;
- 159 :  3B5;
- 15A :  3B3;
- 15B :  3B1;
- 15C :  3B0;
- 15D :  3AE;
- 15E :  3AC;
- 15F :  3AB;
- 160 :  3A9;
- 161 :  3A7;
- 162 :  3A5;
- 163 :  3A3;
- 164 :  3A2;
- 165 :  3A0;
- 166 :  39E;
- 167 :  39C;
- 168 :  39A;
- 169 :  398;
- 16A :  397;
- 16B :  395;
- 16C :  393;
- 16D :  391;
- 16E :  38F;
- 16F :  38D;
- 170 :  38B;
- 171 :  389;
- 172 :  387;
- 173 :  385;
- 174 :  383;
- 175 :  381;
- 176 :  37F;
- 177 :  37D;
- 178 :  37A;
- 179 :  378;
- 17A :  376;
- 17B :  374;
- 17C :  372;
- 17D :  370;
- 17E :  36E;
- 17F :  36B;
- 180 :  369;
- 181 :  367;
- 182 :  365;
- 183 :  362;
- 184 :  360;
- 185 :  35E;
- 186 :  35C;
- 187 :  359;
- 188 :  357;
- 189 :  355;
- 18A :  352;
- 18B :  350;
- 18C :  34E;
- 18D :  34B;
- 18E :  349;
- 18F :  346;
- 190 :  344;
- 191 :  342;
- 192 :  33F;
- 193 :  33D;
- 194 :  33A;
- 195 :  338;
- 196 :  335;
- 197 :  333;
- 198 :  330;
- 199 :  32E;
- 19A :  32B;
- 19B :  329;
- 19C :  326;
- 19D :  323;
- 19E :  321;
- 19F :  31E;
- 1A0 :  31C;
- 1A1 :  319;
- 1A2 :  316;
- 1A3 :  314;
- 1A4 :  311;
- 1A5 :  30E;
- 1A6 :  30C;
- 1A7 :  309;
- 1A8 :  306;
- 1A9 :  304;
- 1AA :  301;
- 1AB :  2FE;
- 1AC :  2FC;
- 1AD :  2F9;
- 1AE :  2F6;
- 1AF :  2F3;
- 1B0 :  2F1;
- 1B1 :  2EE;
- 1B2 :  2EB;
- 1B3 :  2E8;
- 1B4 :  2E5;
- 1B5 :  2E3;
- 1B6 :  2E0;
- 1B7 :  2DD;
- 1B8 :  2DA;
- 1B9 :  2D7;
- 1BA :  2D5;
- 1BB :  2D2;
- 1BC :  2CF;
- 1BD :  2CC;
- 1BE :  2C9;
- 1BF :  2C6;
- 1C0 :  2C3;
- 1C1 :  2C0;
- 1C2 :  2BD;
- 1C3 :  2BB;
- 1C4 :  2B8;
- 1C5 :  2B5;
- 1C6 :  2B2;
- 1C7 :  2AF;
- 1C8 :  2AC;
- 1C9 :  2A9;
- 1CA :  2A6;
- 1CB :  2A3;
- 1CC :  2A0;
- 1CD :  29D;
- 1CE :  29A;
- 1CF :  297;
- 1D0 :  294;
- 1D1 :  291;
- 1D2 :  28E;
- 1D3 :  28B;
- 1D4 :  288;
- 1D5 :  285;
- 1D6 :  282;
- 1D7 :  27F;
- 1D8 :  27C;
- 1D9 :  279;
- 1DA :  276;
- 1DB :  273;
- 1DC :  270;
- 1DD :  26D;
- 1DE :  269;
- 1DF :  266;
- 1E0 :  263;
- 1E1 :  260;
- 1E2 :  25D;
- 1E3 :  25A;
- 1E4 :  257;
- 1E5 :  254;
- 1E6 :  251;
- 1E7 :  24E;
- 1E8 :  24B;
- 1E9 :  247;
- 1EA :  244;
- 1EB :  241;
- 1EC :  23E;
- 1ED :  23B;
- 1EE :  238;
- 1EF :  235;
- 1F0 :  232;
- 1F1 :  22F;
- 1F2 :  22B;
- 1F3 :  228;
- 1F4 :  225;
- 1F5 :  222;
- 1F6 :  21F;
- 1F7 :  21C;
- 1F8 :  219;
- 1F9 :  215;
- 1FA :  212;
- 1FB :  20F;
- 1FC :  20C;
- 1FD :  209;
- 1FE :  206;
- 1FF :  203;
- 200 :  200;
- 201 :  1FC;
- 202 :  1F9;
- 203 :  1F6;
- 204 :  1F3;
- 205 :  1F0;
- 206 :  1ED;
- 207 :  1EA;
- 208 :  1E6;
- 209 :  1E3;
- 20A :  1E0;
- 20B :  1DD;
- 20C :  1DA;
- 20D :  1D7;
- 20E :  1D4;
- 20F :  1D0;
- 210 :  1CD;
- 211 :  1CA;
- 212 :  1C7;
- 213 :  1C4;
- 214 :  1C1;
- 215 :  1BE;
- 216 :  1BB;
- 217 :  1B8;
- 218 :  1B4;
- 219 :  1B1;
- 21A :  1AE;
- 21B :  1AB;
- 21C :  1A8;
- 21D :  1A5;
- 21E :  1A2;
- 21F :  19F;
- 220 :  19C;
- 221 :  199;
- 222 :  196;
- 223 :  192;
- 224 :  18F;
- 225 :  18C;
- 226 :  189;
- 227 :  186;
- 228 :  183;
- 229 :  180;
- 22A :  17D;
- 22B :  17A;
- 22C :  177;
- 22D :  174;
- 22E :  171;
- 22F :  16E;
- 230 :  16B;
- 231 :  168;
- 232 :  165;
- 233 :  162;
- 234 :  15F;
- 235 :  15C;
- 236 :  159;
- 237 :  156;
- 238 :  153;
- 239 :  150;
- 23A :  14D;
- 23B :  14A;
- 23C :  147;
- 23D :  144;
- 23E :  142;
- 23F :  13F;
- 240 :  13C;
- 241 :  139;
- 242 :  136;
- 243 :  133;
- 244 :  130;
- 245 :  12D;
- 246 :  12A;
- 247 :  128;
- 248 :  125;
- 249 :  122;
- 24A :  11F;
- 24B :  11C;
- 24C :  11A;
- 24D :  117;
- 24E :  114;
- 24F :  111;
- 250 :  10E;
- 251 :  10C;
- 252 :  109;
- 253 :  106;
- 254 :  103;
- 255 :  101;
- 256 :   FE;
- 257 :   FB;
- 258 :   F9;
- 259 :   F6;
- 25A :   F3;
- 25B :   F1;
- 25C :   EE;
- 25D :   EB;
- 25E :   E9;
- 25F :   E6;
- 260 :   E3;
- 261 :   E1;
- 262 :   DE;
- 263 :   DC;
- 264 :   D9;
- 265 :   D6;
- 266 :   D4;
- 267 :   D1;
- 268 :   CF;
- 269 :   CC;
- 26A :   CA;
- 26B :   C7;
- 26C :   C5;
- 26D :   C2;
- 26E :   C0;
- 26F :   BD;
- 270 :   BB;
- 271 :   B9;
- 272 :   B6;
- 273 :   B4;
- 274 :   B1;
- 275 :   AF;
- 276 :   AD;
- 277 :   AA;
- 278 :   A8;
- 279 :   A6;
- 27A :   A3;
- 27B :   A1;
- 27C :   9F;
- 27D :   9D;
- 27E :   9A;
- 27F :   98;
- 280 :   96;
- 281 :   94;
- 282 :   91;
- 283 :   8F;
- 284 :   8D;
- 285 :   8B;
- 286 :   89;
- 287 :   87;
- 288 :   85;
- 289 :   82;
- 28A :   80;
- 28B :   7E;
- 28C :   7C;
- 28D :   7A;
- 28E :   78;
- 28F :   76;
- 290 :   74;
- 291 :   72;
- 292 :   70;
- 293 :   6E;
- 294 :   6C;
- 295 :   6A;
- 296 :   68;
- 297 :   67;
- 298 :   65;
- 299 :   63;
- 29A :   61;
- 29B :   5F;
- 29C :   5D;
- 29D :   5C;
- 29E :   5A;
- 29F :   58;
- 2A0 :   56;
- 2A1 :   54;
- 2A2 :   53;
- 2A3 :   51;
- 2A4 :   4F;
- 2A5 :   4E;
- 2A6 :   4C;
- 2A7 :   4A;
- 2A8 :   49;
- 2A9 :   47;
- 2AA :   46;
- 2AB :   44;
- 2AC :   42;
- 2AD :   41;
- 2AE :   3F;
- 2AF :   3E;
- 2B0 :   3C;
- 2B1 :   3B;
- 2B2 :   39;
- 2B3 :   38;
- 2B4 :   37;
- 2B5 :   35;
- 2B6 :   34;
- 2B7 :   32;
- 2B8 :   31;
- 2B9 :   30;
- 2BA :   2E;
- 2BB :   2D;
- 2BC :   2C;
- 2BD :   2B;
- 2BE :   29;
- 2BF :   28;
- 2C0 :   27;
- 2C1 :   26;
- 2C2 :   25;
- 2C3 :   23;
- 2C4 :   22;
- 2C5 :   21;
- 2C6 :   20;
- 2C7 :   1F;
- 2C8 :   1E;
- 2C9 :   1D;
- 2CA :   1C;
- 2CB :   1B;
- 2CC :   1A;
- 2CD :   19;
- 2CE :   18;
- 2CF :   17;
- 2D0 :   16;
- 2D1 :   15;
- 2D2 :   14;
- 2D3 :   13;
- 2D4 :   13;
- 2D5 :   12;
- 2D6 :   11;
- 2D7 :   10;
- 2D8 :    F;
- 2D9 :    F;
- 2DA :    E;
- 2DB :    D;
- 2DC :    C;
- 2DD :    C;
- 2DE :    B;
- 2DF :    A;
- 2E0 :    A;
- 2E1 :    9;
- 2E2 :    9;
- 2E3 :    8;
- 2E4 :    8;
- 2E5 :    7;
- 2E6 :    6;
- 2E7 :    6;
- 2E8 :    6;
- 2E9 :    5;
- 2EA :    5;
- 2EB :    4;
- 2EC :    4;
- 2ED :    3;
- 2EE :    3;
- 2EF :    3;
- 2F0 :    2;
- 2F1 :    2;
- 2F2 :    2;
- 2F3 :    2;
- 2F4 :    1;
- 2F5 :    1;
- 2F6 :    1;
- 2F7 :    1;
- 2F8 :    1;
- 2F9 :    0;
- 2FA :    0;
- 2FB :    0;
- 2FC :    0;
- 2FD :    0;
- 2FE :    0;
- 2FF :    0;
- 300 :    0;
- 301 :    0;
- 302 :    0;
- 303 :    0;
- 304 :    0;
- 305 :    0;
- 306 :    0;
- 307 :    0;
- 308 :    1;
- 309 :    1;
- 30A :    1;
- 30B :    1;
- 30C :    1;
- 30D :    2;
- 30E :    2;
- 30F :    2;
- 310 :    2;
- 311 :    3;
- 312 :    3;
- 313 :    3;
- 314 :    4;
- 315 :    4;
- 316 :    5;
- 317 :    5;
- 318 :    6;
- 319 :    6;
- 31A :    6;
- 31B :    7;
- 31C :    8;
- 31D :    8;
- 31E :    9;
- 31F :    9;
- 320 :    A;
- 321 :    A;
- 322 :    B;
- 323 :    C;
- 324 :    C;
- 325 :    D;
- 326 :    E;
- 327 :    F;
- 328 :    F;
- 329 :   10;
- 32A :   11;
- 32B :   12;
- 32C :   13;
- 32D :   13;
- 32E :   14;
- 32F :   15;
- 330 :   16;
- 331 :   17;
- 332 :   18;
- 333 :   19;
- 334 :   1A;
- 335 :   1B;
- 336 :   1C;
- 337 :   1D;
- 338 :   1E;
- 339 :   1F;
- 33A :   20;
- 33B :   21;
- 33C :   22;
- 33D :   23;
- 33E :   25;
- 33F :   26;
- 340 :   27;
- 341 :   28;
- 342 :   29;
- 343 :   2B;
- 344 :   2C;
- 345 :   2D;
- 346 :   2E;
- 347 :   30;
- 348 :   31;
- 349 :   32;
- 34A :   34;
- 34B :   35;
- 34C :   37;
- 34D :   38;
- 34E :   39;
- 34F :   3B;
- 350 :   3C;
- 351 :   3E;
- 352 :   3F;
- 353 :   41;
- 354 :   42;
- 355 :   44;
- 356 :   46;
- 357 :   47;
- 358 :   49;
- 359 :   4A;
- 35A :   4C;
- 35B :   4E;
- 35C :   4F;
- 35D :   51;
- 35E :   53;
- 35F :   54;
- 360 :   56;
- 361 :   58;
- 362 :   5A;
- 363 :   5C;
- 364 :   5D;
- 365 :   5F;
- 366 :   61;
- 367 :   63;
- 368 :   65;
- 369 :   67;
- 36A :   68;
- 36B :   6A;
- 36C :   6C;
- 36D :   6E;
- 36E :   70;
- 36F :   72;
- 370 :   74;
- 371 :   76;
- 372 :   78;
- 373 :   7A;
- 374 :   7C;
- 375 :   7E;
- 376 :   80;
- 377 :   82;
- 378 :   85;
- 379 :   87;
- 37A :   89;
- 37B :   8B;
- 37C :   8D;
- 37D :   8F;
- 37E :   91;
- 37F :   94;
- 380 :   96;
- 381 :   98;
- 382 :   9A;
- 383 :   9D;
- 384 :   9F;
- 385 :   A1;
- 386 :   A3;
- 387 :   A6;
- 388 :   A8;
- 389 :   AA;
- 38A :   AD;
- 38B :   AF;
- 38C :   B1;
- 38D :   B4;
- 38E :   B6;
- 38F :   B9;
- 390 :   BB;
- 391 :   BD;
- 392 :   C0;
- 393 :   C2;
- 394 :   C5;
- 395 :   C7;
- 396 :   CA;
- 397 :   CC;
- 398 :   CF;
- 399 :   D1;
- 39A :   D4;
- 39B :   D6;
- 39C :   D9;
- 39D :   DC;
- 39E :   DE;
- 39F :   E1;
- 3A0 :   E3;
- 3A1 :   E6;
- 3A2 :   E9;
- 3A3 :   EB;
- 3A4 :   EE;
- 3A5 :   F1;
- 3A6 :   F3;
- 3A7 :   F6;
- 3A8 :   F9;
- 3A9 :   FB;
- 3AA :   FE;
- 3AB :  101;
- 3AC :  103;
- 3AD :  106;
- 3AE :  109;
- 3AF :  10C;
- 3B0 :  10E;
- 3B1 :  111;
- 3B2 :  114;
- 3B3 :  117;
- 3B4 :  11A;
- 3B5 :  11C;
- 3B6 :  11F;
- 3B7 :  122;
- 3B8 :  125;
- 3B9 :  128;
- 3BA :  12A;
- 3BB :  12D;
- 3BC :  130;
- 3BD :  133;
- 3BE :  136;
- 3BF :  139;
- 3C0 :  13C;
- 3C1 :  13F;
- 3C2 :  142;
- 3C3 :  144;
- 3C4 :  147;
- 3C5 :  14A;
- 3C6 :  14D;
- 3C7 :  150;
- 3C8 :  153;
- 3C9 :  156;
- 3CA :  159;
- 3CB :  15C;
- 3CC :  15F;
- 3CD :  162;
- 3CE :  165;
- 3CF :  168;
- 3D0 :  16B;
- 3D1 :  16E;
- 3D2 :  171;
- 3D3 :  174;
- 3D4 :  177;
- 3D5 :  17A;
- 3D6 :  17D;
- 3D7 :  180;
- 3D8 :  183;
- 3D9 :  186;
- 3DA :  189;
- 3DB :  18C;
- 3DC :  18F;
- 3DD :  192;
- 3DE :  196;
- 3DF :  199;
- 3E0 :  19C;
- 3E1 :  19F;
- 3E2 :  1A2;
- 3E3 :  1A5;
- 3E4 :  1A8;
- 3E5 :  1AB;
- 3E6 :  1AE;
- 3E7 :  1B1;
- 3E8 :  1B4;
- 3E9 :  1B8;
- 3EA :  1BB;
- 3EB :  1BE;
- 3EC :  1C1;
- 3ED :  1C4;
- 3EE :  1C7;
- 3EF :  1CA;
- 3F0 :  1CD;
- 3F1 :  1D0;
- 3F2 :  1D4;
- 3F3 :  1D7;
- 3F4 :  1DA;
- 3F5 :  1DD;
- 3F6 :  1E0;
- 3F7 :  1E3;
- 3F8 :  1E6;
- 3F9 :  1EA;
- 3FA :  1ED;
- 3FB :  1F0;
- 3FC :  1F3;
- 3FD :  1F6;
- 3FE :  1F9;
- 3FF :  1FC;
-END
+-- ROM Initialization file
+WIDTH = 10;
+DEPTH = 1024;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+   0 :  200;
+   1 :  203;
+   2 :  206;
+   3 :  209;
+   4 :  20C;
+   5 :  20F;
+   6 :  212;
+   7 :  215;
+   8 :  219;
+   9 :  21C;
+   A :  21F;
+   B :  222;
+   C :  225;
+   D :  228;
+   E :  22B;
+   F :  22F;
+  10 :  232;
+  11 :  235;
+  12 :  238;
+  13 :  23B;
+  14 :  23E;
+  15 :  241;
+  16 :  244;
+  17 :  247;
+  18 :  24B;
+  19 :  24E;
+  1A :  251;
+  1B :  254;
+  1C :  257;
+  1D :  25A;
+  1E :  25D;
+  1F :  260;
+  20 :  263;
+  21 :  266;
+  22 :  269;
+  23 :  26D;
+  24 :  270;
+  25 :  273;
+  26 :  276;
+  27 :  279;
+  28 :  27C;
+  29 :  27F;
+  2A :  282;
+  2B :  285;
+  2C :  288;
+  2D :  28B;
+  2E :  28E;
+  2F :  291;
+  30 :  294;
+  31 :  297;
+  32 :  29A;
+  33 :  29D;
+  34 :  2A0;
+  35 :  2A3;
+  36 :  2A6;
+  37 :  2A9;
+  38 :  2AC;
+  39 :  2AF;
+  3A :  2B2;
+  3B :  2B5;
+  3C :  2B8;
+  3D :  2BB;
+  3E :  2BD;
+  3F :  2C0;
+  40 :  2C3;
+  41 :  2C6;
+  42 :  2C9;
+  43 :  2CC;
+  44 :  2CF;
+  45 :  2D2;
+  46 :  2D5;
+  47 :  2D7;
+  48 :  2DA;
+  49 :  2DD;
+  4A :  2E0;
+  4B :  2E3;
+  4C :  2E5;
+  4D :  2E8;
+  4E :  2EB;
+  4F :  2EE;
+  50 :  2F1;
+  51 :  2F3;
+  52 :  2F6;
+  53 :  2F9;
+  54 :  2FC;
+  55 :  2FE;
+  56 :  301;
+  57 :  304;
+  58 :  306;
+  59 :  309;
+  5A :  30C;
+  5B :  30E;
+  5C :  311;
+  5D :  314;
+  5E :  316;
+  5F :  319;
+  60 :  31C;
+  61 :  31E;
+  62 :  321;
+  63 :  323;
+  64 :  326;
+  65 :  329;
+  66 :  32B;
+  67 :  32E;
+  68 :  330;
+  69 :  333;
+  6A :  335;
+  6B :  338;
+  6C :  33A;
+  6D :  33D;
+  6E :  33F;
+  6F :  342;
+  70 :  344;
+  71 :  346;
+  72 :  349;
+  73 :  34B;
+  74 :  34E;
+  75 :  350;
+  76 :  352;
+  77 :  355;
+  78 :  357;
+  79 :  359;
+  7A :  35C;
+  7B :  35E;
+  7C :  360;
+  7D :  362;
+  7E :  365;
+  7F :  367;
+  80 :  369;
+  81 :  36B;
+  82 :  36E;
+  83 :  370;
+  84 :  372;
+  85 :  374;
+  86 :  376;
+  87 :  378;
+  88 :  37A;
+  89 :  37D;
+  8A :  37F;
+  8B :  381;
+  8C :  383;
+  8D :  385;
+  8E :  387;
+  8F :  389;
+  90 :  38B;
+  91 :  38D;
+  92 :  38F;
+  93 :  391;
+  94 :  393;
+  95 :  395;
+  96 :  397;
+  97 :  398;
+  98 :  39A;
+  99 :  39C;
+  9A :  39E;
+  9B :  3A0;
+  9C :  3A2;
+  9D :  3A3;
+  9E :  3A5;
+  9F :  3A7;
+  A0 :  3A9;
+  A1 :  3AB;
+  A2 :  3AC;
+  A3 :  3AE;
+  A4 :  3B0;
+  A5 :  3B1;
+  A6 :  3B3;
+  A7 :  3B5;
+  A8 :  3B6;
+  A9 :  3B8;
+  AA :  3B9;
+  AB :  3BB;
+  AC :  3BD;
+  AD :  3BE;
+  AE :  3C0;
+  AF :  3C1;
+  B0 :  3C3;
+  B1 :  3C4;
+  B2 :  3C6;
+  B3 :  3C7;
+  B4 :  3C8;
+  B5 :  3CA;
+  B6 :  3CB;
+  B7 :  3CD;
+  B8 :  3CE;
+  B9 :  3CF;
+  BA :  3D1;
+  BB :  3D2;
+  BC :  3D3;
+  BD :  3D4;
+  BE :  3D6;
+  BF :  3D7;
+  C0 :  3D8;
+  C1 :  3D9;
+  C2 :  3DA;
+  C3 :  3DC;
+  C4 :  3DD;
+  C5 :  3DE;
+  C6 :  3DF;
+  C7 :  3E0;
+  C8 :  3E1;
+  C9 :  3E2;
+  CA :  3E3;
+  CB :  3E4;
+  CC :  3E5;
+  CD :  3E6;
+  CE :  3E7;
+  CF :  3E8;
+  D0 :  3E9;
+  D1 :  3EA;
+  D2 :  3EB;
+  D3 :  3EC;
+  D4 :  3EC;
+  D5 :  3ED;
+  D6 :  3EE;
+  D7 :  3EF;
+  D8 :  3F0;
+  D9 :  3F0;
+  DA :  3F1;
+  DB :  3F2;
+  DC :  3F3;
+  DD :  3F3;
+  DE :  3F4;
+  DF :  3F5;
+  E0 :  3F5;
+  E1 :  3F6;
+  E2 :  3F6;
+  E3 :  3F7;
+  E4 :  3F7;
+  E5 :  3F8;
+  E6 :  3F9;
+  E7 :  3F9;
+  E8 :  3F9;
+  E9 :  3FA;
+  EA :  3FA;
+  EB :  3FB;
+  EC :  3FB;
+  ED :  3FC;
+  EE :  3FC;
+  EF :  3FC;
+  F0 :  3FD;
+  F1 :  3FD;
+  F2 :  3FD;
+  F3 :  3FD;
+  F4 :  3FE;
+  F5 :  3FE;
+  F6 :  3FE;
+  F7 :  3FE;
+  F8 :  3FE;
+  F9 :  3FF;
+  FA :  3FF;
+  FB :  3FF;
+  FC :  3FF;
+  FD :  3FF;
+  FE :  3FF;
+  FF :  3FF;
+ 100 :  3FF;
+ 101 :  3FF;
+ 102 :  3FF;
+ 103 :  3FF;
+ 104 :  3FF;
+ 105 :  3FF;
+ 106 :  3FF;
+ 107 :  3FF;
+ 108 :  3FE;
+ 109 :  3FE;
+ 10A :  3FE;
+ 10B :  3FE;
+ 10C :  3FE;
+ 10D :  3FD;
+ 10E :  3FD;
+ 10F :  3FD;
+ 110 :  3FD;
+ 111 :  3FC;
+ 112 :  3FC;
+ 113 :  3FC;
+ 114 :  3FB;
+ 115 :  3FB;
+ 116 :  3FA;
+ 117 :  3FA;
+ 118 :  3F9;
+ 119 :  3F9;
+ 11A :  3F9;
+ 11B :  3F8;
+ 11C :  3F7;
+ 11D :  3F7;
+ 11E :  3F6;
+ 11F :  3F6;
+ 120 :  3F5;
+ 121 :  3F5;
+ 122 :  3F4;
+ 123 :  3F3;
+ 124 :  3F3;
+ 125 :  3F2;
+ 126 :  3F1;
+ 127 :  3F0;
+ 128 :  3F0;
+ 129 :  3EF;
+ 12A :  3EE;
+ 12B :  3ED;
+ 12C :  3EC;
+ 12D :  3EC;
+ 12E :  3EB;
+ 12F :  3EA;
+ 130 :  3E9;
+ 131 :  3E8;
+ 132 :  3E7;
+ 133 :  3E6;
+ 134 :  3E5;
+ 135 :  3E4;
+ 136 :  3E3;
+ 137 :  3E2;
+ 138 :  3E1;
+ 139 :  3E0;
+ 13A :  3DF;
+ 13B :  3DE;
+ 13C :  3DD;
+ 13D :  3DC;
+ 13E :  3DA;
+ 13F :  3D9;
+ 140 :  3D8;
+ 141 :  3D7;
+ 142 :  3D6;
+ 143 :  3D4;
+ 144 :  3D3;
+ 145 :  3D2;
+ 146 :  3D1;
+ 147 :  3CF;
+ 148 :  3CE;
+ 149 :  3CD;
+ 14A :  3CB;
+ 14B :  3CA;
+ 14C :  3C8;
+ 14D :  3C7;
+ 14E :  3C6;
+ 14F :  3C4;
+ 150 :  3C3;
+ 151 :  3C1;
+ 152 :  3C0;
+ 153 :  3BE;
+ 154 :  3BD;
+ 155 :  3BB;
+ 156 :  3B9;
+ 157 :  3B8;
+ 158 :  3B6;
+ 159 :  3B5;
+ 15A :  3B3;
+ 15B :  3B1;
+ 15C :  3B0;
+ 15D :  3AE;
+ 15E :  3AC;
+ 15F :  3AB;
+ 160 :  3A9;
+ 161 :  3A7;
+ 162 :  3A5;
+ 163 :  3A3;
+ 164 :  3A2;
+ 165 :  3A0;
+ 166 :  39E;
+ 167 :  39C;
+ 168 :  39A;
+ 169 :  398;
+ 16A :  397;
+ 16B :  395;
+ 16C :  393;
+ 16D :  391;
+ 16E :  38F;
+ 16F :  38D;
+ 170 :  38B;
+ 171 :  389;
+ 172 :  387;
+ 173 :  385;
+ 174 :  383;
+ 175 :  381;
+ 176 :  37F;
+ 177 :  37D;
+ 178 :  37A;
+ 179 :  378;
+ 17A :  376;
+ 17B :  374;
+ 17C :  372;
+ 17D :  370;
+ 17E :  36E;
+ 17F :  36B;
+ 180 :  369;
+ 181 :  367;
+ 182 :  365;
+ 183 :  362;
+ 184 :  360;
+ 185 :  35E;
+ 186 :  35C;
+ 187 :  359;
+ 188 :  357;
+ 189 :  355;
+ 18A :  352;
+ 18B :  350;
+ 18C :  34E;
+ 18D :  34B;
+ 18E :  349;
+ 18F :  346;
+ 190 :  344;
+ 191 :  342;
+ 192 :  33F;
+ 193 :  33D;
+ 194 :  33A;
+ 195 :  338;
+ 196 :  335;
+ 197 :  333;
+ 198 :  330;
+ 199 :  32E;
+ 19A :  32B;
+ 19B :  329;
+ 19C :  326;
+ 19D :  323;
+ 19E :  321;
+ 19F :  31E;
+ 1A0 :  31C;
+ 1A1 :  319;
+ 1A2 :  316;
+ 1A3 :  314;
+ 1A4 :  311;
+ 1A5 :  30E;
+ 1A6 :  30C;
+ 1A7 :  309;
+ 1A8 :  306;
+ 1A9 :  304;
+ 1AA :  301;
+ 1AB :  2FE;
+ 1AC :  2FC;
+ 1AD :  2F9;
+ 1AE :  2F6;
+ 1AF :  2F3;
+ 1B0 :  2F1;
+ 1B1 :  2EE;
+ 1B2 :  2EB;
+ 1B3 :  2E8;
+ 1B4 :  2E5;
+ 1B5 :  2E3;
+ 1B6 :  2E0;
+ 1B7 :  2DD;
+ 1B8 :  2DA;
+ 1B9 :  2D7;
+ 1BA :  2D5;
+ 1BB :  2D2;
+ 1BC :  2CF;
+ 1BD :  2CC;
+ 1BE :  2C9;
+ 1BF :  2C6;
+ 1C0 :  2C3;
+ 1C1 :  2C0;
+ 1C2 :  2BD;
+ 1C3 :  2BB;
+ 1C4 :  2B8;
+ 1C5 :  2B5;
+ 1C6 :  2B2;
+ 1C7 :  2AF;
+ 1C8 :  2AC;
+ 1C9 :  2A9;
+ 1CA :  2A6;
+ 1CB :  2A3;
+ 1CC :  2A0;
+ 1CD :  29D;
+ 1CE :  29A;
+ 1CF :  297;
+ 1D0 :  294;
+ 1D1 :  291;
+ 1D2 :  28E;
+ 1D3 :  28B;
+ 1D4 :  288;
+ 1D5 :  285;
+ 1D6 :  282;
+ 1D7 :  27F;
+ 1D8 :  27C;
+ 1D9 :  279;
+ 1DA :  276;
+ 1DB :  273;
+ 1DC :  270;
+ 1DD :  26D;
+ 1DE :  269;
+ 1DF :  266;
+ 1E0 :  263;
+ 1E1 :  260;
+ 1E2 :  25D;
+ 1E3 :  25A;
+ 1E4 :  257;
+ 1E5 :  254;
+ 1E6 :  251;
+ 1E7 :  24E;
+ 1E8 :  24B;
+ 1E9 :  247;
+ 1EA :  244;
+ 1EB :  241;
+ 1EC :  23E;
+ 1ED :  23B;
+ 1EE :  238;
+ 1EF :  235;
+ 1F0 :  232;
+ 1F1 :  22F;
+ 1F2 :  22B;
+ 1F3 :  228;
+ 1F4 :  225;
+ 1F5 :  222;
+ 1F6 :  21F;
+ 1F7 :  21C;
+ 1F8 :  219;
+ 1F9 :  215;
+ 1FA :  212;
+ 1FB :  20F;
+ 1FC :  20C;
+ 1FD :  209;
+ 1FE :  206;
+ 1FF :  203;
+ 200 :  200;
+ 201 :  1FC;
+ 202 :  1F9;
+ 203 :  1F6;
+ 204 :  1F3;
+ 205 :  1F0;
+ 206 :  1ED;
+ 207 :  1EA;
+ 208 :  1E6;
+ 209 :  1E3;
+ 20A :  1E0;
+ 20B :  1DD;
+ 20C :  1DA;
+ 20D :  1D7;
+ 20E :  1D4;
+ 20F :  1D0;
+ 210 :  1CD;
+ 211 :  1CA;
+ 212 :  1C7;
+ 213 :  1C4;
+ 214 :  1C1;
+ 215 :  1BE;
+ 216 :  1BB;
+ 217 :  1B8;
+ 218 :  1B4;
+ 219 :  1B1;
+ 21A :  1AE;
+ 21B :  1AB;
+ 21C :  1A8;
+ 21D :  1A5;
+ 21E :  1A2;
+ 21F :  19F;
+ 220 :  19C;
+ 221 :  199;
+ 222 :  196;
+ 223 :  192;
+ 224 :  18F;
+ 225 :  18C;
+ 226 :  189;
+ 227 :  186;
+ 228 :  183;
+ 229 :  180;
+ 22A :  17D;
+ 22B :  17A;
+ 22C :  177;
+ 22D :  174;
+ 22E :  171;
+ 22F :  16E;
+ 230 :  16B;
+ 231 :  168;
+ 232 :  165;
+ 233 :  162;
+ 234 :  15F;
+ 235 :  15C;
+ 236 :  159;
+ 237 :  156;
+ 238 :  153;
+ 239 :  150;
+ 23A :  14D;
+ 23B :  14A;
+ 23C :  147;
+ 23D :  144;
+ 23E :  142;
+ 23F :  13F;
+ 240 :  13C;
+ 241 :  139;
+ 242 :  136;
+ 243 :  133;
+ 244 :  130;
+ 245 :  12D;
+ 246 :  12A;
+ 247 :  128;
+ 248 :  125;
+ 249 :  122;
+ 24A :  11F;
+ 24B :  11C;
+ 24C :  11A;
+ 24D :  117;
+ 24E :  114;
+ 24F :  111;
+ 250 :  10E;
+ 251 :  10C;
+ 252 :  109;
+ 253 :  106;
+ 254 :  103;
+ 255 :  101;
+ 256 :   FE;
+ 257 :   FB;
+ 258 :   F9;
+ 259 :   F6;
+ 25A :   F3;
+ 25B :   F1;
+ 25C :   EE;
+ 25D :   EB;
+ 25E :   E9;
+ 25F :   E6;
+ 260 :   E3;
+ 261 :   E1;
+ 262 :   DE;
+ 263 :   DC;
+ 264 :   D9;
+ 265 :   D6;
+ 266 :   D4;
+ 267 :   D1;
+ 268 :   CF;
+ 269 :   CC;
+ 26A :   CA;
+ 26B :   C7;
+ 26C :   C5;
+ 26D :   C2;
+ 26E :   C0;
+ 26F :   BD;
+ 270 :   BB;
+ 271 :   B9;
+ 272 :   B6;
+ 273 :   B4;
+ 274 :   B1;
+ 275 :   AF;
+ 276 :   AD;
+ 277 :   AA;
+ 278 :   A8;
+ 279 :   A6;
+ 27A :   A3;
+ 27B :   A1;
+ 27C :   9F;
+ 27D :   9D;
+ 27E :   9A;
+ 27F :   98;
+ 280 :   96;
+ 281 :   94;
+ 282 :   91;
+ 283 :   8F;
+ 284 :   8D;
+ 285 :   8B;
+ 286 :   89;
+ 287 :   87;
+ 288 :   85;
+ 289 :   82;
+ 28A :   80;
+ 28B :   7E;
+ 28C :   7C;
+ 28D :   7A;
+ 28E :   78;
+ 28F :   76;
+ 290 :   74;
+ 291 :   72;
+ 292 :   70;
+ 293 :   6E;
+ 294 :   6C;
+ 295 :   6A;
+ 296 :   68;
+ 297 :   67;
+ 298 :   65;
+ 299 :   63;
+ 29A :   61;
+ 29B :   5F;
+ 29C :   5D;
+ 29D :   5C;
+ 29E :   5A;
+ 29F :   58;
+ 2A0 :   56;
+ 2A1 :   54;
+ 2A2 :   53;
+ 2A3 :   51;
+ 2A4 :   4F;
+ 2A5 :   4E;
+ 2A6 :   4C;
+ 2A7 :   4A;
+ 2A8 :   49;
+ 2A9 :   47;
+ 2AA :   46;
+ 2AB :   44;
+ 2AC :   42;
+ 2AD :   41;
+ 2AE :   3F;
+ 2AF :   3E;
+ 2B0 :   3C;
+ 2B1 :   3B;
+ 2B2 :   39;
+ 2B3 :   38;
+ 2B4 :   37;
+ 2B5 :   35;
+ 2B6 :   34;
+ 2B7 :   32;
+ 2B8 :   31;
+ 2B9 :   30;
+ 2BA :   2E;
+ 2BB :   2D;
+ 2BC :   2C;
+ 2BD :   2B;
+ 2BE :   29;
+ 2BF :   28;
+ 2C0 :   27;
+ 2C1 :   26;
+ 2C2 :   25;
+ 2C3 :   23;
+ 2C4 :   22;
+ 2C5 :   21;
+ 2C6 :   20;
+ 2C7 :   1F;
+ 2C8 :   1E;
+ 2C9 :   1D;
+ 2CA :   1C;
+ 2CB :   1B;
+ 2CC :   1A;
+ 2CD :   19;
+ 2CE :   18;
+ 2CF :   17;
+ 2D0 :   16;
+ 2D1 :   15;
+ 2D2 :   14;
+ 2D3 :   13;
+ 2D4 :   13;
+ 2D5 :   12;
+ 2D6 :   11;
+ 2D7 :   10;
+ 2D8 :    F;
+ 2D9 :    F;
+ 2DA :    E;
+ 2DB :    D;
+ 2DC :    C;
+ 2DD :    C;
+ 2DE :    B;
+ 2DF :    A;
+ 2E0 :    A;
+ 2E1 :    9;
+ 2E2 :    9;
+ 2E3 :    8;
+ 2E4 :    8;
+ 2E5 :    7;
+ 2E6 :    6;
+ 2E7 :    6;
+ 2E8 :    6;
+ 2E9 :    5;
+ 2EA :    5;
+ 2EB :    4;
+ 2EC :    4;
+ 2ED :    3;
+ 2EE :    3;
+ 2EF :    3;
+ 2F0 :    2;
+ 2F1 :    2;
+ 2F2 :    2;
+ 2F3 :    2;
+ 2F4 :    1;
+ 2F5 :    1;
+ 2F6 :    1;
+ 2F7 :    1;
+ 2F8 :    1;
+ 2F9 :    0;
+ 2FA :    0;
+ 2FB :    0;
+ 2FC :    0;
+ 2FD :    0;
+ 2FE :    0;
+ 2FF :    0;
+ 300 :    0;
+ 301 :    0;
+ 302 :    0;
+ 303 :    0;
+ 304 :    0;
+ 305 :    0;
+ 306 :    0;
+ 307 :    0;
+ 308 :    1;
+ 309 :    1;
+ 30A :    1;
+ 30B :    1;
+ 30C :    1;
+ 30D :    2;
+ 30E :    2;
+ 30F :    2;
+ 310 :    2;
+ 311 :    3;
+ 312 :    3;
+ 313 :    3;
+ 314 :    4;
+ 315 :    4;
+ 316 :    5;
+ 317 :    5;
+ 318 :    6;
+ 319 :    6;
+ 31A :    6;
+ 31B :    7;
+ 31C :    8;
+ 31D :    8;
+ 31E :    9;
+ 31F :    9;
+ 320 :    A;
+ 321 :    A;
+ 322 :    B;
+ 323 :    C;
+ 324 :    C;
+ 325 :    D;
+ 326 :    E;
+ 327 :    F;
+ 328 :    F;
+ 329 :   10;
+ 32A :   11;
+ 32B :   12;
+ 32C :   13;
+ 32D :   13;
+ 32E :   14;
+ 32F :   15;
+ 330 :   16;
+ 331 :   17;
+ 332 :   18;
+ 333 :   19;
+ 334 :   1A;
+ 335 :   1B;
+ 336 :   1C;
+ 337 :   1D;
+ 338 :   1E;
+ 339 :   1F;
+ 33A :   20;
+ 33B :   21;
+ 33C :   22;
+ 33D :   23;
+ 33E :   25;
+ 33F :   26;
+ 340 :   27;
+ 341 :   28;
+ 342 :   29;
+ 343 :   2B;
+ 344 :   2C;
+ 345 :   2D;
+ 346 :   2E;
+ 347 :   30;
+ 348 :   31;
+ 349 :   32;
+ 34A :   34;
+ 34B :   35;
+ 34C :   37;
+ 34D :   38;
+ 34E :   39;
+ 34F :   3B;
+ 350 :   3C;
+ 351 :   3E;
+ 352 :   3F;
+ 353 :   41;
+ 354 :   42;
+ 355 :   44;
+ 356 :   46;
+ 357 :   47;
+ 358 :   49;
+ 359 :   4A;
+ 35A :   4C;
+ 35B :   4E;
+ 35C :   4F;
+ 35D :   51;
+ 35E :   53;
+ 35F :   54;
+ 360 :   56;
+ 361 :   58;
+ 362 :   5A;
+ 363 :   5C;
+ 364 :   5D;
+ 365 :   5F;
+ 366 :   61;
+ 367 :   63;
+ 368 :   65;
+ 369 :   67;
+ 36A :   68;
+ 36B :   6A;
+ 36C :   6C;
+ 36D :   6E;
+ 36E :   70;
+ 36F :   72;
+ 370 :   74;
+ 371 :   76;
+ 372 :   78;
+ 373 :   7A;
+ 374 :   7C;
+ 375 :   7E;
+ 376 :   80;
+ 377 :   82;
+ 378 :   85;
+ 379 :   87;
+ 37A :   89;
+ 37B :   8B;
+ 37C :   8D;
+ 37D :   8F;
+ 37E :   91;
+ 37F :   94;
+ 380 :   96;
+ 381 :   98;
+ 382 :   9A;
+ 383 :   9D;
+ 384 :   9F;
+ 385 :   A1;
+ 386 :   A3;
+ 387 :   A6;
+ 388 :   A8;
+ 389 :   AA;
+ 38A :   AD;
+ 38B :   AF;
+ 38C :   B1;
+ 38D :   B4;
+ 38E :   B6;
+ 38F :   B9;
+ 390 :   BB;
+ 391 :   BD;
+ 392 :   C0;
+ 393 :   C2;
+ 394 :   C5;
+ 395 :   C7;
+ 396 :   CA;
+ 397 :   CC;
+ 398 :   CF;
+ 399 :   D1;
+ 39A :   D4;
+ 39B :   D6;
+ 39C :   D9;
+ 39D :   DC;
+ 39E :   DE;
+ 39F :   E1;
+ 3A0 :   E3;
+ 3A1 :   E6;
+ 3A2 :   E9;
+ 3A3 :   EB;
+ 3A4 :   EE;
+ 3A5 :   F1;
+ 3A6 :   F3;
+ 3A7 :   F6;
+ 3A8 :   F9;
+ 3A9 :   FB;
+ 3AA :   FE;
+ 3AB :  101;
+ 3AC :  103;
+ 3AD :  106;
+ 3AE :  109;
+ 3AF :  10C;
+ 3B0 :  10E;
+ 3B1 :  111;
+ 3B2 :  114;
+ 3B3 :  117;
+ 3B4 :  11A;
+ 3B5 :  11C;
+ 3B6 :  11F;
+ 3B7 :  122;
+ 3B8 :  125;
+ 3B9 :  128;
+ 3BA :  12A;
+ 3BB :  12D;
+ 3BC :  130;
+ 3BD :  133;
+ 3BE :  136;
+ 3BF :  139;
+ 3C0 :  13C;
+ 3C1 :  13F;
+ 3C2 :  142;
+ 3C3 :  144;
+ 3C4 :  147;
+ 3C5 :  14A;
+ 3C6 :  14D;
+ 3C7 :  150;
+ 3C8 :  153;
+ 3C9 :  156;
+ 3CA :  159;
+ 3CB :  15C;
+ 3CC :  15F;
+ 3CD :  162;
+ 3CE :  165;
+ 3CF :  168;
+ 3D0 :  16B;
+ 3D1 :  16E;
+ 3D2 :  171;
+ 3D3 :  174;
+ 3D4 :  177;
+ 3D5 :  17A;
+ 3D6 :  17D;
+ 3D7 :  180;
+ 3D8 :  183;
+ 3D9 :  186;
+ 3DA :  189;
+ 3DB :  18C;
+ 3DC :  18F;
+ 3DD :  192;
+ 3DE :  196;
+ 3DF :  199;
+ 3E0 :  19C;
+ 3E1 :  19F;
+ 3E2 :  1A2;
+ 3E3 :  1A5;
+ 3E4 :  1A8;
+ 3E5 :  1AB;
+ 3E6 :  1AE;
+ 3E7 :  1B1;
+ 3E8 :  1B4;
+ 3E9 :  1B8;
+ 3EA :  1BB;
+ 3EB :  1BE;
+ 3EC :  1C1;
+ 3ED :  1C4;
+ 3EE :  1C7;
+ 3EF :  1CA;
+ 3F0 :  1CD;
+ 3F1 :  1D0;
+ 3F2 :  1D4;
+ 3F3 :  1D7;
+ 3F4 :  1DA;
+ 3F5 :  1DD;
+ 3F6 :  1E0;
+ 3F7 :  1E3;
+ 3F8 :  1E6;
+ 3F9 :  1EA;
+ 3FA :  1ED;
+ 3FB :  1F0;
+ 3FC :  1F3;
+ 3FD :  1F6;
+ 3FE :  1F9;
+ 3FF :  1FC;
+END
diff --git a/part_3/ex13/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex13/simulation/modelsim/do_files/tb_spi2dac.do
index b12a7d7..52dd5a2 100755
--- a/part_3/ex13/simulation/modelsim/do_files/tb_spi2dac.do
+++ b/part_3/ex13/simulation/modelsim/do_files/tb_spi2dac.do
@@ -1,17 +1,17 @@
-add wave -position end  sysclk
-add wave -position end -hexadecimal data_in
-add wave -position end load
-add wave -position end  dac_sdi
-add wave -position end  dac_cs
-add wave -position end  dac_sck
-add wave -position end  dac_ld
-force sysclk 1 0, 0 10ns -r 20ns
-force data_in 10'h23b
-force load 0
-run 200ns
-force load 1
-run 400ns
-force load 0
-run 20us
-
-
+add wave -position end  sysclk
+add wave -position end -hexadecimal data_in
+add wave -position end load
+add wave -position end  dac_sdi
+add wave -position end  dac_cs
+add wave -position end  dac_sck
+add wave -position end  dac_ld
+force sysclk 1 0, 0 10ns -r 20ns
+force data_in 10'h23b
+force load 0
+run 200ns
+force load 1
+run 400ns
+force load 0
+run 20us
+
+
diff --git a/part_3/ex13/simulation/modelsim/rtl_work/_info b/part_3/ex13/simulation/modelsim/rtl_work/_info
index 499bdd4..63648ac 100755
--- a/part_3/ex13/simulation/modelsim/rtl_work/_info
+++ b/part_3/ex13/simulation/modelsim/rtl_work/_info
@@ -1,25 +1,25 @@
-m255
-K3
-13
-cModel Technology
-Z0 dC:\New folder\ex10\simulation\modelsim
-vspi2dac
-!i10b 1
-!s100 Yc_:?1WP<4LKj7cQXiUbl1
-IzTNjHgWKkeSFYc0]WM5Gm2
-VFNOGDa=aYhJTn=76LYB@A2
-Z1 dC:\New folder\ex10\simulation\modelsim
-w1478805578
-8C:/New folder/ex10/verilog_files/spi2dac.v
-FC:/New folder/ex10/verilog_files/spi2dac.v
-L0 9
-OV;L;10.1d;51
-r1
-!s85 0
-31
-!s108 1480413939.783000
-!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
-!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
-!s101 -O0
-o-vlog01compat -work work -O0
-!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\ex10\simulation\modelsim
+vspi2dac
+!i10b 1
+!s100 Yc_:?1WP<4LKj7cQXiUbl1
+IzTNjHgWKkeSFYc0]WM5Gm2
+VFNOGDa=aYhJTn=76LYB@A2
+Z1 dC:\New folder\ex10\simulation\modelsim
+w1478805578
+8C:/New folder/ex10/verilog_files/spi2dac.v
+FC:/New folder/ex10/verilog_files/spi2dac.v
+L0 9
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1480413939.783000
+!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
diff --git a/part_3/ex13/simulation/modelsim/rtl_work/_vmake b/part_3/ex13/simulation/modelsim/rtl_work/_vmake
index 2f7e729..b51b305 100755
--- a/part_3/ex13/simulation/modelsim/rtl_work/_vmake
+++ b/part_3/ex13/simulation/modelsim/rtl_work/_vmake
@@ -1,3 +1,3 @@
-m255
-K3
-cModel Technology
+m255
+K3
+cModel Technology
diff --git a/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
index e874ed3..2a503c0 100755
--- a/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
+++ b/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
@@ -1,30 +1,30 @@
-library verilog;
-use verilog.vl_types.all;
-entity spi2dac is
-    generic(
-        BUF             : vl_logic := Hi1;
-        GA_N            : vl_logic := Hi1;
-        SHDN_N          : vl_logic := Hi1;
-        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
-        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
-        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
-        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
-    );
-    port(
-        sysclk          : in     vl_logic;
-        data_in         : in     vl_logic_vector(9 downto 0);
-        load            : in     vl_logic;
-        dac_sdi         : out    vl_logic;
-        dac_cs          : out    vl_logic;
-        dac_sck         : out    vl_logic;
-        dac_ld          : out    vl_logic
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of BUF : constant is 1;
-    attribute mti_svvh_generic_type of GA_N : constant is 1;
-    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
-    attribute mti_svvh_generic_type of TC : constant is 1;
-    attribute mti_svvh_generic_type of IDLE : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
-end spi2dac;
+library verilog;
+use verilog.vl_types.all;
+entity spi2dac is
+    generic(
+        BUF             : vl_logic := Hi1;
+        GA_N            : vl_logic := Hi1;
+        SHDN_N          : vl_logic := Hi1;
+        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
+        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
+    );
+    port(
+        sysclk          : in     vl_logic;
+        data_in         : in     vl_logic_vector(9 downto 0);
+        load            : in     vl_logic;
+        dac_sdi         : out    vl_logic;
+        dac_cs          : out    vl_logic;
+        dac_sck         : out    vl_logic;
+        dac_ld          : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BUF : constant is 1;
+    attribute mti_svvh_generic_type of GA_N : constant is 1;
+    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
+    attribute mti_svvh_generic_type of TC : constant is 1;
+    attribute mti_svvh_generic_type of IDLE : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
+end spi2dac;
diff --git a/pin_assignment.txt b/pin_assignment.txt
index 04a3a75..4a576a0 100755
--- a/pin_assignment.txt
+++ b/pin_assignment.txt
@@ -1,211 +1,211 @@
-#============================================================
-# CLOCK
-#============================================================
-set_location_assignment PIN_AF14 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# Add-on Card Interface Pins
-#============================================================
-set_location_assignment PIN_AJ20 -to PWM_OUT
-set_location_assignment PIN_AK21 -to DAC_LD
-set_location_assignment PIN_AD20 -to DAC_CS
-set_location_assignment PIN_AF20 -to DAC_SCK
-set_location_assignment PIN_AF21 -to ADC_SCK
-set_location_assignment PIN_AG21 -to ADC_SDI
-set_location_assignment PIN_AG20 -to ADC_CS
-set_location_assignment PIN_AG18 -to DAC_SDI
-set_location_assignment PIN_AJ21 -to ADC_SDO
-set_location_assignment PIN_Y17 -to OLED_CS
-set_location_assignment PIN_Y18 -to OLED_RST
-set_location_assignment PIN_AK18 -to OLED_DC
-set_location_assignment PIN_AJ19 -to OLED_CLK
-set_location_assignment PIN_AJ16 -to OLED_DATA
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
-
-
-#============================================================
-# HEX0
-#============================================================
-set_location_assignment PIN_AE26 -to HEX0[0]
-set_location_assignment PIN_AE27 -to HEX0[1]
-set_location_assignment PIN_AE28 -to HEX0[2]
-set_location_assignment PIN_AG27 -to HEX0[3]
-set_location_assignment PIN_AF28 -to HEX0[4]
-set_location_assignment PIN_AG28 -to HEX0[5]
-set_location_assignment PIN_AH28 -to HEX0[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
-
-#============================================================
-# HEX1
-#============================================================
-set_location_assignment PIN_AJ29 -to HEX1[0]
-set_location_assignment PIN_AH29 -to HEX1[1]
-set_location_assignment PIN_AH30 -to HEX1[2]
-set_location_assignment PIN_AG30 -to HEX1[3]
-set_location_assignment PIN_AF29 -to HEX1[4]
-set_location_assignment PIN_AF30 -to HEX1[5]
-set_location_assignment PIN_AD27 -to HEX1[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
-
-#============================================================
-# HEX2
-#============================================================
-set_location_assignment PIN_AB23 -to HEX2[0]
-set_location_assignment PIN_AE29 -to HEX2[1]
-set_location_assignment PIN_AD29 -to HEX2[2]
-set_location_assignment PIN_AC28 -to HEX2[3]
-set_location_assignment PIN_AD30 -to HEX2[4]
-set_location_assignment PIN_AC29 -to HEX2[5]
-set_location_assignment PIN_AC30 -to HEX2[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
-
-#============================================================
-# HEX3
-#============================================================
-set_location_assignment PIN_AD26 -to HEX3[0]
-set_location_assignment PIN_AC27 -to HEX3[1]
-set_location_assignment PIN_AD25 -to HEX3[2]
-set_location_assignment PIN_AC25 -to HEX3[3]
-set_location_assignment PIN_AB28 -to HEX3[4]
-set_location_assignment PIN_AB25 -to HEX3[5]
-set_location_assignment PIN_AB22 -to HEX3[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
-
-#============================================================
-# HEX4
-#============================================================
-set_location_assignment PIN_AA24 -to HEX4[0]
-set_location_assignment PIN_Y23 -to HEX4[1]
-set_location_assignment PIN_Y24 -to HEX4[2]
-set_location_assignment PIN_W22 -to HEX4[3]
-set_location_assignment PIN_W24 -to HEX4[4]
-set_location_assignment PIN_V23 -to HEX4[5]
-set_location_assignment PIN_W25 -to HEX4[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
-
-#============================================================
-# HEX5
-#============================================================
-set_location_assignment PIN_V25 -to HEX5[0]
-set_location_assignment PIN_AA28 -to HEX5[1]
-set_location_assignment PIN_Y27 -to HEX5[2]
-set_location_assignment PIN_AB27 -to HEX5[3]
-set_location_assignment PIN_AB26 -to HEX5[4]
-set_location_assignment PIN_AA26 -to HEX5[5]
-set_location_assignment PIN_AA25 -to HEX5[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
-
-#============================================================
-# KEY
-#============================================================
-set_location_assignment PIN_AA14 -to KEY[0]
-set_location_assignment PIN_AA15 -to KEY[1]
-set_location_assignment PIN_W15 -to KEY[2]
-set_location_assignment PIN_Y16 -to KEY[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
-
-#============================================================
-# LEDR
-#============================================================
-set_location_assignment PIN_V16 -to LEDR[0]
-set_location_assignment PIN_W16 -to LEDR[1]
-set_location_assignment PIN_V17 -to LEDR[2]
-set_location_assignment PIN_V18 -to LEDR[3]
-set_location_assignment PIN_W17 -to LEDR[4]
-set_location_assignment PIN_W19 -to LEDR[5]
-set_location_assignment PIN_Y19 -to LEDR[6]
-set_location_assignment PIN_W20 -to LEDR[7]
-set_location_assignment PIN_W21 -to LEDR[8]
-set_location_assignment PIN_Y21 -to LEDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
-
-#============================================================
-# SW
-#============================================================
-set_location_assignment PIN_AB12 -to SW[0]
-set_location_assignment PIN_AC12 -to SW[1]
-set_location_assignment PIN_AF9 -to SW[2]
-set_location_assignment PIN_AF10 -to SW[3]
-set_location_assignment PIN_AD11 -to SW[4]
-set_location_assignment PIN_AD12 -to SW[5]
-set_location_assignment PIN_AE11 -to SW[6]
-set_location_assignment PIN_AC9 -to SW[7]
-set_location_assignment PIN_AD10 -to SW[8]
-set_location_assignment PIN_AE12 -to SW[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
-
-#============================================================
-# End of pin and io_standard assignments
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
 #============================================================
 \ No newline at end of file
author	ymherklotz <ymherklotz@gmail.com>	2016-12-11 16:37:13 +0000
committer	ymherklotz <ymherklotz@gmail.com>	2016-12-11 16:37:13 +0000
commit	47665d0ff2ee13848f4b5b2e3a36d7f4e8b08731 (patch)
tree	3b6ca2e93e2ad9fd56d4286af311c3c880c09068
parent	137e647c057d471bd0a26fa037b1ef575a2568e7 (diff)
download	VerilogCoursework-47665d0ff2ee13848f4b5b2e3a36d7f4e8b08731.tar.gz VerilogCoursework-47665d0ff2ee13848f4b5b2e3a36d7f4e8b08731.zip