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module delay(clk, N, trigger, time_out);
parameter BIT_SZ = 7
input clk, trigger;
input [BIT_SZ-1:0] N;
output time_out;
reg[BIT_SZ-1:0] count;
reg time_out;
reg [1:0] state;
parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;
initial begin
state = IDLE;
count = N-1'b1;
end
always @ (posedge clk)
case(state)
IDLE: if(trigger == 1'b1)
state <= COUNTING;
COUNTING: if(count == 1'b0) begin
count <= n - 1'b1;
state <= TIME_OUT;
end
TIME_OUT: if(trigger == 1'b0)
state <= IDLE;
else
state <= WAIT_LOW;
WAIT_LOW: if(trigger == 1'b0)
state <= IDLE;
defualt: ;
endcase
always @ (*)
case(state)
IDLE: time_out = 1'b0;
COUNTING: time_out = 1'b0;
TIME_OUT: time_out = 1'b1;
WAIT_LOW: time_out = 1'b0;
default: ;
endcase
endmodule
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