1 files changed, 47 insertions, 0 deletions
diff --git a/part_2/ex9/verilog_files/delay.v.bak b/part_2/ex9/verilog_files/delay.v.bak
new file mode 100644
index 0000000..fb1cfab
--- /dev/null
+++ b/part_2/ex9/verilog_files/delay.v.bak
@@ -0,0 +1,47 @@
+module delay(clk, N, trigger, time_out);
+
+	parameter BIT_SZ = 7
+
+	input clk, trigger;
+	input [BIT_SZ-1:0] N;
+	output time_out;
+
+	reg[BIT_SZ-1:0] count;
+	reg time_out;
+
+	reg [1:0] state;
+
+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;
+
+	initial begin
+		state = IDLE;
+		count = N-1'b1;
+	end
+	
+	always @ (posedge clk)
+		case(state)
+			IDLE: if(trigger == 1'b1)
+					state <= COUNTING;
+			COUNTING: if(count == 1'b0) begin
+					count <= n - 1'b1;
+					state <= TIME_OUT;
+				end
+			TIME_OUT: if(trigger == 1'b0)
+					state <= IDLE;
+				else
+					state <= WAIT_LOW;
+			WAIT_LOW: if(trigger == 1'b0)
+					state <= IDLE;
+			defualt: ;
+		endcase
+		
+	always @ (*)
+		case(state)
+			IDLE: time_out = 1'b0;
+			COUNTING: time_out = 1'b0;
+			TIME_OUT: time_out = 1'b1;
+			WAIT_LOW: time_out = 1'b0;
+			default: ;
+		endcase
+
+endmodule
+\ No newline at end of file