adding first project and initial files

63 files changed, 367 insertions, 0 deletions

diff --git a/part_1/ex1/db/_cmp.kpt b/part_1/ex1/db/_cmp.kpt
new file mode 100644
index 0000000..454d272
--- /dev/null
+++ b/part_1/ex1/db/_cmp.kpt
diff --git a/part_1/ex1/db/ex1.(0).cnf.cdb b/part_1/ex1/db/ex1.(0).cnf.cdb
new file mode 100644
index 0000000..e600a11
--- /dev/null
+++ b/part_1/ex1/db/ex1.(0).cnf.cdb
diff --git a/part_1/ex1/db/ex1.(0).cnf.hdb b/part_1/ex1/db/ex1.(0).cnf.hdb
new file mode 100644
index 0000000..7d57a69
--- /dev/null
+++ b/part_1/ex1/db/ex1.(0).cnf.hdb
diff --git a/part_1/ex1/db/ex1.(1).cnf.cdb b/part_1/ex1/db/ex1.(1).cnf.cdb
new file mode 100644
index 0000000..c0402be
--- /dev/null
+++ b/part_1/ex1/db/ex1.(1).cnf.cdb
diff --git a/part_1/ex1/db/ex1.(1).cnf.hdb b/part_1/ex1/db/ex1.(1).cnf.hdb
new file mode 100644
index 0000000..b579b27
--- /dev/null
+++ b/part_1/ex1/db/ex1.(1).cnf.hdb
diff --git a/part_1/ex1/db/ex1.ae.hdb b/part_1/ex1/db/ex1.ae.hdb
new file mode 100644
index 0000000..e1dfcb9
--- /dev/null
+++ b/part_1/ex1/db/ex1.ae.hdb
diff --git a/part_1/ex1/db/ex1.asm.qmsg b/part_1/ex1/db/ex1.asm.qmsg
new file mode 100644
index 0000000..48b3c3e
--- /dev/null
+++ b/part_1/ex1/db/ex1.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479203384105 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479203384108 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 09:49:43 2016 " "Processing started: Tue Nov 15 09:49:43 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479203384108 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479203384108 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex1 -c ex1 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex1 -c ex1" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479203384108 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479203384923 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479203389932 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "892 " "Peak virtual memory: 892 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479203393520 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 09:49:53 2016 " "Processing ended: Tue Nov 15 09:49:53 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479203393520 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479203393520 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479203393520 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479203393520 ""}

diff --git a/part_1/ex1/db/ex1.asm.rdb b/part_1/ex1/db/ex1.asm.rdb
new file mode 100644
index 0000000..b6146dc
--- /dev/null
+++ b/part_1/ex1/db/ex1.asm.rdb
diff --git a/part_1/ex1/db/ex1.cbx.xml b/part_1/ex1/db/ex1.cbx.xml
new file mode 100644
index 0000000..4417b7d
--- /dev/null
+++ b/part_1/ex1/db/ex1.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>

+<LOG_ROOT>

+	<PROJECT NAME="ex1">

+	</PROJECT>

+</LOG_ROOT>

diff --git a/part_1/ex1/db/ex1.cmp.ammdb b/part_1/ex1/db/ex1.cmp.ammdb
new file mode 100644
index 0000000..114cc7c
--- /dev/null
+++ b/part_1/ex1/db/ex1.cmp.ammdb
diff --git a/part_1/ex1/db/ex1.cmp.bpm b/part_1/ex1/db/ex1.cmp.bpm
new file mode 100644
index 0000000..5af97fb
--- /dev/null
+++ b/part_1/ex1/db/ex1.cmp.bpm
diff --git a/part_1/ex1/db/ex1.cmp.cdb b/part_1/ex1/db/ex1.cmp.cdb
new file mode 100644
index 0000000..f8d2ef7
--- /dev/null
+++ b/part_1/ex1/db/ex1.cmp.cdb
diff --git a/part_1/ex1/db/ex1.cmp.hdb b/part_1/ex1/db/ex1.cmp.hdb
new file mode 100644
index 0000000..9939091
--- /dev/null
+++ b/part_1/ex1/db/ex1.cmp.hdb
diff --git a/part_1/ex1/db/ex1.cmp.idb b/part_1/ex1/db/ex1.cmp.idb
new file mode 100644
index 0000000..174bc1b
--- /dev/null
+++ b/part_1/ex1/db/ex1.cmp.idb
diff --git a/part_1/ex1/db/ex1.cmp.logdb b/part_1/ex1/db/ex1.cmp.logdb
new file mode 100644
index 0000000..6387fe4
--- /dev/null
+++ b/part_1/ex1/db/ex1.cmp.logdb
@@ -0,0 +1,51 @@
+v1

+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,

+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,

+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,

+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,

+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,

+IO_RULES_MATRIX,Total Pass,11;0;11;0;0;11;11;0;11;11;0;7;0;0;0;0;7;0;0;0;0;7;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Inapplicable,0;11;0;11;11;0;0;11;0;0;11;4;11;11;11;11;4;11;11;11;11;4;11;11;11;11;11;11,

+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_SUMMARY,Total I/O Rules,28,

+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,

+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,

+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,

+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19,

diff --git a/part_1/ex1/db/ex1.cmp.rdb b/part_1/ex1/db/ex1.cmp.rdb
new file mode 100644
index 0000000..c33a804
--- /dev/null
+++ b/part_1/ex1/db/ex1.cmp.rdb
diff --git a/part_1/ex1/db/ex1.cmp_merge.kpt b/part_1/ex1/db/ex1.cmp_merge.kpt
new file mode 100644
index 0000000..83afb45
--- /dev/null
+++ b/part_1/ex1/db/ex1.cmp_merge.kpt
diff --git a/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100644
index 0000000..5b115d6
--- /dev/null
+++ b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100644
index 0000000..3a7a497
--- /dev/null
+++ b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100644
index 0000000..aa473fa
--- /dev/null
+++ b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100644
index 0000000..acc52a8
--- /dev/null
+++ b/part_1/ex1/db/ex1.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_1/ex1/db/ex1.db_info b/part_1/ex1/db/ex1.db_info
new file mode 100644
index 0000000..a96dd54
--- /dev/null
+++ b/part_1/ex1/db/ex1.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Tue Nov 15 09:24:05 2016

diff --git a/part_1/ex1/db/ex1.fit.qmsg b/part_1/ex1/db/ex1.fit.qmsg
new file mode 100644
index 0000000..89644f0
--- /dev/null
+++ b/part_1/ex1/db/ex1.fit.qmsg
@@ -0,0 +1,43 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479203350480 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479203350482 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex1 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex1\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479203350790 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479203350854 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479203350854 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479203351272 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479203351823 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479203361959 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203361980 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479203362001 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479203362001 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479203362001 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479203362002 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479203362002 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479203362002 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479203362003 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479203362004 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479203362004 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203362018 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex1.sdc " "Synopsys Design Constraints File file not found: 'ex1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1479203367610 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1479203367611 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1479203367612 ""}

+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1479203367612 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479203367613 ""}

+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1479203367613 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1479203367613 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479203367618 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479203367696 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203368226 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479203368593 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479203368841 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203368841 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479203369463 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "H:/VERI/part_1/ex1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479203373739 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479203373739 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479203373919 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479203373919 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479203373919 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203373922 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.07 " "Total time spent on timing analysis during the Fitter is 0.07 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479203375238 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479203375282 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479203375620 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479203375620 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479203375919 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479203377837 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/VERI/part_1/ex1/output_files/ex1.fit.smsg " "Generated suppressed messages file H:/VERI/part_1/ex1/output_files/ex1.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479203378187 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2539 " "Peak virtual memory: 2539 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479203380178 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 09:49:40 2016 " "Processing ended: Tue Nov 15 09:49:40 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479203380178 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Elapsed time: 00:00:32" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479203380178 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479203380178 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479203380178 ""}

diff --git a/part_1/ex1/db/ex1.hier_info b/part_1/ex1/db/ex1.hier_info
new file mode 100644
index 0000000..224e60b
--- /dev/null
+++ b/part_1/ex1/db/ex1.hier_info
@@ -0,0 +1,73 @@
+|ex1

+HEX0[0] <= My7seg:inst.out[0]

+HEX0[1] <= My7seg:inst.out[1]

+HEX0[2] <= My7seg:inst.out[2]

+HEX0[3] <= My7seg:inst.out[3]

+HEX0[4] <= My7seg:inst.out[4]

+HEX0[5] <= My7seg:inst.out[5]

+HEX0[6] <= My7seg:inst.out[6]

+SW[0] => My7seg:inst.in[0]

+SW[1] => My7seg:inst.in[1]

+SW[2] => My7seg:inst.in[2]

+SW[3] => My7seg:inst.in[3]

+

+

+|ex1|My7seg:inst

+out[0] <= inst37.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= inst32.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= inst27.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= inst23.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= inst16.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= inst14.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= inst7.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => inst3.IN0

+in[0] => inst21.IN2

+in[0] => inst20.IN2

+in[0] => inst35.IN3

+in[0] => inst36.IN3

+in[0] => inst34.IN3

+in[0] => inst30.IN3

+in[0] => inst29.IN2

+in[0] => inst12.IN2

+in[0] => inst13.IN3

+in[0] => inst11.IN2

+in[0] => inst1.IN3

+in[0] => inst15.IN2

+in[0] => inst8.IN1

+in[1] => inst4.IN0

+in[1] => inst21.IN1

+in[1] => inst22.IN2

+in[1] => inst25.IN2

+in[1] => inst26.IN2

+in[1] => inst36.IN2

+in[1] => inst31.IN1

+in[1] => inst29.IN1

+in[1] => inst10.IN2

+in[1] => inst12.IN1

+in[1] => inst1.IN2

+in[2] => inst19.IN1

+in[2] => inst21.IN0

+in[2] => inst5.IN0

+in[2] => inst25.IN1

+in[2] => inst24.IN1

+in[2] => inst33.IN1

+in[2] => inst35.IN1

+in[2] => inst28.IN1

+in[2] => inst30.IN1

+in[2] => inst31.IN0

+in[2] => inst13.IN1

+in[2] => inst1.IN1

+in[2] => inst2.IN1

+in[2] => inst9.IN1

+in[3] => inst6.IN0

+in[3] => inst22.IN0

+in[3] => inst25.IN0

+in[3] => inst24.IN0

+in[3] => inst35.IN0

+in[3] => inst36.IN0

+in[3] => inst28.IN0

+in[3] => inst29.IN0

+in[3] => inst13.IN0

+in[3] => inst2.IN0

+

+

diff --git a/part_1/ex1/db/ex1.hif b/part_1/ex1/db/ex1.hif
new file mode 100644
index 0000000..3eeb213
--- /dev/null
+++ b/part_1/ex1/db/ex1.hif
diff --git a/part_1/ex1/db/ex1.lpc.html b/part_1/ex1/db/ex1.lpc.html
new file mode 100644
index 0000000..75daae6
--- /dev/null
+++ b/part_1/ex1/db/ex1.lpc.html
@@ -0,0 +1,34 @@
+<TABLE>

+<TR  bgcolor="#C0C0C0">

+<TH>Hierarchy</TH>

+<TH>Input</TH>

+<TH>Constant Input</TH>

+<TH>Unused Input</TH>

+<TH>Floating Input</TH>

+<TH>Output</TH>

+<TH>Constant Output</TH>

+<TH>Unused Output</TH>

+<TH>Floating Output</TH>

+<TH>Bidir</TH>

+<TH>Constant Bidir</TH>

+<TH>Unused Bidir</TH>

+<TH>Input only Bidir</TH>

+<TH>Output only Bidir</TH>

+</TR>

+<TR >

+<TD >inst</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+</TABLE>

diff --git a/part_1/ex1/db/ex1.lpc.rdb b/part_1/ex1/db/ex1.lpc.rdb
new file mode 100644
index 0000000..5008357
--- /dev/null
+++ b/part_1/ex1/db/ex1.lpc.rdb
diff --git a/part_1/ex1/db/ex1.lpc.txt b/part_1/ex1/db/ex1.lpc.txt
new file mode 100644
index 0000000..ec1e423
--- /dev/null
+++ b/part_1/ex1/db/ex1.lpc.txt
@@ -0,0 +1,7 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Legal Partition Candidates                                                                                                                                                                                     ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; inst      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

diff --git a/part_1/ex1/db/ex1.map.ammdb b/part_1/ex1/db/ex1.map.ammdb
new file mode 100644
index 0000000..174eb00
--- /dev/null
+++ b/part_1/ex1/db/ex1.map.ammdb
diff --git a/part_1/ex1/db/ex1.map.bpm b/part_1/ex1/db/ex1.map.bpm
new file mode 100644
index 0000000..2b712e8
--- /dev/null
+++ b/part_1/ex1/db/ex1.map.bpm
diff --git a/part_1/ex1/db/ex1.map.cdb b/part_1/ex1/db/ex1.map.cdb
new file mode 100644
index 0000000..91d305e
--- /dev/null
+++ b/part_1/ex1/db/ex1.map.cdb
diff --git a/part_1/ex1/db/ex1.map.hdb b/part_1/ex1/db/ex1.map.hdb
new file mode 100644
index 0000000..9261c7d
--- /dev/null
+++ b/part_1/ex1/db/ex1.map.hdb
diff --git a/part_1/ex1/db/ex1.map.kpt b/part_1/ex1/db/ex1.map.kpt
new file mode 100644
index 0000000..d18a67e
--- /dev/null
+++ b/part_1/ex1/db/ex1.map.kpt
diff --git a/part_1/ex1/db/ex1.map.logdb b/part_1/ex1/db/ex1.map.logdb
new file mode 100644
index 0000000..d45424f
--- /dev/null
+++ b/part_1/ex1/db/ex1.map.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_1/ex1/db/ex1.map.qmsg b/part_1/ex1/db/ex1.map.qmsg
new file mode 100644
index 0000000..8d7aa08
--- /dev/null
+++ b/part_1/ex1/db/ex1.map.qmsg
@@ -0,0 +1,14 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479203336217 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479203336221 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 09:48:55 2016 " "Processing started: Tue Nov 15 09:48:55 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479203336221 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479203336221 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479203336221 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479203336789 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479203336790 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bdf_files/my7seg.bdf 1 1 " "Found 1 design units, including 1 entities, in source file bdf_files/my7seg.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 My7seg " "Found entity 1: My7seg" {  } { { "BDF_Files/My7seg.bdf" "" { Schematic "H:/VERI/part_1/ex1/BDF_Files/My7seg.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479203345325 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479203345325 ""}

+{ "Warning" "WSGN_FILE_IS_MISSING" "BDF_Files/ex1_top.bdf " "Can't analyze file -- file BDF_Files/ex1_top.bdf is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1479203345328 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bdf_files/ex1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file bdf_files/ex1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ex1 " "Found entity 1: ex1" {  } { { "BDF_Files/ex1.bdf" "" { Schematic "H:/VERI/part_1/ex1/BDF_Files/ex1.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479203345333 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479203345333 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex1 " "Elaborating entity \"ex1\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479203345387 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "My7seg My7seg:inst " "Elaborating entity \"My7seg\" for hierarchy \"My7seg:inst\"" {  } { { "BDF_Files/ex1.bdf" "inst" { Schematic "H:/VERI/part_1/ex1/BDF_Files/ex1.bdf" { { 224 840 1056 320 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479203345414 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479203346281 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479203346968 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479203346968 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479203347426 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479203347426 ""} { "Info" "ICUT_CUT_TM_LCELLS" "7 " "Implemented 7 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479203347426 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479203347426 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "882 " "Peak virtual memory: 882 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479203347524 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 09:49:07 2016 " "Processing ended: Tue Nov 15 09:49:07 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479203347524 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479203347524 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479203347524 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479203347524 ""}

diff --git a/part_1/ex1/db/ex1.map.rdb b/part_1/ex1/db/ex1.map.rdb
new file mode 100644
index 0000000..c9bff7e
--- /dev/null
+++ b/part_1/ex1/db/ex1.map.rdb
diff --git a/part_1/ex1/db/ex1.map_bb.cdb b/part_1/ex1/db/ex1.map_bb.cdb
new file mode 100644
index 0000000..4bbea3d
--- /dev/null
+++ b/part_1/ex1/db/ex1.map_bb.cdb
diff --git a/part_1/ex1/db/ex1.map_bb.hdb b/part_1/ex1/db/ex1.map_bb.hdb
new file mode 100644
index 0000000..4fbdade
--- /dev/null
+++ b/part_1/ex1/db/ex1.map_bb.hdb
diff --git a/part_1/ex1/db/ex1.map_bb.logdb b/part_1/ex1/db/ex1.map_bb.logdb
new file mode 100644
index 0000000..d45424f
--- /dev/null
+++ b/part_1/ex1/db/ex1.map_bb.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_1/ex1/db/ex1.pplq.rdb b/part_1/ex1/db/ex1.pplq.rdb
new file mode 100644
index 0000000..8627bdd
--- /dev/null
+++ b/part_1/ex1/db/ex1.pplq.rdb
diff --git a/part_1/ex1/db/ex1.pre_map.cdb b/part_1/ex1/db/ex1.pre_map.cdb
new file mode 100644
index 0000000..372b591
--- /dev/null
+++ b/part_1/ex1/db/ex1.pre_map.cdb
diff --git a/part_1/ex1/db/ex1.pre_map.hdb b/part_1/ex1/db/ex1.pre_map.hdb
new file mode 100644
index 0000000..717a0a9
--- /dev/null
+++ b/part_1/ex1/db/ex1.pre_map.hdb
diff --git a/part_1/ex1/db/ex1.root_partition.map.reg_db.cdb b/part_1/ex1/db/ex1.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..4fa69f7
--- /dev/null
+++ b/part_1/ex1/db/ex1.root_partition.map.reg_db.cdb
diff --git a/part_1/ex1/db/ex1.routing.rdb b/part_1/ex1/db/ex1.routing.rdb
new file mode 100644
index 0000000..c469cb8
--- /dev/null
+++ b/part_1/ex1/db/ex1.routing.rdb
diff --git a/part_1/ex1/db/ex1.rtlv.hdb b/part_1/ex1/db/ex1.rtlv.hdb
new file mode 100644
index 0000000..050e289
--- /dev/null
+++ b/part_1/ex1/db/ex1.rtlv.hdb
diff --git a/part_1/ex1/db/ex1.rtlv_sg.cdb b/part_1/ex1/db/ex1.rtlv_sg.cdb
new file mode 100644
index 0000000..99ab5a6
--- /dev/null
+++ b/part_1/ex1/db/ex1.rtlv_sg.cdb
diff --git a/part_1/ex1/db/ex1.rtlv_sg_swap.cdb b/part_1/ex1/db/ex1.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..f5bfe0a
--- /dev/null
+++ b/part_1/ex1/db/ex1.rtlv_sg_swap.cdb
diff --git a/part_1/ex1/db/ex1.sld_design_entry.sci b/part_1/ex1/db/ex1.sld_design_entry.sci
new file mode 100644
index 0000000..92c1102
--- /dev/null
+++ b/part_1/ex1/db/ex1.sld_design_entry.sci
diff --git a/part_1/ex1/db/ex1.sld_design_entry_dsc.sci b/part_1/ex1/db/ex1.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..92c1102
--- /dev/null
+++ b/part_1/ex1/db/ex1.sld_design_entry_dsc.sci
diff --git a/part_1/ex1/db/ex1.smart_action.txt b/part_1/ex1/db/ex1.smart_action.txt
new file mode 100644
index 0000000..437a63e
--- /dev/null
+++ b/part_1/ex1/db/ex1.smart_action.txt
@@ -0,0 +1 @@
+DONE

diff --git a/part_1/ex1/db/ex1.sta.qmsg b/part_1/ex1/db/ex1.sta.qmsg
new file mode 100644
index 0000000..ad0b311
--- /dev/null
+++ b/part_1/ex1/db/ex1.sta.qmsg
@@ -0,0 +1,61 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479203395401 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479203395405 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 09:49:54 2016 " "Processing started: Tue Nov 15 09:49:54 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479203395405 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203395405 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex1 -c ex1 " "Command: quartus_sta ex1 -c ex1" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203395406 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203395628 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396254 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396254 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396301 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396301 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex1.sdc " "Synopsys Design Constraints File file not found: 'ex1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396936 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396937 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396938 ""}

+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396939 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396940 ""}

+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396942 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203396945 ""}

+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203396989 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203397009 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397012 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397057 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397080 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397103 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397123 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397145 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203397178 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397238 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397753 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397847 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397847 ""}

+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397847 ""}

+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397847 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397848 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397882 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397900 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397919 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397939 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203397959 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203397987 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398340 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398761 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398849 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398849 ""}

+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398849 ""}

+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398849 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398867 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398884 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398907 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398928 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203398949 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479203398975 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399311 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399311 ""}

+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399311 ""}

+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399313 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399329 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399347 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399365 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399386 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203399403 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203401578 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203401579 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1173 " "Peak virtual memory: 1173 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479203402045 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 09:50:02 2016 " "Processing ended: Tue Nov 15 09:50:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479203402045 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479203402045 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479203402045 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479203402045 ""}

diff --git a/part_1/ex1/db/ex1.sta.rdb b/part_1/ex1/db/ex1.sta.rdb
new file mode 100644
index 0000000..b4f2a86
--- /dev/null
+++ b/part_1/ex1/db/ex1.sta.rdb
diff --git a/part_1/ex1/db/ex1.sta_cmp.6_slow_1100mv_85c.tdb b/part_1/ex1/db/ex1.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100644
index 0000000..9b8e12b
--- /dev/null
+++ b/part_1/ex1/db/ex1.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_1/ex1/db/ex1.taw.rdb b/part_1/ex1/db/ex1.taw.rdb
new file mode 100644
index 0000000..1728c3f
--- /dev/null
+++ b/part_1/ex1/db/ex1.taw.rdb
diff --git a/part_1/ex1/db/ex1.tis_db_list.ddb b/part_1/ex1/db/ex1.tis_db_list.ddb
new file mode 100644
index 0000000..88225e8
--- /dev/null
+++ b/part_1/ex1/db/ex1.tis_db_list.ddb
diff --git a/part_1/ex1/db/ex1.tiscmp.fast_1100mv_0c.ddb b/part_1/ex1/db/ex1.tiscmp.fast_1100mv_0c.ddb
new file mode 100644
index 0000000..bf20fad
--- /dev/null
+++ b/part_1/ex1/db/ex1.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_1/ex1/db/ex1.tiscmp.fast_1100mv_85c.ddb b/part_1/ex1/db/ex1.tiscmp.fast_1100mv_85c.ddb
new file mode 100644
index 0000000..6e45a2b
--- /dev/null
+++ b/part_1/ex1/db/ex1.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_1/ex1/db/ex1.tiscmp.slow_1100mv_0c.ddb b/part_1/ex1/db/ex1.tiscmp.slow_1100mv_0c.ddb
new file mode 100644
index 0000000..6231e30
--- /dev/null
+++ b/part_1/ex1/db/ex1.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_1/ex1/db/ex1.tiscmp.slow_1100mv_85c.ddb b/part_1/ex1/db/ex1.tiscmp.slow_1100mv_85c.ddb
new file mode 100644
index 0000000..08123f8
--- /dev/null
+++ b/part_1/ex1/db/ex1.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_1/ex1/db/ex1.tmw_info b/part_1/ex1/db/ex1.tmw_info
new file mode 100644
index 0000000..46ba178
--- /dev/null
+++ b/part_1/ex1/db/ex1.tmw_info
@@ -0,0 +1,3 @@
+start_analysis_synthesis:s:00:00:13-start_full_compilation

+start_analysis_elaboration:s-start_full_compilation

+start_fitter:s:00:00:35-start_full_compilation

diff --git a/part_1/ex1/db/ex1.vpr.ammdb b/part_1/ex1/db/ex1.vpr.ammdb
new file mode 100644
index 0000000..6dccbfa
--- /dev/null
+++ b/part_1/ex1/db/ex1.vpr.ammdb
diff --git a/part_1/ex1/db/ex1_partition_pins.json b/part_1/ex1/db/ex1_partition_pins.json
new file mode 100644
index 0000000..4a972c2
--- /dev/null
+++ b/part_1/ex1/db/ex1_partition_pins.json
@@ -0,0 +1,53 @@
+{

+	"partitions" : [

+		{

+			"name" : "Top",

+			"pins" : [

+				{

+					"name" : "HEX0[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[0]",

+					"strict" : false

+				},

+				{

+					"name" : "SW[2]",

+					"strict" : false

+				},

+				{

+					"name" : "SW[3]",

+					"strict" : false

+				},

+				{

+					"name" : "SW[1]",

+					"strict" : false

+				},

+				{

+					"name" : "SW[0]",

+					"strict" : false

+				}

+			]

+		}

+	]

+}
\ No newline at end of file
diff --git a/part_1/ex1/db/prev_cmp_ex1.qmsg b/part_1/ex1/db/prev_cmp_ex1.qmsg
new file mode 100644
index 0000000..d3fbe2f
--- /dev/null
+++ b/part_1/ex1/db/prev_cmp_ex1.qmsg
@@ -0,0 +1,11 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479203131490 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Elaboration Quartus Prime " "Running Quartus Prime Analysis & Elaboration" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479203131493 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 09:45:31 2016 " "Processing started: Tue Nov 15 09:45:31 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479203131493 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479203131493 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1 --analysis_and_elaboration " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex1 -c ex1 --analysis_and_elaboration" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479203131493 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479203132012 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479203132012 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bdf_files/my7seg.bdf 1 1 " "Found 1 design units, including 1 entities, in source file bdf_files/my7seg.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 My7seg " "Found entity 1: My7seg" {  } { { "BDF_Files/My7seg.bdf" "" { Schematic "H:/VERI/part_1/ex1/BDF_Files/My7seg.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479203140592 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1479203140592 ""}

+{ "Warning" "WSGN_FILE_IS_MISSING" "BDF_Files/ex1_top.bdf " "Can't analyze file -- file BDF_Files/ex1_top.bdf is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Design Software" 0 -1 1479203140595 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bdf_files/ex1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file bdf_files/ex1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ex1 " "Found entity 1: ex1" {  } { { "BDF_Files/ex1.bdf" "" { Schematic "H:/VERI/part_1/ex1/BDF_Files/ex1.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479203140599 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Design Software" 0 -1 1479203140599 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex1 " "Elaborating entity \"ex1\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Design Software" 0 -1 1479203140636 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "My7seg My7seg:inst " "Elaborating entity \"My7seg\" for hierarchy \"My7seg:inst\"" {  } { { "BDF_Files/ex1.bdf" "inst" { Schematic "H:/VERI/part_1/ex1/BDF_Files/ex1.bdf" { { 224 840 1056 320 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Design Software" 0 -1 1479203140689 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Elaboration 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Elaboration was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "837 " "Peak virtual memory: 837 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479203141232 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 09:45:41 2016 " "Processing ended: Tue Nov 15 09:45:41 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479203141232 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479203141232 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479203141232 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479203141232 ""}