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| author | zedarider <ymherklotz@gmail.com> | 2016-11-15 21:33:02 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-11-15 21:33:02 +0000 |
| commit | ee5d729de8ea22b4d7524bf839ba08fcb4b3843d (patch) | |
| tree | a6cbbd40144834affb26acfeaaa8e9159b7cf4a9 /part_1/ex1/output_files/ex1.map.summary | |
| download | VerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.tar.gz VerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.zip | |
adding first project and initial files
Diffstat (limited to 'part_1/ex1/output_files/ex1.map.summary')
| -rw-r--r-- | part_1/ex1/output_files/ex1.map.summary | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/part_1/ex1/output_files/ex1.map.summary b/part_1/ex1/output_files/ex1.map.summary new file mode 100644 index 0000000..8f09a10 --- /dev/null +++ b/part_1/ex1/output_files/ex1.map.summary @@ -0,0 +1,17 @@ +Analysis & Synthesis Status : Successful - Tue Nov 15 09:49:07 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex1
+Top-level Entity Name : ex1
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 0
+Total pins : 11
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
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