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authorzedarider <ymherklotz@gmail.com>2016-11-15 21:33:02 +0000
committerzedarider <ymherklotz@gmail.com>2016-11-15 21:33:02 +0000
commitee5d729de8ea22b4d7524bf839ba08fcb4b3843d (patch)
treea6cbbd40144834affb26acfeaaa8e9159b7cf4a9 /part_1/ex2/output_files/ex2.asm.rpt
downloadVerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.tar.gz
VerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.zip
adding first project and initial files
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+Assembler report for ex2
+Tue Nov 15 10:38:51 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: H:/VERI/part_1/ex2/output_files/ex2.sof
+ 6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Tue Nov 15 10:38:51 2016 ;
+; Revision Name ; ex2 ;
+; Top-level Entity Name ; ex2 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++-----------------------------------------+
+; Assembler Generated Files ;
++-----------------------------------------+
+; File Name ;
++-----------------------------------------+
+; H:/VERI/part_1/ex2/output_files/ex2.sof ;
++-----------------------------------------+
+
+
++-------------------------------------------------------------------+
+; Assembler Device Options: H:/VERI/part_1/ex2/output_files/ex2.sof ;
++----------------+--------------------------------------------------+
+; Option ; Setting ;
++----------------+--------------------------------------------------+
+; Device ; 5CSEMA5F31C6 ;
+; JTAG usercode ; 0x00AF7D85 ;
+; Checksum ; 0x00AF7D85 ;
++----------------+--------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Tue Nov 15 10:38:42 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex2 -c ex2
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 896 megabytes
+ Info: Processing ended: Tue Nov 15 10:38:52 2016
+ Info: Elapsed time: 00:00:10
+ Info: Total CPU time (on all processors): 00:00:06
+
+