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| author | zedarider <ymherklotz@gmail.com> | 2016-11-15 21:33:02 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-11-15 21:33:02 +0000 |
| commit | ee5d729de8ea22b4d7524bf839ba08fcb4b3843d (patch) | |
| tree | a6cbbd40144834affb26acfeaaa8e9159b7cf4a9 /part_1/ex4/ex4.v | |
| download | VerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.tar.gz VerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.zip | |
adding first project and initial files
Diffstat (limited to 'part_1/ex4/ex4.v')
| -rw-r--r-- | part_1/ex4/ex4.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/part_1/ex4/ex4.v b/part_1/ex4/ex4.v new file mode 100644 index 0000000..e92e969 --- /dev/null +++ b/part_1/ex4/ex4.v @@ -0,0 +1,16 @@ +module ex4(SW, HEX0, HEX1, HEX2, HEX3);
+
+ input [9:0] SW;
+ output [6:0] HEX0, HEX1, HEX2, HEX3;
+
+ wire [3:0] w0, w1, w2, w3;
+
+ bin2bcd_10(SW, w0, w1, w2, w3);
+
+ hex_to_7seg(HEX0, w0);
+ hex_to_7seg(HEX1, w1);
+ hex_to_7seg(HEX2, w2);
+ hex_to_7seg(HEX3, w3);
+
+
+endmodule
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