adding full files to github, with all updates

5 files changed, 58 insertions, 58 deletions

diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_info b/part_2/ex5/simulation/modelsim/rtl_work/_info
index 9a0155e..9a599cc 100755
--- a/part_2/ex5/simulation/modelsim/rtl_work/_info
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_info
@@ -1,25 +1,25 @@
-m255

-K3

-13

-cModel Technology

-Z0 dC:\New folder\simulation\modelsim

-vcounter_8

-!i10b 1

-!s100 ;ldZ:oUkgLo?@Aa7ibdbm2

-Ia91@O_<g0BVIc?WTzTbB62

-Vdn7aTnOzPKdeZA;zmQ`Cl3

-Z1 dC:\New folder\simulation\modelsim

-w1479807538

-8C:/New folder/verilog_files/counter_8.v

-FC:/New folder/verilog_files/counter_8.v

-L0 3

-OV;L;10.1d;51

-r1

-!s85 0

-31

-!s108 1479807676.024000

-!s107 C:/New folder/verilog_files/counter_8.v|

-!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/verilog_files|C:/New folder/verilog_files/counter_8.v|

-!s101 -O0

-o-vlog01compat -work work -O0

-!s92 -vlog01compat -work work {+incdir+C:/New folder/verilog_files} -O0

+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\simulation\modelsim
+vcounter_8
+!i10b 1
+!s100 ;ldZ:oUkgLo?@Aa7ibdbm2
+Ia91@O_<g0BVIc?WTzTbB62
+Vdn7aTnOzPKdeZA;zmQ`Cl3
+Z1 dC:\New folder\simulation\modelsim
+w1479807538
+8C:/New folder/verilog_files/counter_8.v
+FC:/New folder/verilog_files/counter_8.v
+L0 3
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1479807676.024000
+!s107 C:/New folder/verilog_files/counter_8.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/verilog_files|C:/New folder/verilog_files/counter_8.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/verilog_files} -O0
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_vmake b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
index b51b305..2f7e729 100755
--- a/part_2/ex5/simulation/modelsim/rtl_work/_vmake
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
@@ -1,3 +1,3 @@
-m255

-K3

-cModel Technology

+m255
+K3
+cModel Technology
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
index 8ada04e..0dd84bc 100755
--- a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
@@ -1,14 +1,14 @@
-library verilog;

-use verilog.vl_types.all;

-entity counter_8 is

-    generic(

-        BIT_SZ          : integer := 8

-    );

-    port(

-        clock           : in     vl_logic;

-        enable          : in     vl_logic;

-        count           : out    vl_logic_vector

-    );

-    attribute mti_svvh_generic_type : integer;

-    attribute mti_svvh_generic_type of BIT_SZ : constant is 1;

-end counter_8;

+library verilog;
+use verilog.vl_types.all;
+entity counter_8 is
+    generic(
+        BIT_SZ          : integer := 8
+    );
+    port(
+        clock           : in     vl_logic;
+        enable          : in     vl_logic;
+        count           : out    vl_logic_vector
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BIT_SZ : constant is 1;
+end counter_8;
diff --git a/part_2/ex5/simulation/modelsim/tb_counter b/part_2/ex5/simulation/modelsim/tb_counter
index 4544d6a..6256691 100755
--- a/part_2/ex5/simulation/modelsim/tb_counter
+++ b/part_2/ex5/simulation/modelsim/tb_counter
@@ -1,9 +1,9 @@
-add wave clock enable

-add wave -hexadecimal count

-force clock 0 0, 1 10ns -repeat 20ns

-force enable 1

-run 100ns

-force enable 0

-run 100ns

-force enable 1

+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
 run 1000
\ No newline at end of file
diff --git a/part_2/ex5/simulation/modelsim/tb_counter.do b/part_2/ex5/simulation/modelsim/tb_counter.do
index 4544d6a..6256691 100755
--- a/part_2/ex5/simulation/modelsim/tb_counter.do
+++ b/part_2/ex5/simulation/modelsim/tb_counter.do
@@ -1,9 +1,9 @@
-add wave clock enable

-add wave -hexadecimal count

-force clock 0 0, 1 10ns -repeat 20ns

-force enable 1

-run 100ns

-force enable 0

-run 100ns

-force enable 1

+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
 run 1000
\ No newline at end of file