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| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_2/ex6/ex6.sdc | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_2/ex6/ex6.sdc')
| -rwxr-xr-x | part_2/ex6/ex6.sdc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/part_2/ex6/ex6.sdc b/part_2/ex6/ex6.sdc new file mode 100755 index 0000000..f902c4a --- /dev/null +++ b/part_2/ex6/ex6.sdc @@ -0,0 +1 @@ +create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
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